JP2873033B2 - Column selection circuit - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention is in the field of integrated circuits, and more particularly to decoder circuits for integrated storage circuits.

This invention was made with government support under Department of Defense Contract 001-86-C-0090. The government has rights in the invention.

2. Description of the Related Art A storage element array in a conventional random access storage device (RAM) is generally arranged in independently selectable rows and columns. The selected address signal appearing at the address terminal of the device is decoded by a row decoder to select a column of the storage element array that leads to a sense amplifier. Other address signals are decoded by a column decoder to select one or more bits in a selected column from which to read or write data. Thus, the column decoder in a conventional RAM will eventually perform a multiplexing operation to select one of many possible bits in the selected column.

Referring to FIG. 1, a common column decoding and demultiplexing scheme illustrating one of the four choices is shown. Signals A0 and A0- are mutually logical complements and constitute the least significant bits of the two address signals, and similarly signals A1 and A1- represent the true and false states of the second least significant bit. The AND gate 10 ₀ to 10 ₃ are connected to various combinations of the four true and false address lines, producing a high logic level corresponding to the appropriate combination of address signals at its input. For example
The output of the AND gate 10 ₂ corresponding to the A0 and A1- address line is high (the address A2) becomes high. AN
If the output from the D gate 10 is high, to connect the data lines D ₀ from the passage control transistor 12 ₀ its associated until 12 ₃ corresponds to coming to the D ₃ to the line OUT. For example, from the data lines D ₀ to D ₃ are the data line to be driven by the four sense amplifiers in the RAM device, in the case of the circuit of FIG. 1 is adapted to select the application of line OUT. It is instead from the line D ₀ to D _3, before sensing to be an actual bit line of that storage device using a single sense amplifier for storage or multiple columns. As shown in FIG. 1, the transistor 14 is connected between the line OUT and the power supply V _dd, the signal PC at the gate of transistor 14 to precharge the line OUT is at the high to V _dd. Then line OUT remains high if the data state from the line D ₀ to D ₃ is pulled down if the row (pulled to ground potential) Luke, or selected data line is high. As is well known in the art, if even drive a direct line OUT from the data lines D ₀ to D ₃ (or discharge or maintained), logic - is to discharge the line OUT and the gate sequentially discharge the capacitor in the event of row You can also. Many other implementation issues of the column decoder shown in FIG. 1 can, of course, be implemented using a domino theory implementation or other pass control gate concept including precharge-discharge schemes. In addition, a greater number of pass control gates are used to decode a greater number of address lines, and one or more from a much greater number of data line groups 8 (eg, 128 groups) than the four shown in FIG. You can also choose bits.

Exposure of the device containing the circuit as shown in FIG. 1 to transient gamma radiation causes the passage control transistor 12,
Further, the precharge transistor 14 is normally conductive even if it is nonconductive because of photoconductivity. If these transistors conduct when they should be non-conductive, the logic state of the selected data lines D ₀ through D ₃ will cause the V _dd power supply to drive line OUT high due to the photoconduction of transistor 14 and to pull the line OUT by light conduction passage control transistor 12 selected not from the data lines D ₀ to D ₃ lines related to their logic level, the state of the line OUT may become unreasonable.
If reaches the value of the current flowing through one of the passage control transistor 12 ₀ the sum is selected for light conduction current of the transistor 14 and the selected non passes control transistor 12 to 12 _3, it may occur in error. In the worst case where this kind of events occurred in the circuit of FIG. 1, for example, selected data line D ₀ is a row - becomes a logic level, high from the data line D ₁ which is not selected to D ₃ - a logic level . 4 transistors to be non-conductive, 14 and 12 ₁
If the reached value of the current flowing through the passage control transistor 12 ₀ the sum is selected photoconductive current flowing up to 12 _3, the logic appearing on the data lines D ₀ - level of the row will not be detected.

Accordingly, it is an object of the present invention to provide a control transistor with greater resistance to photoconduction, such as in the event of gamma ray radiation, which would conduct when it should be non-conductive. A column decoder circuit is provided.

Another object of the present invention is to provide a column decoder having a multi-stage configuration so that a weak output from the preceding stage can be strengthened in the subsequent stage, and further improve the resistance of the device to transient radiation.

It is yet another object of the present invention to provide a column decoder with fewer fan-in and fan-out stages, thereby reducing switching time versus temperature sensitivity.

Other objects and advantages of the present invention will become apparent to those of ordinary skill in the art upon reading the following specification with reference to the drawings.

The present invention may be incorporated in a multi-stage column decoder where each stage accepts a group of data lines and a group of decoded address signals from a previous stage or from a first stage array of storage elements. it can. Within each stage, logic is provided for gating each of the data lines corresponding to its associated decoded address signal. If the decoded address line is used for a data line, the state of the data line drives the tri-state driver, and the unused address lines drive the tri-state driver to a high impedance state. The high impedance state of the unselected drivers separates their data lines from the decoder stage and causes the transient conduction to conduct light rather than high or low, pulling the circuit out to the output node towards the intermediate rail. Increases resistance. The multi-stage design increases the power of each stage and recovers logic levels from certain stages that have been degraded by transient radiation events.

Embodiment Referring now to FIG. 2, the stage 20 of the column decoder according to the present invention will be described. For purposes of explanation, stage 20 of FIG. 2 will be described as the stage closest to the storage element array, and it will be described later that this same design is equally applicable to the subsequent stages of the multi-stage column decoder.

Stage 20, like the decoder shown in FIG. 1 receives a signal on the data line from D ₀ to D _3. stage
20 receives from D ₀ at terminal OUT ₂₀ from the address input COL0 for selecting one of the data lines to the D ₃ to COL3. As for the address signal on lines COL0 to COL3, one of lines COL0 to COL3 is affirmed (that is, high-level).
Logic level and the) selecting from the four data lines D ₀ One to D _3, three other four address lines COL0~3 is not affirmative (i.e. row - is decoded so that a logic level) Address signal. Therefore the second
From the line COL0 in FIG up COL3 corresponds to the output of the AND gate from the four 10 ₀ shown in FIG. 1 to 10 _3.

Stage 20 four sub-stage, from 20 ₀ can be considered as composed of up to 20 _3, each of the data lines D ₀ One to D _3, and the address lines COL0 corresponding thereto to COL3 Receive one of As for the sub-stage 20 _0, NAND gate 22 ₀ is the data line D ₀ at one input, and receives an address line COL0 corresponding thereto in other input. NAND gate 22
The output of ₀ is coupled to the gate of the p- channel transistors 24 ₀ gate and n- channel transistors 28 _0,. Address lines COL0 is connected directly to the gate of the n- channel transistors 26 _0. Transistors 24 ₀ , 26
₀ and 28 ₀ are power supply node V _dd and the source are connected in series between the ground - constituted by a drain between paths, p- channel transistors 24 ₀ three transistors 24 _0, 26 ₀ and 28 ₀ the role of the pull-up transistor of a push-pull driver, n- channel transistor 28 ₀ as a pull-down transistor, also the transistor 26 ₀ to serve as an isolation transistor. The output of substage 20 ₀ is in the node between the transistors 24 ₀ and 28 ₀ of the drain, the node is connected directly to the output exits Ah line OUT ₂₀ of the stage 20.

Operation when, if the address line COL0 is affirmed to choose the data lines D _0, NAND gate 22 ₀ is the logical complement of the logic state of the data line D _0. Transistor if line COL0 is at high-logic level
26 ₀ serves as a code conversion push-pull driver in response to the logic state of the output of the NAND gate 22 ₀ conducting. Therefore, when selected, appear (inverted twice) logic state of the data line D ₀ is the node between the drains of transistors 24 ₀ and 26 _0, the output of the stage 20 line
You will meet at OUT ₂₀ .

Address of the data line from D ₀ to D ₃ line COL0
The unselected line corresponding to CLO3 goes to a low-logic level. For example for the sub-stage 20 _1, address line COL0 is high - line COL1 If the logic level is low. Thus the output of NAND gate 22 ₀ is independently of forced high level of the state of the data line D _1, to turn off the transistor 24 _1. Furthermore, the line COL1 is low - by the logic level, the transistor 26 ₁ is turned off, which is connected between the transistors 24 ₁ and 28 ₁ of the drain. Taking the example where data line D ₀ is selected, line OUT ₂₀ is connected to transistors 24 ₁ and 28 ₁
Is turned off, isolating it from the _Vdd and ground nodes of the substage. In this example, substage 20 ₂
When 20 ₃ similarly row address lines COL2 and COL2 - Since the logic levels, 24 and respective transistors
26 can substage 20 ₀ turned off drives the line OUT _20.

As is well known in the art, transient radiation events cause, above all other effects, source-to-drain photoconduction of MOS transistors that should normally be off. As discussed above with respect to the circuit of FIG. 1, the effect of photoconductivity to or from one logic state may make the reading or writing of another logic state grainy. The circuit of FIG. 2, 20 ₀ to 20 ₃
Transistors 24 and 26, which should be normally off of the sub-stage not selected before, tend to conduct. If this kind of event occurs in the circuit of FIG. 2, the line OU
T ₂₀ will try Komimo tension to a value between a certain voltage somewhere V _dd ground. The example shown in FIG.
Are decoded from the seven column address signals A to A6 into a single output bit. For a 128 column array. As described for Figure 2, each of the stage 20 receives the 4 of the data lines from D ₀ to D _127, thus in the embodiment of FIG. 3 32 sets of the stage 20 is present. Four address lines, (in COL _n third FIG) COL3 from COL0, one according to the value of the line A ₀ and A ₁ on the address signals - of - Fore (one-of-four) decoder, it is formed by 29, Leads to each of 32 stages 2.

A group of the second stage 30 has the same configuration as the stage 20 of FIG. 2, but in this embodiment, one-of-eight (one out of eight) is used.
Make a selection). Thus, in the embodiment of FIG. 3, there are four second stages, 30. Each of the second stages 30 receives the outputs of the eight sets of stages 20 as data inputs. The second stage four by the corresponding address lines 34 _n, appear in each of the 30, one of which one corresponds to the value of the address signals on the address lines from A ₂ to A ₄ - positive by Eight decoder - of Is done. In this way, 4 sets of 2nd
Each of the stages 30 selects and outputs one data state of its associated stage, 20.

The third stage, 40, makes the final selection of the bit to be read. The third stage 40 is also the stage 20 shown in FIG.
And receives the outputs from the four second stages 30 as its data inputs. Third stage, one formed by the value on the address lines A5 and A6 - of - receiving a corresponding address signal on line 44 _n from Fore decoder. One is thus second stage selected among the data lines from D ₀ to D _127, communicates with the line OUT through the stage 20 selected by one selected of 30.

With the multi-stage selection completed by the circuit of FIG. 3, the deteriorated signal from the previous stage is recovered. Returning to FIG.
Quite high by one of the NAND gate 22 one data state selected among the data lines from D ₀ to D ₃ is equivalent to - or no wax - is inverted to either logic level. For the second stage, 30 or third stage, 40, the NAND gate receiving the output signal from the selected previous stage does not degrade and its logic level has dropped to an intermediate value (inaccurate). As far as possible, the same inversion processing is performed. Selected sub-stage, since the transistors 24 and 28 in the 20 _n inverts where the output of the NAND gate 22 completely, is any degradation of the signal received from the preceding stage second stage constructed in accordance with the present invention, 30 and the 3 steps, 40
Removed by Also, the use of multi-stage processing (reduction of fan-in and fan-out) also enhances the degraded signal due to high temperature operation, thus making the circuit performance more stable over a given temperature range. .

It should further be noted that the embodiment of the stage shown in FIG. 2 can be used as a one-stage decoder in devices with a small number of data lines or where transient immunity is not an issue. That's what it means. As noted above for the embodiment of FIG. 1, drives the out selected data line itself D ₃ from D ₀ or either the load capacitor line OUT of the sense amplifier (and stray capacitance of the transistor 14) However, either driving ability is often small considering the load to be driven. According to the design of FIG. 2, the voltage of the selected data line can be amplified to increase the communication speed to the output terminal of the selected storage element.

Although the present invention has been described in detail with reference to the embodiments, it is to be understood that this description is given by way of example only, and is not meant to limit the scope. It is also evident that the details of the embodiments of the invention have various changes and further embodiments of the present invention, and those of ordinary skill in the art will do so based on this description. You have to understand that you can. Such changes and further embodying them,
It is within the spirit and true scope of the following claims.

[Brief description of the drawings]

FIG. 1 is a wiring diagram showing, in the form of a system diagram, a conventional column decoder using a pass control gate method. FIG. 2 is a wiring diagram showing a column decode and selection circuit constructed according to the present invention in the form of a system diagram. FIG. 3 is a wiring diagram showing a three-stage column decode and selection circuit constructed according to the present invention in the form of a system diagram.

Claims (9)

(57) [Claims] 1. A column selection circuit in a column selector of a storage device, comprising: an input for receiving a data signal and an input for receiving a decoded address signal, and responding to the decoded address signal instructing selection of a data signal. A plurality of gates that output signals corresponding to the data signals, and a plurality of drivers that are connected to the gates and drive to a logic state according to the logic of the gates. Inputting the received address signal, and providing a separating means for setting the output to high impedance in response to the decoded address signal instructing non-selection of the data signal, wherein the outputs of the plurality of drivers are combined and selected. Column selection circuit that outputs the logic state of the data signal. 2. The driver comprises a pull-down transistor and a pull-up load connected to the gate, and the separating means includes an isolation transistor having a gate for inputting the decoded address signal. The isolation transistor becomes non-conductive in response to the decoded address signal instructing the non-selection of the data signal, and the source-drain path of the pull-up load and pull-down transistor and the isolation transistor are connected to the power supply node and the reference node. 2. The column selection circuit according to claim 1, wherein the column selection circuit is connected between them. 3. The pull-up load is a transistor having a gate connected to the output of the gate, and a source-drain path connected in series to a source-drain path of the pull-down transistor and the isolation transistor. 3. The column selection circuit according to claim 2, wherein: 4. Each of the gates is responsive to a decoded address signal indicating a non-selection of a data signal.
2. The column selection circuit according to claim 1, wherein the column selection circuit outputs a logic state of: 5. The plurality of drivers include a pull-down transistor and a pull-up transistor, and a gate of the pull-up transistor is connected to the gate,
The gate of the pull-down transistor receives the output of the gate and turns off the pull-up transistor in response to a decoded address signal instructing non-selection of a data signal. An isolation transistor having a gate for receiving the data signal. The isolation transistor is turned off in response to a decoded address signal instructing non-selection of a data signal, and the source and drain paths of the pull-down transistor are connected to the isolation transistor. A driver connected in series between a source-drain path of the transistor and a reference node; a source and drain path of the pull-up transistor connected in series between a source-drain path of the isolation transistor and a power supply node; Output Column selection circuit according to claim 4, characterized in that the connection point of the pull-up transistor and the isolation transistor. 6. A multi-stage column decoder for selecting a data line of a storage device in response to a column address signal, comprising: a first address signal decoder for decoding a predetermined number of bits of the column address signal; A second address signal decoder for decoding a predetermined number of bits of the column address signal other than the bits decoded by the one address signal decoder; and a plurality of data lines and an output of the first address signal decoder. And selecting a plurality of first data lines in response to an output of the first address signal decoder.
A selecting step, wherein the column decoder of the first selecting step has an input for receiving a data signal and an input for receiving a decoded address signal, and outputs a decoded address signal indicating selection of a data signal. A plurality of gates for outputting a signal corresponding to a data signal in response thereto; and a plurality of drivers connected to the gates for driving to a logic state according to the logic of the gates, the driver comprising: Separating means for inputting the selected address signal and setting a high impedance state in response to the composite address signal instructing non-selection of the data signal, wherein a plurality of drivers of the column decoder in the first selection stage are provided. The outputs are connected together to represent the output of the first selection stage, and the column decoder of the second selection stage includes a plurality of outputs of the first selection stage and a second address signal decod. Is connected to the output of da, multistage column decoder, characterized in that it is configured to select the output of the first selection step in response to the decoded address signal from said second address signal decoder. 7. The second selection stage column decoder has an input for receiving one of the outputs of the first selection stage, and an input for receiving an address signal decoded by the second address signal decoder. A plurality of gates for outputting a signal corresponding to the output of the first stage in response to a composite address signal instructing selection of a data signal; and a plurality of gates connected to the gate and driven to a logic state according to the logic of the gate A driver for inputting the decoded address signal and setting a high impedance state in response to the composite address signal instructing non-selection of the output of the first selection stage. 7. The multi-stage as claimed in claim 6, wherein a plurality of drivers of the second selection stage are connected together to produce one selected output of the first selection stage. Ko Mudekoda. And a third decoder for decoding an address signal having a predetermined number of bits of the column address signal other than the bits decoded by the first and second address signal decoders. A third address signal decoder, an output of the second selection stage and an output of the third address signal decoder, and a plurality of second selection stages corresponding to decoded address signals from the third address signal decoder; 7. The multi-stage column decoder according to claim 6, comprising a third-stage column decoder for selecting one of the outputs. 9. A decoded signal having an input for receiving one of the outputs of the second selection stage and an input for receiving an address signal decoded by the third address signal decoder, and instructing selection of a data signal. A plurality of gates for outputting a signal corresponding to the output of the second stage in response to the address signal; and a driver connected to the gate and driving to a logic state according to the logic of the gate. Comprises separating means for inputting the decoded address signal and setting a high impedance state in response to the combined address signal instructing non-selection of the output of the second selection step, 9. The multi-stage column decoder according to claim 8, wherein said drivers are connected together to produce a selected one output of said second selection stage.