JP2870202B2 - Method and apparatus for mutual monitoring between processors - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for monitoring between processors in a computer system comprising a plurality of processors.

[0002]

2. Description of the Related Art In a computer system composed of a plurality of processors, each processor usually has a self-diagnosis function. When a self-abnormality is detected, the occurrence of the abnormality is notified to another processor. I have.

With this self-diagnosis function, for example, in a computer system that controls a certain machine, when a controlling processor detects its own abnormality, the other processor is notified of the occurrence of the abnormality and operates normally. Other processors can safely shut down the machine.

However, for example, in the case of a failure in which the processor itself stops operating, the self-diagnosis function does not work, of course, so that another processor cannot know the occurrence of the abnormality. there were.

Therefore, conventionally, the operation of a plurality of processors is mutually monitored so that even if one processor fails and the self-diagnosis function does not operate, another processor can detect the abnormality of the processor. I have.

Hereinafter, at least two processors A and B
A conventional mutual monitoring method will be described using an example of a multiprocessor system composed of the common memories C and D accessed by these processors.

FIGS. 11 to 15 show a conventional mutual monitoring method.
The processing contents of the processor A and the processor B in FIG.
It is a flowchart. In this processor system,
Period t in processor A₀, T₁For mutual monitoring every time
Are executed, and the processor B is executed.
At the period t _Two, T_ThreeA program for mutual monitoring every time
B-1 and B-2 are executed.

First, the processing on the processor A side will be described with reference to FIGS. The processor A, the program A-1 shown in FIG. 11 every period t ₀ is activated.
In the program A-1, the common memory C is cleared to "0" as shown in step S1 of FIG.

Furthermore, the processor A, the program A-2 shown in FIG. 12 for each period t ₁ is started. In the program A-2, the data in the common memory C is read in step S2, and it is determined in next step S3 whether the data read this time matches the data read last time.

If the data does not match, the common memory C
Is incremented by "1" by a program B-1 on the processor B side, which will be described later. In this case, in step S4, it is determined that the processor B is operating normally, and the processing is performed. Terminate.

On the other hand, if it is determined in step S3 that the data read this time matches the data read last time, it is determined in step 5 that the data in the common memory C has not been incremented due to some abnormality in the processor B. And terminate the process.

Next, processing on the processor B side will be described with reference to FIGS. The processor B, program B-1 shown in FIG. 13 every cycle t ₂ is executed.
In the program B-1, the data in the common memory C is read in step S6 in FIG. 13, and the value is incremented in the next step S7. Further, in step S8, the incremented data is written to the common memory C.

In the processor B, a program B-2 shown in FIG. 14 is executed every cycle t ₃ . In the program B-2, the common memory C in step S9 in FIG.
Is read, and it is determined in the next step S10 whether or not the data is less than a specified value.

When the data in the common memory C is less than the specified value, the contents of the common memory C incremented by "1" by the above-mentioned program B-1 on the processor B side are changed by the program A-1 on the processor A side. Period t ₀
This is the case when it is cleared every time.

In this case, it is determined in step S11 that the processor A is operating normally, and the process is terminated. On the other hand, if the data in the common memory C is equal to or more than the specified value in the determination in step S10, the data in the common memory C is incremented by the program B-1 in a state where the program A-1 is not executed and the common memory C is not cleared. This is the case when it exceeds the specified value.

In this case, it is determined in step S12 that an error has occurred in the processor A, and the specified value is written to the common memory C in the next step S13, and the process is terminated.

[0017] Incidentally, when the activation period t ₃ of the program B-1 activation period t ₂ and Program B-2 are equal, together into one the programs, to create the program B-0 shown in FIG. 15 be able to.

In this program B-0, step S1
In step S15, the data in the common memory C is read out.
Then, it is determined whether or not the data read out is smaller than a specified value. If the read data is less than the specified value, step S16
Determines that the processor A is operating normally, increments the data in the common memory C by "1" in the next step S17, writes the data in the common memory C in step S18, and ends the processing. I do.

[0019] On the other hand, data of the common memory C is greater than or equal to the prescribed value
In step S19, it is determined that an error has occurred in the processor A in step S19, a specified value is set in the next step S20, and the specified value is written in the common memory C in step S18, and the process is terminated. I do.

Next, the operation of the processor when the processors A and B are normal or when the processor A or B has an abnormality will be described with reference to the operation time charts of FIGS.

[0021] When processor A, B are operating normally, as shown in operation timing chart of FIG. 16, the data of the common memory C every period t ₂ by the program B-1 is increased by one "1", Further, the contents of the common memory C are cleared every cycle t ₀ by the program A-1.

At this time, the change in the value of the common memory C can be detected by the program A-2 executed in the processor A at each cycle t ₁ , so that the processor B
Can be determined to be operating normally.

Further, although not shown in FIG. 16, a program executed in each cycle t ₃ in processor B B-
According to 2, it is possible to detect that the data in the common memory C is less than the specified value, so that it can be determined that the processor A is operating normally.

Next, an operation when an abnormality occurs in the processor A will be described with reference to an operation time chart of FIG. When an error occurs in the processor A, the processor B
Although the contents of the common memory C are incremented by the program B-1 on the side of FIG. 17, since the contents of the common memory C are not cleared to “0” by the program A-1, FIG.
The value of the common memory C gradually increases as shown in FIG.

As a result, in the processor B, the period t ₃
The common memory C is executed by the program B-2 executed every time.
Is detected to be equal to or greater than the specified value, and the processor A
Is determined to be abnormal.

Next, an operation when an abnormality occurs in the processor B will be described with reference to an operation time chart of FIG. When an abnormality occurs in the processor B, the value of the common memory C is not incremented by the above-described program B-1, and the value of the common memory C becomes a constant value as shown in FIG.

As a result, the coincidence between the data read this time from the common memory C and the data read last time is detected by the program A-1 executed by the processor A every cycle t ₁ , and the processor B is determined to be abnormal. You.

Even if an error occurs in the processor B, when the data in the common memory C is read and compared before and after the common memory C is cleared by the processor A, the present data and the previous data do not match. Therefore, there is a case where the processor B is determined to be normal.

Even in this case, if the comparison of the data in the common memory C in the program A-2 is repeated a plurality of times, if an abnormality has occurred in the processor B, the data in the common memory C after clearing is cleared. Since the content becomes a constant value “0”, the abnormality of the processor B can be reliably detected.

Note that the starting cycle t _{0 of} each program,
t ₁ and t ₂ need to satisfy the following relationship. The condition of t ₀ > t ₂ t ₁ > t ₂ t ₁ ≠ n × t ₀ (n = 1, 2,...) is a condition for increasing the data of the common memory C in a normal state. The condition is a condition that the previous read data of the common memory C does not match the present read data in the normal state.

[0031]

However, in the above-described conventional mutual monitoring method, when the processor A and the processor B are operating asynchronously, a problem arises when the program is started, for example, at the timing shown in FIG. .

As shown in FIG. 19, if the processor A clears the common memory C to "0" immediately after the processor B has read the data in the common memory C, then the program B-1 reads the data. The incremented data is incremented, and the incremented data is written to the common memory C.

As a result, the data in the common memory C is not cleared, and the data continues to increase. When the data exceeds the specified value, the program B-2 erroneously determines that an abnormality has occurred in the processor A.

An object of the present invention is to provide a method and apparatus for mutual monitoring between processors which can accurately detect the operating state of the processors in a system including a plurality of processors.

[0035]

FIG. 1 is a diagram illustrating the principle of the present invention. An inter-processor mutual monitoring method used in a system including a plurality of processors and common memories C and D accessible from the plurality of processors, wherein processors A and B monitoring the operation among the plurality of processors. Processor A writes a message to the common memory D every cycle t ₀ . Further, the data in the common memory C is read every cycle t _1, and the data read this time and the data read last time are compared. If the data does not match, the processor B determines that the data is normal. Is determined to be abnormal.

If the other processor B is shorter than the period t ₁
Reads the message of the common memory D to have each period t _2,
The presence or absence of a message from the processor A is determined, and if a message exists, the common memory C is cleared or specified.
A value is set, and if there is no message, the data in the common memory C is incremented or decremented. Further, the data in the common memory C is compared with the reference value, and if the data is within the reference value, the processor A is determined to be normal, and if the data exceeds the reference value, the processor A is determined to be abnormal.

[0037]

According to the mutual monitoring method of the present invention, the other processor B clears or increments (or decrements) the data in the common memory C depending on whether one processor A has written a predetermined message in the common memory D or not. I did it.

Therefore, the contents of the common memory C are not cleared during the increment (or decrement) of the data in the common memory C, for example, by the start timing of the program as in the related art. In addition, it is possible to prevent erroneous determination of an abnormality while the processor is operating normally.

[0039]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a configuration diagram of the processor system according to the first embodiment of the present invention. Processor card A (for example,
A board on which a processor A is mounted) and N processor cards B (hereinafter, an arbitrary processor on this card is referred to as a processor B _M (M = 1, 2,... N)). The common memory cards X that are commonly accessed are connected via a system bus E, respectively.

Processor card A and processor card B
Means that data is exchanged with each other via the common memory card X. There are a number of data storage areas in the common memory card X.
Message is written by a common memory D in which the message is read by the processor B _M, cleared or incremented by the processor B _M (or decrement), N pieces of the common memory C _M, the contents of which are read by the processor A ( M = 1, 2, 3, ...
N) etc. are provided.

In this embodiment, N common memories _CM are provided to detect the presence or absence of an abnormality in the N processors B. Next, the processors A and B _M of the first embodiment
3 to 6 about the mutual monitoring program executed in
This will be described with reference to the flowchart of FIG.

FIG. 3 is a flowchart of the program A-1 executed by the processor A every cycle t ₀ . The program A-1 is a program for writing “0” or “1” as a message in the common memory D.

First, in step S21 of FIG. 3, it is determined whether or not "0" was previously written in the common memory D as a message. If "0" has been previously written to the common memory D, the process proceeds to step S22, and this time the common memory D
"1" as a message.

On the other hand, if "1" was previously written to the common memory D, the process proceeds to step S23, and "0" is written to the common memory D this time as a message. Here, in the program A-1, "0" and "1" are alternately written as a message in the common memory D because it is possible to determine whether the processor A is operating normally on the processor _BM side. It is to do so.

FIG. 4 is a flowchart of a program A-2 executed by the processor A at each cycle t ₁ . The program A-2 includes a data read current from the common memory C _M, by comparing the data previously read is a process for detecting an abnormality of the processor B _M.

Firstly, it reads the data of the common memory C _M in step S24 in FIG. 4. Then comparing the common memory C _M data and the previous read data read out this time in step S25, it is determined whether they match.

If the data do not match, step S2
At 6, it is determined that the processor _BM is operating normally, and the process ends. On the other hand, if the data matches,
Not executed program B _M -1, which will be described later in the processor B _M, the case where the value of the common memory C _M is not incremented in this case determines that an abnormality has occurred in the processor B _M in step S27, the processing To end.

Next, FIG. 5 is a flowchart of the program B _M -1 executed by the processor B _M every cycle t ₂ . The program B _M -1 is a process for clearing or incrementing the common memory C _M depending on whether the value of the common memory D is the same as the previous value.

First, the contents of the common memory D are read in step S28 in FIG. Then, in step S29, the content of the common memory D read this time is compared with the content of the common memory D read last time, and it is determined whether or not they match.

When the contents of the common memory D do not match,
In the case where the program A-1 described above by the processor A is executed, it has been rewritten alternately value of the common memory D from "0" to "1" or from "1" every period t ₀ to "0" Yes, in this case, to clear the common memory C _M to "0", the flow proceeds to step S30, and the process ends.

On the other hand, when the values of the common memory D match, the program A-1 is not executed during the time t ₀ and the value of the common memory D is not rewritten. the common memory C _M proceeds to S31 is incremented "1", the process ends.

FIG. 6 is a flowchart of a program B _M -2 executed by the processor B _M every cycle t ₃ . The program B _M -2 compares the data in the common memory C _M with a specified value (reference value) to generate the processor A _M.
This is a process for detecting abnormalities in the data.

[0053] First, reading the data of the common memory C _M in step S32 in FIG. 6. Next, in step S33, data of the common memory C _M read it is determined whether or not less than a specified value.

When the data in the common memory C _M is less than the specified value, the content of the common memory D is rewritten by the processor A every cycle t ₀ , and based on the result, the program B _M -1 causes the fixed cycle t _2. Common memory C _{M for} each
Is cleared to “0”.

In this case, it is determined in step S34 that the processor A is operating normally, and the process is terminated. On the other hand, when the data of the common memory C _M is equal to or larger than the predetermined value, in order by a program A-1 has not been rewritten because of the common memory D, is incremented common memory C _M by a program B _M -1 specified value This is the case when the above is reached.

[0056] store that in this case, it is determined that an abnormality has occurred in the processor A in step S35, an abnormality in the processor A has occurred further by setting the specified value to the common memory C _M in the next step S36 I do.

Next, with reference to the shared register D and the operation time charts in FIGS. 7-9 showing the temporal change in the value of C _M when the above program by the processor A and B _M is executed, The operation of each processor will be described.

First, the operation of the processors when the processors A and B _M are normal will be described with reference to the operation time chart of FIG. After rewriting the data value of the common memory D processor A in a certain time to execute the program A-1 from "1" to "0", the processor B _M is the executing the program B _M -1. In this case, the value read this time from the common memory D does not match the value read last time, so the program B _M -1 clears the common memory _CM to “0”.

[0059] Next t ₀ time to the program A-1 is executed, the value of the common memory D remains unchanged at "0", the program B _M -1 by between processor B _M
There the value of the common memory C _M different runs is gradually increased sequentially.

After the period t ₀ , the program A-
When 1 is executed and the data value of the common memory D is rewritten from "0" to "1", the program B _M -1 detects a mismatch between the current read value and the previous read value of the common memory D, The common memory _CM is cleared to "0" again.

That is, when the processor A is operating normally, the value of the common memory D is changed from “1” to “0”.
Or from “0” to “1” alternately,
The common register D in the program B _M -1 on the processor B side
Is detected, and the common memory C is cleared. As a result, the value of the common memory C _M since suppressed below a predetermined value, it is determined that the processor A by the program B _M -2 is operating normally.

[0062] Also, when the processor B is operating properly, the value of the common memory C _M every period t ₂ by the program B _M -1 is incremented one by "1", the value of the common memory C _M Is detected by the program A-1 on the processor A side, and it is determined that the processor B is operating normally.

Next, the operation when abnormality occurs in the processor B _M, will be described with reference to an operation timing chart of FIG. When abnormality in the processor B _M is generated as shown in FIG. 8, the program B _M -1 processor B _M side from running, the value of the common memory C _M is not cleared or incremented. Therefore, a constant value does not increase the data value of the common memory C _M.

Then, the common memory C _M read out by the program A-2 executed by the processor A every cycle t ₁
The current read value and the previous read value match.
Thus the processor A can detect that an abnormality has occurred in the processor B _M.

Next, an operation when an abnormality occurs in the processor A will be described with reference to an operation time chart of FIG. As shown in FIG. 9, when an abnormality occurs in the processor A, the program A-1 on the processor A side is not executed, and the value of the common memory D cannot be rewritten. When the value of the common memory D stops changing, the value of the common memory C _M is not cleared to “0” by the program B _M −1 on the processor B side, and the value gradually increases.

As a result, it is detected by the program B _M -2 executed by the processor B _M every period t ₃ that the value of the common memory C _M has exceeded the specified value. Thereby, the processor B _M can detect that an abnormality has occurred in the processor A.

Here, the cause of the erroneous determination that the processor is abnormal by the conventional mutual monitoring method will be examined. In the conventional mutual monitoring method, immediately after the program B-1 of the processor B reads the data of the common memory C,
A problem occurs when the program A-1 of the processor A clears the value of the common memory C to "0".

That is, in the conventional mutual monitoring method, the common memory C is cleared by the program A-1 on the processor A side, and the common memory C is cleared by the program B-1 on the processor B side.
Is incremented, the value of the common memory C may increase depending on the activation timing of the two.

On the other hand, in the mutual monitoring method according to the present embodiment, the processor A determines whether or not the processor A has rewritten the message (in this case, “0” or “1”) in the common memory D. program B _M -1 are in the common memory C _M clear or increment the contents of (or decrement) it is so.

Therefore, the value of the common memory C _M cannot be increased in principle due to the start timing of the program, and the determination error can be completely eliminated. In addition,
In this embodiment, the processor A itself rewrites the value of the common memory D alternately from, for example, “0” to “1” (or “1” to “0”). Can be performed independently of the program on the processor B side.

Next, a second embodiment of the present invention will be described. This embodiment is basically has the same configuration as the system configuration of the first embodiment shown in FIG. 2, each processor A, also basic part each program to be executed by the B _M first embodiment Is the same as

Hereinafter, the characteristic portions of the second embodiment will be described. In this example, the program A-1 of the processor A side, writing the numerical data Y in the common memory D every period t _0.

[0073] Then, if the common memory D content numeric data Y, the processor B _M side program B _M -
1 clears the common memory D and the common memory _CM to “0” at every cycle t _3, and the content of the common memory D is set to the numerical data Y
Otherwise, being "1" at a time increments the value of the common memory C _M (or decrement).

The program A-2 and the program B _M
-2 is the same as that of the second embodiment. When, for example, an error occurs in the processor A and the numerical data Y is no longer written to the common memory D by the above-described program, the value of the common memory C _M is increased by the program B _M -1 on the processor B side, and the value becomes the specified value. At this point, it is determined that the processor A is abnormal.

Next, a third embodiment of the present invention will be described. FIG. 10 is a system configuration diagram of the processor system of the third embodiment. In this embodiment, the processor A is N
This is an example in the case where there is one processor B.

In FIG. 10, a processor card B on which a processor B is mounted, and N processors A _M (M =
, N) are connected to a common bus E.

In the common memory card X, one common memory C and N common memories D _M to which messages (for example, numerical values “1” or “0”) from the processor A _M are written are provided. I have.

Further, in the processor card B, N-1 memories C _M accessible by the processor B (in this embodiment, N-1 memories accessed by the processor B in the processor card B are stored in the memory). referred to as C _M) is provided.

The program A _M -1 executed on the processor A _M side is a process which is started every period t ₀ and writes “0” and “1” as messages in the common memory D _M alternately.

The program A _M -2 is started every cycle t ₁ , reads out the data in the common memory C, compares the data read out this time with the data read out last time. If so, the processor B determines that it is normal.

Program B Executed on Processor B
-1 is activated every period t _2, the common memory read the contents of the D _M, compares the read value and the present value previously read, if they match (if the message from processor A _M is absent) , The data of the memory C _M (including the common memory C, the same applies hereinafter) is incremented (or decremented), and if they do not match (when there is a message from the processor A _M ), the memory C is cleared to “0”. This is the processing to be performed.

[0082] Also, the program B-2 is activated every period t _3, compared with the data value of the memory C _M a specified value,
If the data value is smaller than the specified value, the processor A _M is judged to be normal, if the data is the specified value or higher, the processor A _M is the process of determining as abnormal.

The above first program is used by these programs.
Similarly to the second embodiment, the processor _AM and the processor B can detect an abnormality of each other.

[0084] In this embodiment, since the processor B is one, common memory C that must be read to detect the abnormality of the processor B from the N processors A _M is sufficient one. Therefore, the number of common memories C is set to one, and N-
Required to detect an abnormality in one of the processors A _M N-
One memory C (in attached to the remaining one processor A _M using a common memory C), are provided only accessible processor card B from the processor B.

[0085] Thus, the memory for detecting an abnormality of N processors A (corresponds to a common memory C _M of the first embodiment), always it is not necessary to the common memory, the memory in the processor card B Since the area can be used, the memory configuration becomes more free.

Next, a fourth embodiment of the present invention will be described. System configuration of this embodiment is the same as the system configuration of the third embodiment shown in FIG. 10, and each processor A _M,
The basic part of each program executed in B is the third part.
This is the same as the program of the embodiment. Hereinafter, the characteristic portions of the fourth embodiment will be described.

[0087] This example, processor A _M is writing numerical data Y as a message to the common memory D _M at fixed intervals. Then, when the numerical data Y is written in the common memory D _M , the processor B sends the common memory D _M and the memory C _M (the common memory C _{M) at} regular intervals.
And the same hereinafter) are cleared to "0", and when the numerical data Y is not written, the memory _CM is incremented.

[0088] The following describes a program to be executed by the processor A _M and B. The program A _M -1 executed by the processor A _M is started every period t ₀ and writes the numerical data Y to the common memory D _M.

Program B- Executed by Processor B
1 is activated every period t _2, reads the contents of the common memory D _M, if the read data is numerical data Y, clears the common memory D _M and memory C _M to "0", the read data is Otherwise numerical data Y, is a process that is incremented by "1" the memory C _M.

The program A _M -2 and the program B
-2 is the same as the program of the third embodiment. With these programs, when the processor A _M is operating normally and the numerical data Y is written in the common memory D _M , the data in the memory C _M is cleared to “0” at regular intervals, and data C _M becomes always less than the specified value. On the other hand, when an abnormality occurs in the processor A _M , the data in the memory C _M becomes equal to or more than the specified value, so that it is possible to determine without error whether the N processors A _M are normal.

[0091] Further, depending on whether the value of the memory C _M is changed, it is possible to determine whether the processor B is operating normally. As described above, in the above embodiment, in a processor system in which a plurality of processors operate asynchronously, at least two types of common memory areas are prepared (for example, a common memory C and a common memory D), and one processor A is fixed. For example, “0” or “1” is alternately written to the common memory D as a message in each cycle. When the message of the common memory D is rewritten by the processor A, the other processor B clears the value of another common memory C to "0", and when the message is not rewritten, the data of the common memory C is cleared. Is incremented (or decremented).

Thus, when the processor A is operating normally, the value of the common memory C does not increase, and only when an abnormality occurs in the processor A, the value of the common memory C becomes more than the specified value. . Therefore, by comparing the value of the common memory C with the specified value, the abnormality of the processor A can be accurately detected.

Further, whether or not the processor B is operating normally is detected based on whether or not the value of the common memory C has changed. Moreover, in the mutual monitoring method described above, one processor B clears or increments (or decrements) the common memory C to “0” based on a message written to the common memory D by the other processor A. ing.

Therefore, unlike the conventional mutual monitoring method, the problem that the value of the common memory C increases without being cleared by the start timing of the program does not occur, and the error in detecting the abnormality of the processor is eliminated. Can be.

In the above embodiment, one processor A
(Or B) and a processor system including a plurality of processors B _M (or A _M ) has been described. However, one processor A and B may be provided, respectively, or a plurality of processors A and B may be provided.

The message to be written to the common memory D is not limited to "0", "1" or numerical data described in the embodiment, and may be any message. One of the processors can write some information. Good.

[0097]

According to the present invention, in a system including a plurality of processors, it is possible to eliminate a detection error of an operating state of a processor caused by a timing of starting a program of each processor.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a system configuration diagram of a first embodiment of the present invention.

FIG. 3 is a flowchart of a program A-1 executed by a processor A of the embodiment.

FIG. 4 is a flowchart of a program A-2 executed by a processor A of the embodiment.

FIG. 5 is a flowchart of a program B _M -1 executed by the processor B _M of the embodiment.

FIG. 6 is a flowchart of a program B-2 executed by a processor B _M of the embodiment.

FIG. 7 is an operation time chart when the processors A and _BM are normal in the mutual monitoring method according to the embodiment.

8 is an operational time chart in the case where abnormality occurs in the processor B _M in mutual monitoring method in Example.

FIG. 9 is an operation time chart when an abnormality occurs in the processor A in the mutual monitoring method of the embodiment.

FIG. 10 is a system configuration diagram of a third embodiment.

FIG. 11 is a processing flowchart of a processor A in a conventional mutual monitoring method.

FIG. 12 is a processing flowchart of a processor A in a conventional mutual monitoring method.

FIG. 13 is a processing flowchart of a processor B in a conventional mutual monitoring method.

FIG. 14 is a processing flowchart of a processor B in a conventional mutual monitoring method.

FIG. 15 is a processing flowchart of the processor B when t ₃ = t ₂ .

FIG. 16 is an operation time chart when the processors A and B are normal in the conventional mutual monitoring method.

FIG. 17 is an operation time chart when an error occurs in the processor A in the conventional mutual monitoring method.

FIG. 18 is an operation time chart when an error occurs in the processor B by the conventional mutual monitoring method.

FIG. 19 is an explanatory diagram of a problem of the conventional mutual monitoring method.

[Explanation of symbols]

_{A, B, A M, B} M processor _{C, D, C M, D} M common memory C _i memory

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 15/16 G06F 11/00

Claims (4)

(57) [Claims] 1. A system comprising a plurality of processors and common memories C and D accessible from the plurality of processors.
A processor mutual monitoring method for use in a processor A, which monitors the operation together among the plurality of processors, one processor A and B, writes a message to the common memory D every period t ₀ The data in the common memory C is read every cycle t _1, and the data read this time and the data read last time are compared. If the data does not match, the processor B determines that the data is normal. It determines the abnormality, the other processor B, the common memory D short every period t ₂ than the previous year period t ₁
Is read and the presence or absence of a message from the processor A is determined. If a message is present, the common memory C is cleared or a predetermined value is set. Increments or decrements, compares the data in the common memory C with a reference value,
Processor A is determined to be normal if it is within the reference value Yue
The processor A determines that an abnormality has occurred, the mutual monitoring method between the processors. 2. At least one processor A and N processors B _M (M = 1, 2,... N), a common memory D accessible from the processors A and B _M and N common memories processor for use in a system comprising a C _M
Be between mutual monitoring, the processor A is writing a message to the common memory D every period t _0, it reads the data of the common memory C _M every period t _1,
Comparing the current read data and the previous data read, if the data mismatch, processor B _M which corresponds to the common memory C _M is determined to be normal, the processor B _M if the data are matched with the abnormality determination Then, the processor B _M transmits the common memory D every cycle t ₂ shorter than the previous cycle t _1.
Reading the contents, the processor determines whether the message from A, the message sets clear or predetermined value the contents of the common memory C _M, if present, the common memory if the message is not present C incrementing or decrementing the contents of the _M, it compares the data with a reference value of said common memory C _M, the processor a is determined to be normal if it is within the reference value, the reference value
The processor A determines that the processor A is abnormal if the number exceeds the threshold value . 3. The N processors A _M (M = 1, 2,...)
N), at least one processor B, N common memories D _M and at least one common memory C accessible from the processors A _M and B, and a plurality of memories C accessible from the processor B. Used for the system consisting of _i
Is a processor mutual monitoring, the processor A _M is, write messages to the common memory D _M for each period t _0, it reads the data of the common memory C every period t _1, read time data and the previous comparing the read data, the processor B is determined to be normal if the data mismatch, processor B if the data match, it is determined that the abnormality, the processor B is shorter each period t ₂ than the previous year period t ₁ The common memory D
Reads the contents of the _M, it is determined whether the message from processor A _M, clears the contents of the common memory C or the memory C _i corresponding to the processor A _M when a message is present or
Setting a predetermined value, if there are no messages will increment or decrement the contents of said common memory C or the memory C _i, comparing the data with a reference value of said common memory C and memory C _i, the reference value processor a _M is determined to be normal, processor <br/> if exceeds the reference value Sa a _M determines that abnormality, interprocessor mutual monitoring method characterized by corresponding to the memory if it is within. 4. A system comprising a plurality of processors and common memories C and D accessible from the plurality of processors, wherein one of the processors A and B monitors the operation among the plurality of processors. Processor A writes a message to the common memory D every cycle t ₀ , reads data from the common memory C every cycle t ₁ , compares the data read this time with the data read last time, and the data does not match. processor B is judged to be normal if the processor B if the data match, it is determined that the abnormality, the other processor B, the common memory D short every period t ₂ than the previous year period t ₁
Is read and the presence or absence of a message from the processor A is determined. If a message is present, the common memory C is cleared or a predetermined value is set. Increments or decrements, compares the data in the common memory C with a reference value,
Processor A is determined to be normal if it is within the reference value Yue
The processor A determines that an abnormality has occurred, and the mutual monitoring device between the processors.