JP2865486B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an internal step-down circuit for generating an internal power supply voltage by lowering an external power supply voltage and supplying the same to an internal memory circuit, and is a special mode of the semiconductor memory device. The present invention relates to a semiconductor memory device capable of realizing a stress mode function.

[0002]

2. Description of the Related Art In a conventional semiconductor memory device, a power supply voltage input from the outside is used as it is as a power supply voltage for driving an internal storage circuit. However, with the recent increase in the capacity of semiconductor memory devices, transistors have been miniaturized, and a method of stepping down an external power supply voltage has been widely proposed in order to improve its reliability and reduce current consumption. became.

In general, a semiconductor memory device includes a small number of defects due to miniaturization. At the time of manufacture, even a non-defective product is defective in a short period of use by a certain percentage. Therefore, the manufacturer usually performs continuous operation at high temperature / high voltage for several tens of hours to several days, and performs screening by selecting chips containing the above-mentioned defects in advance.
This high-temperature / high-voltage continuous operation test is called a burn-in test.

[0004] However, the internal step-down circuit generates a constant voltage as shown in FIG. Therefore, in a semiconductor memory device having a built-in internal voltage down converter, even if the external power supply voltage is increased, the internal power supply voltage becomes constant, and the burn-in test cannot be performed. Therefore, at the time of the burn-in test, there is a method of connecting the internal power supply voltage line and the external power supply voltage line and making the internal power supply voltage equal to the external power supply voltage as shown in FIG. The test function by this method is called a stress mode function.

FIG. 15 is a schematic block diagram showing an example of a semiconductor memory device having such a stress mode function. Referring to FIG. 15, this semiconductor memory device 100
Is an external power supply voltage terminal 101 for inputting an external power supply voltage,
It includes an internal step-down circuit 102 for stepping down an external power supply voltage, a memory circuit 103 driven by the internal power supply voltage stepped down by the internal step-down circuit 102, and a / SM terminal for inputting a stress mode signal / SM.

In operation, stress mode signal / SM
In response to the internal power supply voltage line 1
And internal power supply voltage line 2 are connected. As a result, an external power supply voltage is supplied to the memory circuit 103, and a burn-in test can be performed.

FIG. 16 is a circuit diagram showing a conventional internal voltage down converter having a function of equalizing an internal power supply voltage and an external power supply voltage.

In FIG. 16, an internal voltage down converter comprises an external power supply voltage line 1, an internal power supply voltage line 2, a level shifter circuit 3 for generating a voltage Vs shifted down from the level of the internal power supply voltage, and a constant internal power supply voltage. A reference voltage generating circuit 4 for generating a reference voltage Vref for generating a reference voltage Vref, a differential amplifier circuit 5 for amplifying a difference between the voltage Vs and the reference voltage Vref,
P connected between external power supply voltage line 1 and internal power supply voltage line 2 and turned on / off in response to the output of differential amplifier circuit 5
Channel transistor 6 and P-channel transistor 6
And a P-channel transistor 19 connected in parallel and turned on / off in response to stress mode signal / SM. The stress mode signal / SM is at a low level in the stress mode.

External power supply voltage line 1 is connected to external power supply terminal 101.
The internal power supply voltage line 2 is connected to a memory circuit (FIG. 1).
5).

The level shifter circuit 3 includes an internal power supply voltage line 1
And is activated in response to the stress mode signal / SM (high level) to lower the level of the internal power supply voltage by a predetermined voltage to generate the voltage Vs. This level shifter circuit 3
In response to the stress mode signal / SM (low level)
It becomes inactive. The voltage Vs is supplied to the differential amplifier circuit 5.

Reference voltage generating circuit 4 is activated in response to stress mode signal / SM (high level) to generate reference voltage V
ref is generated and inactivated in response to the stress mode signal / SM (low level). The reference voltage Vref is supplied to the differential amplifier circuit 5.

The differential amplifier circuit 5 has two input terminals and one output terminal. One input terminal is connected to receive the voltage Vs, and the other input terminal is connected to the reference voltage Vref.
And the output terminal is connected to the gate electrode of P-channel transistor 6. The differential amplifier circuit 5 compares the voltage Vs with the reference voltage Vref,
If f> Vs, a low-level signal is output and Vre
If f <Vs, a high-level signal is output.

The P-channel transistor 6 has a drain (or source) connected to the external power supply voltage line 1, a source (or drain) connected to the internal power supply voltage line 2,
The gate electrode is connected to the output of the differential amplifier circuit 5.

The P-channel transistor 19 has a drain (or source) connected to the external power supply voltage line 1, a source (or drain) connected to the internal power supply voltage line 2,
The gate electrode is connected to receive stress mode signal / SM.

The P-channel transistors 6 and 19
Since it is necessary to supply a power supply voltage to the memory circuit 103, its current driving capability is increased and it has a relatively large size.

Next, the operation of the voltage drop circuit shown in FIG. 16 will be described.

The level of the internal power supply voltage is reduced by the level shifter circuit 3 to become the voltage Vs. This voltage Vs
Is lower than the reference voltage Vref, the output of the differential amplifier circuit 5 becomes low. In response to this low level output, P-channel transistor 6 is turned on, and external power supply voltage line 1 and internal power supply voltage line 2 are connected.

Conversely, when the internal power supply voltage becomes high and the output voltage Vs of the level shifter circuit 3 becomes higher than the reference voltage Vref, the output of the differential amplifier circuit 5 becomes high level, and this high level P-channel transistor 6 is turned off in response to the signal, and external power supply voltage line 1 and internal power supply voltage line 2 are disconnected.

As described above, the on / off control of the P-channel transistor 6 allows the internal power supply voltage to be kept constant.

Next, in the stress mode, the stress mode signal / SM goes low, and the P-channel transistor 19 turns on. On the other hand, the level shifter circuit 3, the reference voltage generating circuit 4, and the differential amplifier circuit 5 become inactive, and the output of the differential amplifier circuit 5 becomes high. In response, P-channel transistor 6 is turned off, and external power supply voltage line 1 and internal power supply voltage line 2 are connected to P-channel transistor 1.
9.

As a result, an external power supply voltage can be applied to the internal memory circuit in the stress mode.

[0022]

As described above,
In the conventional internal voltage down converter, in the stress mode (stress mode signal / SM is high), P-channel transistor 6 turns on / off between external power supply voltage line 1 and internal power supply voltage line 2 to maintain a constant value. An internal power supply voltage is generated, and in a stress mode, an external power supply voltage line and an internal power supply voltage line are connected by a P-channel transistor 19. Since the two relatively large transistors 6 and 19 are used, there is a problem that the area of the internal voltage down converter and thus the semiconductor memory device increases.

In the stress mode, the level shifter circuit 3, the reference voltage generation circuit 4, and the differential amplifier circuit 5 are inactivated. There is a problem that no stress is applied and a burn-in test cannot be performed on these circuits.

One object of the present invention is to reduce the area of an internal voltage down converter in a semiconductor memory device having an internal voltage down converter.

Another object of the present invention is to enable a burn-in test to be performed on an internal voltage down converter.

[0026]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: an internal memory circuit; an internal step-down circuit for generating an internal power supply voltage by lowering an external power supply voltage and supplying the generated internal power supply voltage to the internal memory circuit; A semiconductor memory device comprising:
The internal voltage down converter has a stress mode test function of applying an external power supply voltage to the internal storage circuit, and operates between an external power supply voltage line supplying the external power supply voltage and an internal power supply voltage line supplying the internal power supply voltage. Switching means for turning on / off the power supply, level lowering means for lowering the level of the internal power supply voltage, reference voltage generating means for generating a reference voltage for making the level of the internal power supply voltage constant, and the reference voltage generation Control means for comparing the reference voltage generated by the means with the internal power supply voltage dropped by the level lowering means and controlling on / off of the switching means based on the comparison result; Sometimes, it is always turned on.

According to a second aspect of the present invention, there is provided a semiconductor memory device comprising:
It includes the same switching means and level lowering means as in claim 1, and further includes first reference voltage generating means, pull-up means and control means.

The first reference voltage generating means generates a first reference voltage for keeping the internal power supply voltage constant.

The pull-up means pulls up the first reference voltage in the stress mode, and generates a second reference voltage having a higher potential than the internal power supply voltage dropped by the level lowering means.

The control means compares the generated first or second reference voltage with the dropped internal power supply voltage,
When the first or second reference voltage is higher than the dropped internal power supply voltage, the switching unit is turned on, and the first or second reference voltage is higher than the dropped internal power supply voltage. If it is also lower, the switching means is turned off.

According to a third aspect of the present invention, there is provided a semiconductor memory device comprising:
It includes the same switching means and reference voltage generating means as in claim 1, and further includes the following level lowering means and control means.

The level lowering means converts the level of the internal power supply voltage to a lowered first voltage in a normal operation, and further lowers the first voltage in a stress mode to be lower than the reference voltage in a stress mode. The potential is converted to a second voltage.

The control means compares the generated reference voltage with the first or second voltage converted by the level lowering means, and when the reference voltage is higher than the first or second voltage, Turns on the switching means, and turns off the switching means when the reference voltage is lower than the first or second voltage.

According to a fourth aspect of the present invention, there is provided a semiconductor memory device comprising:
It includes switching means, level lowering means, and reference voltage generating means similar to those of the first aspect of the present invention, and further includes first control means and second control means.

The first control means compares the reference voltage generated by the reference voltage generation means with the internal power supply voltage dropped by the level drop means, and controls the switching means on / off based on the comparison result.

The second control means always turns on the switching means in response to an externally generated stress mode signal. At the time of the stress mode, at least one of the level lowering unit, the reference voltage generating unit, and the first control unit is inactivated.

According to a fifth aspect of the present invention, there is provided a semiconductor memory device comprising:
And a switching means, a level lowering means, a reference voltage generating means, a first control means and a second control means similar to those of the fourth invention, and further comprising a first control means and a second control means. And means for switching off in response to the stress mode signal.

[0038]

In the semiconductor memory device according to the first aspect of the present invention, there is one switching means for turning on / off between the external power supply voltage line and the internal power supply voltage line, and this switching means is turned on / off in the normal mode. By turning it off, the internal power supply voltage is made constant, and in the stress mode, it is always turned on. As described above, by sharing the switching means requiring a relatively large size between the normal mode and the stress mode, the area of the internal voltage down converter and the semiconductor memory device can be reduced.

In the semiconductor memory device according to the second aspect of the present invention, since the pull-up means generates the second reference voltage higher than the internal power supply voltage whose level has been lowered in the stress mode, the control means can control the stress. In the mode, the switch means is always turned on. Thereby, the internal power supply voltage can be made equal to the external power supply voltage. Thus, even in the stress mode, the burn-in test can be performed while all means included in the internal voltage down converter remain active. As a result, stress can be applied to all means included in the internal voltage down converter.

In the semiconductor memory device according to the third aspect of the present invention, since the level lowering means generates the second voltage higher than the reference voltage in the stress mode, the control means turns on the switching means. . Therefore, in the third aspect of the present invention, one switching means can be shared similarly to the second aspect of the present invention, and in the stress mode, all means included in the internal voltage down converter are activated to reduce the stress. You can call.

In the semiconductor memory device according to the present invention, at least one of the level lowering means, the reference voltage generating means, and the first control means is inactivated by an externally generated stress mode signal. However, the second control means turns on the switching means in response to an externally generated test mode signal. Thereby, the internal power supply voltage line and the external power supply voltage line are connected, and a burn-in test can be performed.

In the semiconductor memory device according to the fifth aspect of the present invention, in the stress mode, the connection between the first control means and the second control means is cut off. The burn-in test can be performed while all of the control means are kept active. Thereby, stress can be applied to all means included in the internal voltage down converter.

[0043]

FIG. 1 is a circuit diagram showing an embodiment of an internal voltage down converter built in a semiconductor memory device. The internal step-down circuit shown in FIG. 1 includes an external power supply voltage 1, an internal power supply voltage 2, a level shifter circuit 3 which is always activated, a reference voltage generating circuit 4 which is always activated, and a differential amplifier which is always activated. The circuit includes a circuit 5, a P-channel transistor 6, and a pull-up circuit 41 for pulling up a reference voltage Vref in response to a stress mode signal / SM.

External power supply voltage line 1, internal power supply voltage line 2, and P-channel transistor 6 have the same structure as the internal voltage down converter shown in FIG. Level shifter circuit 3, reference voltage generating circuit 4, and differential amplifier circuit 5 perform the same operations as the normal operation of level shifter circuit, reference voltage generating circuit, and differential amplifier circuit shown in FIG.

Pull-up circuit 41 includes an inverter 91 and a clocked CMOS 10. The inverter 91
Inverts stress mode signal / SM to generate clocked CM
The OS 10 is controlled. The clocked CMOS 10 has its input connected to the ground terminal and its output connected to a reference voltage line 7 that outputs a reference voltage. Pull-up circuit 4
1 raises the reference voltage line 7 to the power supply potential when the stress mode signal / SM is at a low level.

Next, the operation of the internal step-down circuit shown in FIG. 1 will be described. First, in the normal mode, the level shifter circuit 3 lowers the level of the internal power supply voltage to generate the voltage Vs. This voltage Vs is supplied to the differential amplifier circuit 5. The reference voltage Vref generated by the reference voltage generation circuit 4 is supplied to the differential amplifier circuit 5. When the voltage Vs from the level shifter circuit 3 is lower than the reference voltage Vref generated by the reference voltage generation circuit 4,
The output of the differential amplifier circuit 5 becomes low. In response to this low level output, the P-channel transistor 6 turns on,
External power supply voltage line 1 and internal power supply voltage line 2 are connected.
When the internal power supply voltage increases, the level shifter circuit 3
As a result, the level of the voltage Vs which has been lowered is also increased. When the voltage Vs becomes higher than the reference voltage Vref, the output of the differential amplifier circuit 5 goes high, the P-channel transistor 6 turns off, and the external power supply voltage line 1 is disconnected from the internal power supply voltage line 2. The above operation is the same as in the conventional example.

Next, the operation in the stress mode will be described. Since the reference voltage generation circuit 4 is always activated, the reference voltage generation circuit 4 attempts to generate the reference voltage Vref in the normal mode, but the pull-up circuit 41 responds to the stress mode signal / SM (low level) to generate the reference voltage Vref. The potential of the voltage line is raised to the power supply potential. Thereby, the level of the output Vs of the level shifter circuit 3 becomes lower than the level of the reference voltage line 7. Therefore, the output of the differential amplifier circuit 5 becomes low level, and the P-channel transistor 6 is always turned on in response to the low level output. Thus, external power supply voltage line 1 and internal power supply voltage line 2 can be connected.

In the case of the internal step-down circuit shown in FIG. 1, a relatively large-sized P-channel transistor connected between external power supply voltage line 1 and internal power supply voltage line 2 can be reduced to one. The area of the internal voltage down converter can be reduced. Further, since the level shifter circuit 3, the reference voltage generating circuit 4, and the differential amplifier circuit 5 are always in an activated state, stress is applied even in the stress mode.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. The difference between the internal voltage down-converting circuit shown in FIG. 2 and the internal voltage down-converting circuit shown in FIG. 1 is that the output terminal of the pull-up circuit 41 and the output terminal of the reference voltage generating circuit 4
The MOS transfer gate 11 is provided, and the inverter 92 connected to the gate electrode of the PMOS transistor constituting the transfer gate is provided. CMOS transfer gate 11 and inverter 92 are turned on / off in response to stress mode signal / SM.

Next, the operation of the second embodiment will be described. In the normal mode, the stress mode signal / SM is at a high level, and the CMOS transfer gate 11 is turned on. Therefore, the reference voltage Vref generated by the reference voltage generation circuit 4 is supplied to the differential amplifier circuit 5. When the level of the voltage Vs obtained by lowering the internal power supply voltage by the level shifter circuit 3 is lower than the reference voltage Vref, the output of the differential amplifier circuit 5 becomes low. In response to this low level output, P-channel transistor 6 turns on. Thereby, the external power supply voltage line and the internal power supply voltage line are connected. When the internal power supply voltage increases, the level of the output voltage Vs of the level shifter circuit 3 becomes higher than the reference voltage Vs.
ref, and the output of the differential amplifier circuit 5 becomes a high level. In response to this high level output, P-channel transistor 6 is turned off, and external power supply voltage line 1 and internal power supply voltage line 2 are disconnected.

Next, in the stress mode, the reference voltage Vref is generated by the reference voltage generation circuit 4 which is always activated.
However, since the stress mode signal / SM is at a low level, the CMOS transfer gate 11 is off, and the reference voltage Vref is not transmitted to the differential amplifier circuit 5. On the other hand, since the clocked CMOS 10 is turned on in response to the stress mode signal / SM (low level), the level of the reference voltage line 7 becomes high (external power supply voltage level). Therefore, the level of the output voltage Vs of the level shifter circuit 3 is always lower than the potential of the reference voltage line 7. As a result, the output of the differential amplifier circuit 5 goes low, and in response, the P-channel transistor 6 is always on. Thus, external power supply voltage line 1 and internal power supply voltage line 2 can be connected.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention. The difference between the internal step-down circuit shown in FIG. 3 and the internal step-down circuit shown in FIG. 2 is that N-channel transfer gate 12 which is turned on / off in response to stress mode signal / SM is used instead of CMOS transfer gate 11 and inverter 92. It is provided. The other circuits are the same as the circuits shown in FIG. 2, and the description thereof will be omitted as appropriate.

Next, the operation will be described. First, in the normal mode, since the stress mode signal / SM is at a high level and the N-channel transfer gate 12 is turned on, the output of the reference voltage generating circuit 4 is sent to the differential amplifier circuit 5 via the reference voltage line 7. Supplied. Therefore, when the level of the voltage Vs lowered by the level shifter circuit 3 is lower than the reference voltage Vref, the output of the differential amplifier circuit 5 becomes low. In response to this low level output, P-channel transistor 6 is turned on, and external power supply voltage line 1 and internal power supply voltage line 2 are connected. When the internal power supply voltage increases, the level of the voltage Vs lowered by the level shifter circuit 3 becomes higher than the reference voltage Vref, and the output of the differential amplifier circuit 5 becomes high. In response to this high level output, P-channel transistor 6 is turned off, and external power supply voltage line 1 and internal power supply voltage line 2
And is separated.

Next, in the stress mode, reference voltage Vref is output from activated reference voltage generating circuit 4, but N-channel transfer gate 12 is turned off because stress mode signal / SM is at a low level. I have. Therefore, the reference voltage Vref is not transmitted to the differential amplifier circuit 5. On the other hand, since the clocked CMOS 10 is turned on, the reference voltage line 7 goes high (external power supply voltage level). Subsequent operations in the stress mode are the same as those in FIG. 2, and a description thereof will be omitted.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention. The fourth embodiment is different from the first embodiment only in the pull-up circuit, and FIG. 4 shows only the pull-up circuit.

In FIG. 4, a P-channel transistor 13 is used as a pull-up circuit. P-channel transistor 13 has its source (or drain) connected to the power supply voltage, its drain (or source) connected to reference voltage line 7, and its gate electrode connected to receive stress mode signal / SM.

Next, the operation will be described. First, in the normal mode, the stress mode signal / SM is at a high level, and the P-channel transistor 13 is off. Therefore, the reference voltage Vref generated by the reference voltage generation circuit 4 is supplied to the differential amplifier circuit 5. The subsequent operations in the normal operation are the same as those in the case shown in FIG.

Next, in the stress mode, the reference voltage Vref is generated by the reference voltage generation circuit 4 which is activated.
However, since the stress mode signal / SM is at a low level, the P-channel transistor 13 is turned on,
The reference voltage line 7 is forced to a high level (external power supply voltage level). Subsequent operations are the same as in the first embodiment shown in FIG. 1, and a description thereof will be omitted.

FIG. 5 is a circuit diagram showing a fifth embodiment of the present invention. The circuit shown in FIG. 5 is different from the circuit shown in FIG. 2 in that the pull-up circuit 41 is replaced with the P-channel transistor 13 shown in FIG. In FIG. 5, a differential amplifier circuit, a level shifter circuit, and the like are the same as in FIG. 2, and description thereof is omitted for simplification of display.

Next, the operation will be described. First, in the normal mode, the stress mode signal / SM is at a high level, the P-channel transistor 13 is turned off, and the CM
Since the OS transfer gate 11 is on, the output Vref of the reference voltage generation circuit 4 is supplied to the differential amplifier circuit 5. Subsequent operations in the normal mode are the same as those shown in the first to fourth embodiments, and a description thereof will be omitted.

Next, in the stress mode, the reference voltage Vref is generated by the activated reference voltage generating circuit 4. However, since the stress mode signal / SM is at a low level, the CMOS transfer gate 11 is off. The reference voltage Vref is not transmitted to the differential amplifier circuit 5. On the other hand, since P-channel transistor 13 is turned on in response to stress mode signal / SM (low level), the potential of reference voltage line 7 goes high (external power supply voltage level). Subsequent operations in the stress mode are the same as in the first to fourth embodiments, and a description thereof will be omitted.

FIG. 6 is a circuit diagram showing a sixth embodiment of the present invention. The circuit shown in FIG. 6 differs from the circuit shown in FIG. 7 in that an N-channel transistor 12 shown in FIG. 3 is provided instead of CMOS transfer gate 11 and inverter 92.

Next, the operation will be described. First, in the normal mode, since the stress mode signal / SM is at a high level, the P-channel transistor 13 is turned off and the N-channel transfer gate 12 is turned on, so that the reference voltage Vref generated by the reference voltage generating circuit 4 is It is supplied to the differential amplifier circuit 5. Subsequent operations in the normal mode are the same as those in the first to fifth embodiments, and a description thereof will be omitted.

Next, in the stress mode, reference voltage Vref is generated by activated reference voltage generating circuit 4, but N-channel transfer gate 12 is turned off since stress mode signal / SM is at a low level. Therefore, the reference voltage Vref is not transmitted to the differential amplifier circuit 5. On the other hand, since the P-channel transistor 13 turns on in response to the stress mode signal / SM (low level),
The potential of the reference voltage line 7 goes high (external power supply voltage level). Subsequent operations in the stress mode are the same as those in the first to fifth embodiments, and thus description thereof will be omitted.

FIG. 7 is a circuit diagram showing a seventh embodiment of the present invention. In FIG. 7, the description of the external power supply voltage line 1, the internal power supply voltage line 2, the level shifter circuit 3, and the differential amplifier circuit 5 is omitted. The difference between the circuit shown in FIG. 7 and the circuit shown in FIG. 1 is that reference voltage generating circuit 4 is inactivated by stress mode signal / SM.

Next, the operation will be described. First, in the normal mode, the stress mode signal / SM is at a high level, and the clocked CMOS 10 is off. Reference voltage generating circuit 4 is inactivated when stress mode signal / SM is at a low level and activated when stress mode signal / SM is at a high level. Therefore, only in the normal mode, reference voltage generating circuit 4 generates reference voltage Vref. Therefore, the operation in the normal mode is the same as in the first to sixth embodiments, and a description thereof will be omitted.

Next, in the stress mode, since the stress mode signal / SM is at a low level, the reference voltage generation circuit 4
Are deactivated. The clocked CMOS 10
Is turned on, the reference voltage Vref becomes a high level (external power supply voltage level). Therefore, the level of the voltage Vs lowered by the level shifter circuit 3 is always lower than the reference voltage Vref, and the output of the differential amplifier circuit 5 is low. In response to this low level output, P
Channel transistor 6 is always on, and external power supply voltage line 1 and internal power supply voltage line 2 are connected.

FIG. 8 is a circuit diagram showing an eighth embodiment of the present invention.

In FIG. 8, external power supply voltage lines 1,
The description of the internal power supply voltage line 2, the level shifter circuit 3, and the differential amplifier circuit 5 is omitted. The circuit shown in FIG. 8 is different from the circuit shown in FIG. 4 in that reference voltage generating circuit 4 is deactivated by stress mode signal / SM.

Next, the operation will be described. First, in the normal mode, the stress mode signal / SM is at a high level, and the P-channel transistor 13 is off.
In the normal mode, reference voltage generating circuit 4 is inactivated when stress mode signal / SM is at a low level, and activated when stress mode signal / SM is at a high level. Therefore, in the normal mode, reference voltage Vref is generated. The generated reference voltage Vref is supplied to the differential amplifier circuit 5. The subsequent operation in the normal mode is the same as in the first to seventh embodiments, and the description thereof will be omitted.

Next, in the stress mode, since the stress mode signal / SM is at a low level, the reference voltage generating circuit 4 is deactivated. On the other hand, P channel transistor 13 is turned on in response to stress mode signal / SM, so that the potential of reference voltage line 7 is at a high level (external power supply voltage level). Subsequent operations in the stress mode are the same as in the first to seventh embodiments, and a description thereof will be omitted.

FIG. 9 is a circuit diagram showing a ninth embodiment of the present invention. The difference between the internal step-down circuit shown in FIG. 9 and the internal step-down circuit shown in FIG. 1 is that the pull-up circuit is omitted and the level shifter circuit 3 generating the voltage Vs is replaced by
A level shifter circuit 31 capable of outputting the voltage Vs and the threshold voltage of the PMOS transistor is provided.

The level shifter circuit 31 has two electrodes and 1
P-channel transistors 14 and 15 having two control electrodes, and an inverter 93 are provided. P-channel transistor 14 has one electrode connected to internal power supply voltage line 2, the other electrode connected to one electrode of P-channel transistor 15, and the gate electrode connected to the output of inverter 93. P-channel transistor 15 has the other electrode connected to the ground potential and the gate electrode connected to the ground potential. Inverter 93 is connected so that its input terminal receives stress mode signal / SM,
Its output terminal is connected to the gate electrode of P-channel transistor 14. The connection point between P-channel transistors 14 and 15 is connected to differential amplifier circuit 5.

Next, the operation will be described. First, in normal mode, stress mode signal / SM is at a high level, and P-channel transistors 14 and 15 are both on, so that the level of the internal power supply voltage is reduced by the resistance division. Thereby, the value of the voltage Vs is determined. Further, the reference voltage generation circuit 4 generates a reference voltage Vref which is a certain value. Therefore, when the level of the voltage Vs lowered by the level shifter circuit 3 is lower than the reference voltage Vref, the output of the differential amplifier circuit 5 becomes low. In response to this low level output, P-channel transistor 6 is turned on, and external power supply voltage line 1 and internal power supply voltage line 2 are connected. Also,
When the internal power supply voltage increases, the level of the voltage Vs, which has been lowered by the level shifter circuit 3, is changed to the reference voltage Vr.
ef. In this case, the output of differential amplifier circuit 5 becomes high level, P-channel transistor 6 is turned off, and external power supply voltage line 1 and internal power supply voltage line 2 are disconnected.

Next, in the stress mode, since the stress mode signal / SM is at a low level, the P-channel transistor 14 is turned off and the P-channel transistor 15 is turned on, so that the output Vs of the level shifter circuit 3 becomes
This is the level of the threshold voltage of P-channel transistor 15. The reference voltage generation circuit 4 generates a reference voltage Vref which is a constant value.
When the value of ref is set to a value larger than the value of the voltage Vs (threshold voltage Vtp), the output of the differential amplifier circuit 5 becomes low and the P-channel transistor 6 is always turned on. Thereby, external power supply voltage line 1 and internal power supply voltage line 2 are connected.

FIG. 10 is a circuit diagram showing a tenth embodiment of the present invention. The difference between the internal step-down circuit shown in FIG. 10 and the internal step-down circuit shown in FIG. 9 is that the voltage Vs or Vtp
Voltage Vs or ground potential GN instead of the level shifter circuit for generating (threshold voltage of p-channel transistor)
That is, a level shifter circuit 32 for outputting D is provided. In the level shifter circuit 32, an N-channel transistor 17 and an inverter 94 are further added to the level shifter circuit shown in FIG. N-channel transistor 17 has one electrode connected to differential amplifier circuit 5, the other electrode connected to ground potential, and the gate electrode connected to inverter 94. Inverter 94
Are connected to receive stress mode signal / SM.

Next, the operation will be described. First, in the normal mode, stress mode signal / SM is at a high level, and P-channel transistors 14 and 15
Both are turned on, and the N-channel transistor 17 is turned off. Therefore, the output voltage V of the level shifter circuit 32
s, the level of the internal power supply voltage is reduced by the resistance division of the P-channel transistors 14 and 15;
The value of Vs is determined. Subsequent operations in the normal mode are the same as in the ninth embodiment, and a description thereof will be omitted.

Next, in the stress mode, since the stress mode signal / SM is at a low level, the P-channel transistors 14 and 15 are turned off and the N-channel transistor 17 is turned on. Therefore, the output voltage Vs of the level shifter circuit 32 becomes low level (ground level) and becomes smaller than the value of the reference voltage Vref, so that the output of the differential amplifier circuit 5 becomes low level. In response to this low level output, the P-channel transistor 6 is always on,
External power supply voltage line 1 and internal power supply voltage line 2 are connected.

FIG. 11 is a circuit diagram showing an eleventh embodiment of the present invention. The difference between the internal step-down circuit shown in FIG. 11 and the internal step-down circuit shown in FIG. 1 is that, instead of the differential amplifier always activated, a differential amplifier circuit inactivated by a stress mode signal / SM 5 and a circuit 51 for constantly turning on the P-channel transistor 6 in response to the stress mode signal / SM. Circuit 51 includes N-channel transistor 18 and inverter 95. One electrode of the N-channel transistor 18 is a P-channel transistor 6
The other electrode is connected to the ground terminal, and the gate electrode is connected to the output of the inverter 95. Inverter 95 receives stress mode signal / SM
Connected to receive.

In the normal mode in operation, stress mode signal / SM is at a high level, and N-channel transistor 18 is off. The differential amplifier circuit 5
It is activated when the stress mode signal / SM is at a high level and deactivated when it is at a low level. In the normal mode, stress mode signal / SM is at a high level, and differential amplifier circuit 5 is active. Therefore, other operations in the normal mode are described in the first embodiment.
The description is omitted because it is the same as that described in (10) to (10).

Next, in the stress mode, the stress mode signal / SM is at a low level, and differential amplification is performed irrespective of the values of the reference voltage Vref generated by the reference voltage generating circuit 4 and the voltage Vs output by the level shifter circuit 3. The circuit 5 becomes inactive. N-channel transistor 18 turns on in response to stress mode signal / SM,
Outputs a low-level signal. In response to this low level signal, P-channel transistor 6 is always turned on, and external power supply voltage line 1 and internal power supply voltage line 2 are connected.

FIG. 12 is a circuit diagram showing a twelfth embodiment of the present invention. The difference between the internal step-down circuit shown in FIG. 12 and the internal step-down circuit shown in FIG.
CMOS transfer gate 16 for turning on / off between channel transistor 6 and inverter 96
And the differential amplifier circuit 5 is always activated.

Next, the operation will be described. First, in the normal mode, the stress mode signal / SM is at a high level, the N-channel transistor 18 is off,
The CMOS transfer gate 16 is on. Therefore, subsequent operations in the normal mode are the same as those described in the first to eleventh embodiments.

Next, in the stress mode, the stress mode signal / SM is at a low level, the N-channel transistor 18 is on, and the CMOS transfer gate 16 is off. Therefore, the P-channel transistor 6 is always turned on irrespective of the value of the reference voltage Vref generated by the reference voltage generation circuit 4 or the value of the output voltage Vs of the level shifter circuit 3. Thereby, external power supply voltage line 1 and internal power supply voltage line can be connected.

[0085]

As described above, according to the present invention, it is possible to turn on / off the external power supply voltage line and the internal power supply voltage line in the normal mode by one switching means, and to perform the operation in the stress mode. The external power supply voltage line and the internal power supply voltage line can always be connected. Therefore, the area of the internal voltage down converter can be made smaller than before, and the area of the semiconductor memory device can be made smaller.

Further, even in the stress mode, all of the switching means, the level lowering means, the reference voltage generating means and the control means can be activated, and stress can be applied to all these means. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of an internal voltage down converter of a semiconductor memory device.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a seventh embodiment of the present invention.

FIG. 8 is a circuit diagram showing an eighth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a ninth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a tenth embodiment of the present invention.

FIG. 11 is a circuit diagram showing an eleventh embodiment of the present invention.

FIG. 12 is a circuit diagram showing a twelfth embodiment of the present invention.

FIG. 13 is a graph showing characteristics of the internal voltage down converter.

FIG. 14 is a graph showing a relationship between an external power supply voltage and an internal power supply voltage during a burn-in test.

FIG. 15 is a schematic block diagram illustrating an example of a semiconductor memory device having a stress mode function.

FIG. 16 is a circuit diagram showing a conventional internal step-down circuit having a function of equalizing an internal power supply voltage and an external power supply voltage.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 external power supply voltage line 2 internal power supply voltage line 3 level shifter circuit 4 reference voltage generation circuit 5 differential amplifier circuit 6 P-channel transistor 7 reference voltage line 41 pull-up circuit

Continued on the front page (58) Fields surveyed (Int. Cl. ⁶ , DB name) H01L 27/10 481 G01R 31/28 H01L 21/66

Claims (5)

(57) [Claims] 1. A semiconductor memory device comprising: an internal storage circuit; and an internal step-down circuit that generates an internal power supply voltage by lowering an external power supply voltage and supplies the generated internal power supply voltage to the internal storage circuit. A stress mode test function of applying an external power supply voltage to the internal storage circuit; and turning on / off between an external power supply voltage line supplying the external power supply voltage and an internal power supply voltage line supplying the internal power supply voltage. Switching means, level lowering means for lowering the level of the internal power supply voltage, reference voltage generating means for generating a reference voltage for keeping the level of the internal power supply voltage constant, and a reference generated by the reference voltage generating means A system for comparing a voltage with the internal power supply voltage dropped by the level lowering means, and for controlling on / off of the switching means based on the comparison result. Includes means, said switching means, to the stress mode, a semiconductor memory device characterized in that it is always on state. 2. A semiconductor memory device comprising: an internal storage circuit; and an internal step-down circuit that generates an internal power supply voltage by lowering an external power supply voltage and supplies the internal power supply voltage to the internal storage circuit. A stress mode test function of applying an external power supply voltage to the internal storage circuit; and turning on / off between an external power supply voltage line supplying the external power supply voltage and an internal power supply voltage line supplying the internal power supply voltage. Level switching means for lowering the level of the internal power supply voltage, reference voltage generating means for generating a first reference voltage for keeping the internal power supply voltage constant, and setting the first reference voltage in a stress mode Pull-up means for pulling up to generate a second reference voltage having a higher potential than the internal power supply voltage dropped by the level lowering means; A first or second reference voltage is compared with the dropped internal power supply voltage, and if the first or second reference voltage is higher than the dropped internal power supply voltage, the switching means is turned on. State,
A semiconductor memory device, comprising: control means for turning off the switching means when the first or second reference voltage is lower than the dropped internal power supply voltage. 3. A semiconductor memory device comprising: an internal storage circuit; and an internal step-down circuit for generating an internal power supply voltage by lowering an external power supply voltage and supplying the generated internal power supply voltage to the internal storage circuit. A stress mode test function of applying an external power supply voltage to the internal storage circuit; and turning on / off between an external power supply voltage line supplying the external power supply voltage and an internal power supply voltage line supplying the internal power supply voltage. Two switching means, a reference voltage generating means for generating a reference voltage for keeping the internal power supply voltage constant, and converting the internal power supply voltage to a first voltage lowered during normal operation, and in a stress mode, Level lowering means for further lowering the first voltage to convert it into a second voltage having a lower potential than the reference voltage, and the generated reference voltage and the level Comparing with the first or second voltage converted by the falling means, and when the reference voltage is higher than the first or second voltage, the switching means is turned on, and the reference voltage is A semiconductor memory device comprising a control unit that turns off the switching unit when the voltage is lower than the first or second voltage. 4. A semiconductor memory device comprising: an internal storage circuit; and an internal step-down circuit that generates an internal power supply voltage by lowering an external power supply voltage and supplies the internal power supply voltage to the internal storage circuit. A stress mode test function of applying an external power supply voltage to the internal storage circuit; and turning on / off between an external power supply voltage line supplying the external power supply voltage and an internal power supply voltage line supplying the internal power supply voltage. Switching means, level lowering means for lowering the level of the internal power supply voltage, reference voltage generating means for generating a reference voltage for keeping the level of the internal power supply voltage constant, reference voltage generated by the reference voltage generating means And the internal power supply voltage dropped by the level lowering means, and based on the comparison result, turns on / off the switching means.
A first control means for controlling the off state; and a second control means for constantly turning on the switching means in response to an externally generated stress mode signal. A semiconductor memory device, wherein one of the voltage generating means and the first control means is deactivated. 5. A semiconductor memory device comprising: an internal storage circuit; and an internal step-down circuit that generates an internal power supply voltage by lowering an external power supply voltage and supplies the internal power supply voltage to the internal storage circuit. A stress mode test function of applying an external power supply voltage to the internal storage circuit; and turning on / off between an external power supply voltage line supplying the external power supply voltage and an internal power supply voltage line supplying the internal power supply voltage. Switching means, level lowering means for lowering the level of the internal power supply voltage, reference voltage generating means for generating a reference voltage for keeping the level of the internal power supply voltage constant, reference voltage generated by the reference voltage generating means And the internal power supply voltage dropped by the level lowering means, and based on the comparison result, turns on / off the switching means.
First control means for performing off-control, and second control means for constantly turning on the switching means in response to an externally generated stress mode signal; the first control means and the second control means A semiconductor memory device that is connected between the control unit and a switching unit in response to the stress mode signal.