JP2863566B2 - Voltage adjustment circuit - Google Patents

Description

The present invention relates to a voltage regulator, and more particularly to a three-terminal voltage regulator. These devices are responsive to unregulated input voltages and produce output voltages that do not vary primarily in response to load variations or input voltage variations. The device also uses a circuit that produces a substantially constant output voltage over a wide temperature range.

[Conventional technology and problems to be solved]

It is widely known that voltage regulators have optimal dynamic stability when their output is taken from the emitter of a power transistor. For example, US Industrial Standard
The LM117 and LM140 series devices are relatively stable without external components. Conversely, when the output is taken from the collector of a power transistor, as in the U.S. LM120 and LM137 series devices, a relatively large capacitor should be placed at the output terminal if stability is required. Must connect. The LM120 and LM137 specifications require an output capacitor of at least 1 microfarad (μF) for tantalum and 10 to 25 μF for aluminum. The higher the value, the better.

Although all of the above devices have a bipolar transistor structure, the same considerations apply to metal oxide semiconductor (MOS) structures. In particular, the effective voltage regulator is a complementary MOS (CMO
S) It is configured using devices. In CMOS, the above applies to the source and drain of the power transistor. When the source of the power transistor provides the output, the circuit is relatively stable. However, when the output is taken from the drain of a power transistor, a large output capacitor must be used.

The reason for the lack of stability may be due to the feedback loop gain. In a voltage regulator,
The power transistor is part of a high gain negative feedback loop that is matched to a constant voltage. When the emitter / source electrode of the power transistor provides an output, its voltage gain is less than one and the circuit tends to be stable. When the output is taken from the collector / drain, the voltage gain depends on the load impedance and can be quite large. Therefore, a large output capacitor is required to limit the AC gain for stability.

In the following discussion, the emitter of the bipolar transistor and the source of the MOS transistor will be referred to as the low impedance electrode. The collector of the bipolar transistor and the drain of the MOS transistor are called high impedance electrodes. These characterizations provide functional device equivalents. The base of a bipolar transistor and the gate of a MOS transistor are called control electrodes because they are also functionally equivalent.

Another power supply characteristic is its dropout voltage. This is defined as the input / output voltage difference at which the circuit stops regulating for further drops in the input voltage. As a practical matter, low dropout voltage is an advantage and is considered important in battery operated applications.
Typically, this dropout voltage is on the order of 2 volts for the devices described above and has a negative characteristic with respect to temperature. All of the above devices are in Darlington
Use gton) connected output power transistors or pass transistors. This means that the base of the Darlington input transistor must be at least 2 × V _BE (V _BE : base-emitter voltage) higher than the emitter and the collector must be at least 1 V _SAT (V _SAT : collector-emitter) above this emitter. Saturation voltage) must be high. However, the LM120 is (V
_BE + V _SAT ). At lower operating temperatures, this typically results in a voltage drop of about 2 volts. This voltage drop is sometimes referred to as "headroom" because the input of the voltage regulator must be high enough to allow the sum of the output voltage and the dropout voltage.

Examples of low dropout regulators are LM2930 and LM2931
A series of devices. These are each 150mA
And 100mA rating, both at rated current of 0.6
Has a smaller dropout rating than the bolt. Because the output is output from the collector of the PNP transistor,
These both require a capacitor at its output terminal. Minimum capacitor values are 10 and 22μ, respectively
F.

(Summary of the Invention)

It is an object of the present invention to increase the stability of a low dropout voltage regulator.

Another object of the invention is to provide a pass transistor in a voltage regulator in which the high impedance terminal of the transistor is connected to the output of the regulator and the low impedance terminal of the transistor is also connected to the output terminal for stability. Is to use.

These objects are achieved in the following manner. In the voltage regulation circuit, the pass transistor has the other impedance electrode (emitter / source) connected to the positive input terminal and the high impedance electrode (collector / drain) associated with the output terminal. Typically, this transistor is a bipolar transistor PN
It is a P or P channel MOS transistor. The control electrode (base / gate) is activated at a potential lower than the supply input voltage to turn on the pass transistor. This connection produces the lowest dropout voltage, but does not require a large output capacitor for stabilization. To provide the required stabilization, a second or shunt transistor is provided which is coupled to a low impedance electrode (emitter / source) coupled to the regulator output terminal and to a regulator connection terminal. And a high impedance electrode (collector / drain). This shunt transistor is part of the negative feedback loop of the voltage regulator and is provided with means to ensure that it is conductive for all operating conditions. The voltage regulator circuit includes a temperature stable reference voltage generator connected to drive a first operational amplifier (op amp), the operational amplifier further comprising a shunt transistor control electrode (base / gate). ) And connected. The shunt transistor is connected in series with a high impedance (collector / drain) electrode and a second operational amplifier having an input offset voltage. The output of the second operational amplifier is connected to the control (base / gate) electrode of the pass transistor. Thus, the voltage regulator includes a high gain feedback loop having a reference voltage generating amplifier, a shunt transistor, two operational amplifiers, and a pass transistor. Since a resistor in series with the shunt transistor is connected to the input of the second op amp, the voltage across it must be equal to the offset voltage of the second op amp. Therefore, the feedback loop in all the feedback loops is activated. This secondary feedback loop ensures that the shunt transistor is always on and that its low impedance (emitter / source) electrode operates to stabilize the voltage regulator. Since the bus transistors include only one transistor, the dropout voltage is minimized.

〔Example〕

Although the following description is specific to CMOS structures, it should be understood that the present invention also applies to bipolar transistor circuits. For example, if a P-channel transistor is shown, it can be replaced with a PNP bipolar transistor, and if an N-channel transistor is shown, it can be replaced with a PNP bipolar transistor. In such a case, the collector of the bipolar transistor replaces the drain of the MOS transistor, the emitter becomes the source, and the base becomes the gate. Conventional CM
An OS structure is used as a preferred embodiment. For a corresponding bipolar structure, conventional monolithic, epitaxial, PN junction insulation treatments are preferred. Furthermore,
Although the CMOS circuit shown is associated with an N-well CMOS, various components can be made as P-well devices. In this latter case, all the illustrated transistor elements are replaced by complementary elements, and the polarity of the power supply is reversed.

In FIG. 1, the necessary components are shown in block diagram form. The input of the power supply is connected to the terminal 10 on the positive side and to the ground terminal 11 on the negative side. The conditioned output appears at terminal 12. A series P-channel pass transistor 13 is connected between terminals 10 and 12. Since the source of transistor 13 is connected to terminal 10, its gate is operated at a relatively low potential and the regulator dropout potential is minimized. In the circuit shown, this dropout potential can be as small as a fraction of a volt. However, the drain of transistor 13 is connected to output terminal 12 and is itself unstable in this configuration. Therefore, some stabilization measures are desirable. P-channel shunt transistor 14 has its source connected to output terminal 12 and its drain electrode connected to ground. Since the source of transistor 14 is its low impedance electrode, it serves to stabilize the circuit. Obviously, transistors 13 and 14 can be replaced by PNP bipolar transistors, in which the emitter is connected instead of the source and the collector is connected instead of the drain.

Reference voltage generator 15 generates a temperature stabilized band gap reference voltage and includes a voltage divider responsive to the regulated voltage at terminal 12. Reference voltage generator 15
Drives the op-amp 16, which further drives the gate of the transistor 14. The resistor 17 connects the drain of the transistor 14 to the ground, and the transistor 14
Be able to work as a source amplifier. OP amplifier 18
It is directly connected to the resistor 17 by an internally generated offset voltage source 19. This offset polarity is similar to the offset voltage that appears on both sides of resistor 17 as a small positive potential at the drain of transistor 14 when the input terminals of OP amplifier 18 are at the same potential. The output of OP amplifier 18 drives the gate of transistor 13 which is further connected to terminal 12 (not shown).
Provides the full current needed. In addition, transistor 13
Also provides a current flowing through transistor 14 and a quiescent input current flowing through reference voltage generator 15. The operation of this circuit sets the potential at terminal 12 to the required value. Thus, the components of FIG. 1 form an all-negative feedback loop for terminal 12 that produces a constant voltage level when the input terminals of op amp 16 are at the same potential.

The conduction state in the transistor 14 is maintained by the negative feedback loop means in the negative feedback loop. Op amp 18 sets the conduction state in transistor 14 in conjunction with transistor 13 acting as a common source amplifier such that the voltage drop across resistor 17 is just equal to the offset voltage of op amp 18. The feedback loop for the drain of transistor 14 causes one inversion and is therefore negative.

The voltage regulator feedback loop for terminal 12 includes a reference voltage generator 15, an operational amplifier 16, a shunt transistor 14, an operational amplifier 18, and a pass transistor 13 in series. This loop consists of three inversions (ie, op-amp 16, transistor 14 and transistor 13
Once each) and is therefore negative and conforms to the silicon band gap. In the case shown below, the bandgap reference voltage for this silicon is 1.
2 volts, V _REG drops to 2.5 volts, and _VIN drops to 2.6 volts. This means that the dropout voltage is 0.1 volt at no load.

FIG. 2 is a schematic diagram of a CMOS voltage regulator. The components are of the type found in N-well CMOS, in which all P-channel transistors are made in PN-junction insulated N-wells located on a P-type silicon substrate.
All of the N-channel devices are integrally formed on the P-type substrate and thus have a back gate connection (not shown) to the negative power input terminal 11. Various elements are associated with FIG. 1, but the same notation is used.

Bipolar transistors 24 and 25 are common parasitics for CMOS devices. In such a PNP transistor, the base is an N-well and the collector is dedicated to a substrate at a negative supply potential. The emitter comprises the source or drain of a P-channel transistor. Such a parasitic transistor has a relatively large current gain characteristic. Since the collector is connected to the substrate, such a transistor is operated in a common collector configuration.

The reference voltage generator 15 is connected to the output terminal 12 and includes a voltage divider along with a band gap reference circuit.
Resistors 21 and 22 are connected to terminal 12 and ground (terminal
11) Form a voltage divider connected between. Parasitic PNP transistors 24 and 25 whose collectors are connected to ground have their bases connected to node 23. Resistors 26-69 connect the emitters of transistors 24 and 25 to terminal 12. Transistors 24 and 25 have a current density ratio such that transistor 24 operates at a higher current density than transistor 25. This is most easily done by making transistor 25 n times larger than transistor 24 and operating resistors 26 and 27 at the same emitter current by matching them. Alternatively, transistors 24 and 25 can be identical and operated at different currents. This is done by changing the ratio of resistors 26 and 27. Also transistors
24 and 25 can have a ratio corresponding to the current ratio used. The resulting ΔV _BE appears on both sides of resistor 29. This value follows the relationship of the following equation. That is, Where k is Boltzmann's constant, q is the charge of one electron, and J24 / J2
5 is the current density ratio in transistors 24 and 25.

ΔV _BE is proportional to absolute temperature (PTAT) and becomes zero at zero absolute temperature. At 300K, if transistor 25 operates at eight times the current density of transistor 24, then ΔV
_BE is about 54 mV, determined solely by physical properties.
It has a temperature constant of about 0.33% / ° C.

As noted above, parasitic bipolar transistors must be operated in a common collector configuration, with the collector dedicated to the substrate. However, it has been found that a non-dedicated collector can be formed adjacent to or around the emitter. Such a non-dedicated collector can be used as a separate transistor,
Operates in parallel with a dedicated collector transistor. This concept is described in US Patent No. 4,602,168 to PSSingle, "Low Offset MOS Comparator Circuit". Although a P-well CMOS substrate has been shown to provide an NPN transistor with a non-dedicated collector, it is clear that an N-well process will be used to produce a similar PNP transistor. The teachings in US Patent to Single are incorporated herein by reference.

PNP transistors 30 and 31 are of the type described above, each having a collector dedicated to the substrate engaged with a lateral collector. The two emitters are connected together via a tail current source 20 to the input feed terminal 10. Transistors 30 and 31 are driven by resistors 26 and 27. The resistor 32 is a transistor
Provides a connection to 30. The lateral collectors of transistors 30 and 31 are connected to the N-channel transistor current mirror load of N-channel transistors 33 and 34. The drain of transistor 34
Connected to the gates of transistors 33 and 34. The drain of the transistor 33 is an N-channel transistor
Driving the gate of 35, this transistor 35 acts as a high gain inverter. The capacitor 36 and the resistor 37 perform well-known frequency compensation of the OP amplifier 16. The drain of transistor 34 is connected to the gate of N-channel transistor 38, which is also a high gain inverter with a current mirror load consisting of P-channel transistors 39 and 40. Thus, transistors 35 and
40 are driven out of phase and their drains are
Configure 16 output nodes. This node is directly connected to the gate of P-channel shunt transistor 14.

The collector of transistor 14 is grounded through resistor 17 and is connected to the source of N-channel transistor 42. The drain of transistor 42 is connected to its gate and to the gate of transistor 43 which together form a current mirror. Current source 44 sends a relatively small current of approximately 1 μA through transistor 42, which is mirrored in transistor 43. These two transistors constitute a differential input device of the OP amplifier 18. Note that transistor 43 has its source grounded to form the inverting input as described above. The source of the transistor 42 is operated at a voltage higher than the ground potential by a potential drop across the resistor 17. Said difference represents the offset potential of the operational amplifier 18 (shown as voltage source 19 in FIG. 1). This offset voltage source is created by giving a ratio to the size of transistors 42 and 43, and this causes the current in source 44 to
It is increased by reducing 42 and 43 to a level where they become "depleted".

The drain of transistor 43 is connected to the gate and drain of P-channel transistor 45 which is connected to the gate of P-channel transistor 46 to form a current mirror. Therefore, the transistor 46 is
Configure 18 output nodes. The current sink 47 is a series P
It acts as a pull-down element for the output node directly connected to the gate of channel pass transistor 13. The capacitor 48 performs frequency compensation for the OP amplifier 18.

In operation, transistor 13 drives terminal 12 to a voltage at which the bases of transistors 30 and 31 are at the same potential. In this state, the current flowing through the resistors 26 and 27 is controlled. If resistors 26 and 27 are identical, the currents in transistors 24 and 25 will be equal. Under this condition, ΔV _BE appears across resistor 29. This operation results from the main or overall negative feedback loop.

Transistor 13 provides a current source for output terminal 12, reference voltage generator 15 and resistors 39 and 40, but for quiescent input current, it provides a current source for P-channel shunt transistor 14. In the case described below, resistor 17 is 1000Ω and transistor 14 operates at 100 μA. This means that the offset of the transistors 42, 43 is 0.1 volt. OP amplifier 18 is connected to transistors 14 and 10
Driving transistor 13 to conduct 0 μA of current creates a secondary negative feedback loop (within the main negative feedback loop) responsive to the physically formed offset.

In addition, transistor 13 is capable of conducting any current (to a reasonable extent) through any load element (not shown) connected to terminal 12. Thus, a regulated output voltage is generated at the output terminal 12 which is connected in source form of the transistor 14 and also to the electrode of the low impedance element. Therefore, the voltage regulator is stabilized without requiring a large-capacity filter capacitor in a circuit in which the high impedance electrode of the pass transistor is connected to the output terminal. As pointed out earlier, the dropout voltage is also very small. Although this circuit can be a current source at terminal 12, it should be pointed out that the presence of transistor 14 allows the circuit to sink current to terminal 12. This feature is useful when the regulator is connected to a circuit that operates at a voltage higher than V _REG .

Case The circuit of Fig. 2 is an N-well CM using the following components.
Realized in OS. That is, A transistor (width / length) having the following size was used.
That is, Transistors 24 and 25 were operated at an 8: 1 current density ratio. The voltage at terminal 12 is 2.5 volts,
The circuit was able to produce 4 mA of output current (Vs = + 5.0 volts). The circuit worked well over an input range of 2.6 to 8.0 volts. The voltage at node 23 was 1.3 volts. The voltage across resistor 17 was 100 mV. With a 5 volt input power supply, the quiescent input current was 0.22 mA.

The examples of operation described and described for the present invention have been exhaustive. Modifications and equivalents within the spirit and scope of the invention will be apparent to those skilled in the art from reading the description. For example, while the preferred embodiment used an N-well CMOS structure, a P-well COMS or bipolar structure could be used. Therefore,
The scope of the invention should be limited only by the appended claims.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the circuit of the present invention, and FIG. 2 is a detailed diagram of the circuit of the present invention. 10 ... Input power supply terminal, 11 ... Ground terminal, 12
… Terminal, 13… P-channel pass transistor, 14… P-channel shunt transistor, 15…
... Reference voltage generator, 16, 18 ... Operational amplifier (OP amplifier), 17 ... Resistance, 19 ... Offset voltage source, 20
... current sources, 21, 22 ... resistors, 23 ... nodes, 24,
25 ... Bipolar transistors, 26-29, 32, 37 ...
Resistor, 30, 31 PNP transistor, 33, 34 N-channel transistor, 36 Capacitor, 38, 42 N
Channel transistors 39, 40, 45, 46 P-channel transistors 43 Transistors 44 Current sources 47 Current sinks 48 Capacitors

Claims (5)

(57) [Claims] 1. A voltage adjustment circuit having an unadjusted input power supply terminal, an adjusted output power supply terminal, and a power supply connection terminal, wherein a high impedance and a low impedance electrode through which a controlled current flows, and a current control electrode. And (a) a low impedance electrode connected to the unadjusted input power supply terminal and a high impedance electrode connected to the adjusted output power supply terminal. And (b) means driven from the adjusted output power supply terminal and connected to the control electrode of the series pass transistor, wherein: The output power supply terminal
Means for configuring a negative feedback loop operative to produce a control potential that is maintained at a constant potential level substantially independent of the input supply voltage and the output supply terminal current; and (c) the adjusted output supply terminal. A shunt having a low impedance electrode connected to the power supply connection terminal, and a control electrode.
A transistor responsive to a current flowing through the shunt transistor and connected to the control electrode of the series pass transistor for forming an internal negative feedback loop within the negative feedback loop; Means for maintaining the current flowing through the shunt transistor constant, and thus stabilizing the voltage adjustment circuit. 2. The voltage adjustment circuit according to claim 1, wherein said means for connecting said high impedance electrode of said shunt transistor to said feed connection terminal comprises: said high impedance electrode of said shunt transistor and said feed connection terminal. And a series resistor connected to an input terminal of an operational amplifier having an output terminal connected to the control electrode of the series pass transistor. 3. The voltage adjustment circuit according to claim 2, wherein said operational amplifier includes a means for generating an input offset potential, and thus, said offset potential appears at both ends of said series resistor, so that said shunt voltage is generated. A voltage adjusting circuit for determining a conduction state of a transistor. 4. The voltage adjustment circuit according to claim 1, wherein said circuit is configured using a CMOS structure, and said series pass transistor is a P-channel transistor having a drain connected to said adjusted output power supply terminal. Wherein the shunt transistor is a P-channel transistor having a source connected to the adjusted output power supply terminal. 5. The voltage adjustment circuit according to claim 1, wherein said circuit is configured using a bipolar transistor structure, and said series pass transistor has a collector connected to said regulated output power supply terminal. A voltage adjustment circuit, which is a transistor, wherein the shunt transistor is a PNP transistor having an emitter connected to the adjusted output power supply terminal.