JP2861847B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2861847B2 JP2861847B2 JP7014344A JP1434495A JP2861847B2 JP 2861847 B2 JP2861847 B2 JP 2861847B2 JP 7014344 A JP7014344 A JP 7014344A JP 1434495 A JP1434495 A JP 1434495A JP 2861847 B2 JP2861847 B2 JP 2861847B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- circuit board
- cavity
- semiconductor element
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の構造に関
し、特に回路基板上に半導体素子を実装し、これを樹脂
封止してなる半導体装置に関する。Relates the structure of the present invention is a semiconductor device BACKGROUND OF THE, particularly a semiconductor element mounted on a circuit board, which relates to a semiconductor device in which resin sealing.
【０００２】[0002]
【従来の技術】従来の半導体装置は図５（ａ），（ｂ）
に示されるように、回路基板１にキャビティを設け、そ
のキャビティ中に半導体素子４を実装し、キャビティ内
に封止樹脂２を充填して半導体素子４を封止する構造に
おいて、複数の半導体素子を実装する場合、一つのキャ
ビティ中に複数の半導体素子４を実装していた。また５
はボンデイングワイヤである。図５に示す半導体装置
は、側縁に側面電極３を備えた回路基板１に２個の半導
体素子を実装してボンディングＬＣＣ（Ｌｅａｄｌｅｓ
ｓ Ｃｈｉｐ Ｃａｒｒｉｅｒ）タイプのものであり、
回路基板１の外形寸法は１辺あたり１０〜４０ｍｍと小
型であり、特に複数の半導体素子を回路基板のキャビテ
ィ内に高密度に実装する場合には、回路基板のキャビテ
ィを封止する封止樹脂が回路基板の表面積に占める割合
が高くなっている。図５に示すような半導体装置におい
て回路基板にキャビティを設けるにあたっては、複数の
半導体素子を一括して収容可能な大きさであって、しか
も複数の半導体素子を一括して封止できるような方形状
に形成していた（例えば、特開昭６１−２４７０６０号
参照）。2. Description of the Related Art FIGS. 5A and 5B show a conventional semiconductor device.
As shown in FIG. 1, in a structure in which a cavity is provided in a circuit board 1, a semiconductor element 4 is mounted in the cavity, and a sealing resin 2 is filled in the cavity to seal the semiconductor element 4, Is mounted, a plurality of semiconductor elements 4 are mounted in one cavity. Also 5
Is a bonding wire. In the semiconductor device shown in FIG. 5, two semiconductor elements are mounted on a circuit board 1 having a side electrode 3 on a side edge, and bonding LCC (Leadles
s Chip Carrier) type,
The external dimensions of the circuit board 1 are as small as 10 to 40 mm per side, and especially when a plurality of semiconductor elements are densely mounted in the cavity of the circuit board, a sealing resin for sealing the cavity of the circuit board. Are increasing in the surface area of the circuit board. When providing a cavity in a circuit board in a semiconductor device as shown in FIG. 5, a semiconductor device having a size capable of accommodating a plurality of semiconductor elements at a time and capable of sealing a plurality of semiconductor elements at a time. (See, for example, JP-A-61-247060).
【０００３】[0003]
【発明が解決しようとする課題】上述した従来の半導体
装置では、回路基板の表面積上に占める封止樹脂の割合
が高いため、回路基板のキャビティに封止樹脂を充填し
た後に回路基板に反りが生じる虞れがあった。これは、
回路基板のキャビティに充填した封止樹脂をキュアーす
る際に樹脂の熱硬化収縮が起こることに起因する。特
に、回路基板としてガラスエポキシ材等を用いた場合に
は、回路基板に著しく反りが発生する危険性があった。
回路基板に反りが発生すると、半導体装置の実装時に回
路基板１の一部の側面電極３がプリント基板の電極から
浮き上がってしまい、接続不良を生じてしまうという問
題があった。In the above-mentioned conventional semiconductor device, the proportion of the sealing resin occupying the surface area of the circuit board is high, so that the circuit board warps after the cavity of the circuit board is filled with the sealing resin. There was a risk of occurrence. this is,
This is because the resin cures and shrinks when the sealing resin filled in the cavity of the circuit board is cured. In particular, when a glass epoxy material or the like is used as the circuit board, there is a risk that the circuit board may be significantly warped.
When the circuit board is warped, there is a problem that a part of the side electrode 3 of the circuit board 1 rises from the electrode of the printed board when mounting the semiconductor device, thereby causing a connection failure.
【０００４】また回路基板へのキャビティの加工は、座
ぐり加工によるケースが多いが、一様に方形のキャビテ
ィを形成することは、座ぐり加工面積が広くなる原因と
なり、加工面積が広くなった分、封止樹脂が必要となる
ため総じてコストアップの要因となっていた。またルー
ターによる座ぐり加工は、面積あたりの加工費用が高い
という問題があった。In many cases, the processing of a cavity in a circuit board is performed by counterbore processing. However, forming a square cavity uniformly causes an increase in the counterbore processing area, resulting in an increase in the processing area. This necessitates the use of a sealing resin, which generally causes an increase in cost. In addition, the counterbore processing using a router has a problem that processing cost per area is high.
【０００５】本発明の目的は、封止樹脂による回路基板
の反りを防止する半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device for preventing a circuit board from warping due to a sealing resin.
【０００６】[0006]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置は、回路基板上に複数の半
導体素子を実装し、樹脂で半導体素子を気密封止した半
導体装置であって、前記回路基板は、ガラスエポキシ材
を素材とし、堰部と樹脂分断部とを組合せて形成された
凹部であるキャビティを一主面上に有し、前記キャビテ
ィは、前記樹脂の盛付領域内に位置するとともに、前記
半導体素子を受け入れるものであり、前記堰部と前記樹
脂分断部は、前記回路基板に設けられた前記キャビティ
の側壁をなす基板の立ち上がり部により構成されたもの
であって、前記樹脂は、前記堰部及び前記樹脂分断部を
越えることなく前記凹部内に設けられ、前記半導体素子
は、前記回路基板の一主面上の前記凹部に実装され、前
記回路基板の裏面にて実装基板に接続されるものであ
る。 In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device in which a plurality of semiconductor elements are mounted on a circuit board and the semiconductor elements are hermetically sealed with a resin. The circuit board is made of a glass epoxy material
Was formed by combining the weir part and the resin dividing part
A cavity, which is a concave portion, on one main surface;
Is located within the resin mounting area and the resin
A semiconductor element is received, and the weir portion and the tree are received.
The grease dividing portion is provided in the cavity provided in the circuit board.
Composed of the rising part of the substrate forming the side wall of
In the resin, the weir portion and the resin dividing portion
The semiconductor element provided in the recess without exceeding
Is mounted in the recess on one main surface of the circuit board, and
It is connected to the mounting board on the back of the circuit board.
You.
【０００７】また、回路基板上に複数の半導体素子を実
装し、樹脂で半導体素子を気密封止した半導体装置であ
って、前記回路基板は、ガラスエポキシ材を素材とし、
堰部と樹脂分断部とを組合せて形成された凹部であるキ
ャビティを一主面上に有し、前記キャビティは前記樹脂
の盛付領域内に位置するとともに、前記半導体素子を受
け入れるものであり、前記堰部と前記樹脂分断部は、前
記回路基板上に立上げて装着されて前記キャビティを形
成する樹脂枠により構成されたものであって、前記樹脂
は、前記堰部及び前記樹脂分断部を越えることなく前記
凹部内に設けられ、前記半導体素子は、前記回路基板の
一主面上の前記凹部に実装され、前記回路基板の裏面に
て実装基板に接続されるものである。 Further , a plurality of semiconductor elements are mounted on a circuit board.
A semiconductor device in which a semiconductor element is hermetically sealed with resin
Thus, the circuit board is made of a glass epoxy material,
A key, which is a concave portion formed by combining a weir portion and a resin dividing portion.
Cavity on one main surface, and the cavity is formed of the resin
Within the mounting area of the
And the weir portion and the resin dividing portion are
The cavity is formed by mounting it on a circuit board.
Comprising a resin frame, wherein the resin
The said without crossing the weir portion and the resin dividing portion
The semiconductor element is provided in the recess, and the semiconductor element is provided in the circuit board.
Mounted in the recess on one main surface, on the back of the circuit board
Connected to the mounting board.
【０００８】[0008]
【０００９】[0009]
【００１０】[0010]
【００１１】[0011]
【００１２】[0012]
【作用】回路基板上での気密封止用樹脂の盛付領域内に
位置させて桟を設け、該桟により樹脂の盛付領域を個々
に分断して、樹脂硬化の際に回路基板に加わる反りを抑
制する。According to the present invention, a crossbar is provided in a region where a resin for hermetic sealing is mounted on a circuit board, and the cross section of the resin is individually divided by the crossbar to be added to the circuit board when the resin is cured. Suppress warpage.
【００１３】[0013]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【００１４】（実施例１）図１（ａ）及び（ｂ）は、本
発明の実施例１を示す平面図及び断面図である。(Embodiment 1) FIGS. 1A and 1B are a plan view and a sectional view showing Embodiment 1 of the present invention.
【００１５】図において、ガラスエポキシ材を素材とす
る回路基板１に、ルーターを用いた座ぐり加工によって
キャビティ１ａを形成し、キャビティ１ａ内に半導体素
子４を実装し、キャビティ１ａ内に封止樹脂２を注入
し、半導体素子４を樹脂２で気密封止する。また回路基
板１の周縁には、側面電極３を設けており、回路基板１
の電極と半導体素子４の電極とは、ボンデイングワイヤ
５により電気的に接続してある。In FIG. 1, a cavity 1a is formed in a circuit board 1 made of a glass epoxy material by counterboring using a router, a semiconductor element 4 is mounted in the cavity 1a, and a sealing resin is formed in the cavity 1a. 2 is injected, and the semiconductor element 4 is hermetically sealed with the resin 2. A side electrode 3 is provided on the periphery of the circuit board 1.
And the electrode of the semiconductor element 4 are electrically connected by a bonding wire 5.
【００１６】ここで、回路基板１に形成されるキャビテ
ィ１ａは半導体素子４を実装するために必要な部分に形
成する。この場合、回路基板１の周囲に残った基板の立
上った一部により、基板１上に樹脂２を保持する堰部１
ｂを構築する。キャビティ１ａ間を仕切る回路基板１の
立上った一部により、回路基板１上の樹脂盛付領域１ｃ
を長さ方向に分断する桟６を形成する。半導体素子４を
埋め込む場合、キャビティ１ａの深さは０．６〜１．０
ｍｍ程度であり、この深さの場合、形成される桟６の幅
は最小０．２ｍｍ程度までの形成が可能である。寸法的
に許容されるならば、桟６の幅は広い方が基板の反りを
抑える効果は大きい。前述したとおり、封止樹脂として
エポキシ樹脂を用いた場合、この硬化収縮によって基板
１の反りが発生するが、特に本実施例のように回路基板
１の周囲に側面電極３を設けた表面実装タイプのパッケ
ージの場合に基板の反りの問題は大きい。回路基板１の
一辺の長さが２５〜３０ｍｍになると、対策を行ってい
ないパッケージの場合、反りが３００μｍを超える場合
が発生し、実装に支障を来す。これに対し、本実施例の
桟６を幅約３ｍｍとして形成しておくと、反りは約１０
０μｍ程度に抑えられる。Here, the cavity 1a formed in the circuit board 1 is formed in a portion necessary for mounting the semiconductor element 4. In this case, the weir portion 1 holding the resin 2 on the substrate 1 is formed by a part of the substrate remaining around the circuit substrate 1.
Construct b. The resin mounting area 1c on the circuit board 1 is formed by the rising part of the circuit board 1 partitioning between the cavities 1a.
Are formed in the longitudinal direction. When the semiconductor element 4 is embedded, the depth of the cavity 1a is 0.6 to 1.0.
mm, and at this depth, the width of the formed bar 6 can be formed to a minimum of about 0.2 mm. If the dimensions are permissible, the wider the bar 6 is, the greater the effect of suppressing the warpage of the substrate is. As described above, when epoxy resin is used as the sealing resin, the curing shrinkage causes the substrate 1 to warp. In particular, the surface mounting type in which the side electrodes 3 are provided around the circuit board 1 as in this embodiment. In the case of the package described above, the problem of substrate warpage is great. If the length of one side of the circuit board 1 is 25 to 30 mm, in the case of a package for which no countermeasures are taken, the warp may exceed 300 μm, which hinders mounting. On the other hand, if the bar 6 of this embodiment is formed to have a width of about 3 mm, the warp is about 10 mm.
It can be suppressed to about 0 μm.
【００１７】（実施例２）図２（ａ）及び（ｂ）は本発
明の実施例２を示す平面図及び断面図である。本実施例
は実施例１と比較して桟６を途中まで形成した形状と
し、残りを溝７状に残した構造としたものである。この
ような構造をとることによって、各半導体素子４を封止
しているキャビティ１ａ内の樹脂高さを均一化し、基板
１の反りを抑える構造とすることができる。(Embodiment 2) FIGS. 2A and 2B are a plan view and a sectional view showing Embodiment 2 of the present invention. The present embodiment is different from the first embodiment in that the crosspiece 6 has a partially formed shape and the remaining portion is left in a groove 7 shape. With such a structure, the height of the resin in the cavity 1a that seals each semiconductor element 4 can be made uniform, and a structure in which the warpage of the substrate 1 is suppressed can be achieved.
【００１８】（実施例３）図３（ａ）及び（ｂ）は本発
明の実施例３を示す平面図及び断面図である。本実施例
は、回路基板１′に樹脂枠８を立上げて取り付け、樹脂
枠８により、基板１′の周囲に設けられて樹脂２を基板
１′上に保持する堰部１ｂを構築し、さらに樹脂枠８の
開口部を長さ方向に分断するように樹脂枠８の肉厚を厚
くして桟６′を形成する。本実施例のように、封止樹脂
面積を分断する構造は樹脂枠を用いた樹脂封止構造にも
適用できる。(Embodiment 3) FIGS. 3A and 3B are a plan view and a cross-sectional view showing Embodiment 3 of the present invention. In the present embodiment, a resin frame 8 is set up on a circuit board 1 'and attached to the circuit board 1' to construct a weir portion 1b provided around the substrate 1 'and holding the resin 2 on the substrate 1', Further, the cross section 6 'is formed by increasing the thickness of the resin frame 8 so as to divide the opening of the resin frame 8 in the length direction. As in the present embodiment, the structure for dividing the sealing resin area can be applied to a resin sealing structure using a resin frame.
【００１９】（実施例４）図４は、本発明の実施例４を
示す平面図である。本実施例は、回路基板１の形状が正
方形であり、実装する半導体素子４のサイズに比して、
回路基板１の一辺が大きい場合に、基板１上での封止樹
脂２の盛付領域を四分割するように桟６′′を形成した
ものである。本例のように、回路基板サイズと半導体素
子サイズ及び実装配置によって桟による封止部の分割は
任意に設定できる。(Embodiment 4) FIG. 4 is a plan view showing Embodiment 4 of the present invention. In this embodiment, the shape of the circuit board 1 is square, and the size of the semiconductor element 4 to be mounted is
In the case where one side of the circuit board 1 is large, a bar 6 ″ is formed so as to divide the area where the sealing resin 2 is applied on the board 1 into four parts. As in this example, the division of the sealing portion by the crosspiece can be arbitrarily set according to the circuit board size, the semiconductor element size, and the mounting arrangement.
【００２０】[0020]
【発明の効果】以上説明したように、本発明は回路基板
上に半導体素子を実装し、樹脂封止する構成において、
回路基板上での樹脂盛付領域を個々に分断し、樹脂硬化
時に回路基板に加わる反り力を小さくしたため、回路基
板の反りを低減でき、実装性を向上させることができ
る。As described above, the present invention relates to a structure in which a semiconductor element is mounted on a circuit board and sealed with a resin.
Since the resin mounting area on the circuit board is individually divided to reduce the warping force applied to the circuit board when the resin is cured, the warpage of the circuit board can be reduced, and the mountability can be improved.
【００２１】また、基板の座ぐり加工により桟形成を行
う場合には、座ぐり面積を低減させ、座ぐり加工の費用
を低く抑えることができるとともに、封止樹脂量を少な
くすることができるため、コスト低減を図ることができ
る。In addition, when the crosspiece is formed by counterboring the substrate, the counterbore area can be reduced, the cost of the counterbore processing can be reduced, and the amount of sealing resin can be reduced. Therefore, cost can be reduced.
【００２２】また、桟形成を樹脂枠を用いて行なう場合
に、樹脂枠は型枠成形で製造することができ、座ぐり加
工により桟形成を行う場合に比較して製造コストを低減
することができる。In the case where the crosspiece is formed by using a resin frame, the resin frame can be manufactured by molding, and the manufacturing cost can be reduced as compared with the case where the crosspiece is formed by spot facing. it can.
【図１】（ａ）は本発明の実施例１を示す平面図、
（ｂ）は同断面図である。FIG. 1A is a plan view illustrating a first embodiment of the present invention,
(B) is the same sectional view.
【図２】（ａ）は本発明の実施例２を示す平面図、
（ｂ）は同断面図である。FIG. 2A is a plan view showing a second embodiment of the present invention,
(B) is the same sectional view.
【図３】（ａ）は本発明の実施例３を示す平面図、
（ｂ）は同断面図である。FIG. 3A is a plan view showing a third embodiment of the present invention,
(B) is the same sectional view.
【図４】本発明の実施例４を示す平面図である。FIG. 4 is a plan view showing a fourth embodiment of the present invention.
【図５】（ａ）は従来例を示す平面図、（ｂ）は同断面
図である。5A is a plan view showing a conventional example, and FIG. 5B is a sectional view of the same.
１ 回路基板 ２ 封止樹脂 ３ 側面電極 ４ 半導体素子 ５ ボンディングワイヤ ６ 桟 ７ 溝 ８ 樹脂枠 DESCRIPTION OF SYMBOLS 1 Circuit board 2 Sealing resin 3 Side electrode 4 Semiconductor element 5 Bonding wire 6 Bar 7 Groove 8 Resin frame
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/28 H01L 23/12──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 23/28 H01L 23/12
Claims (2)
樹脂で半導体素子を気密封止した半導体装置であって、前記回路基板は、ガラスエポキシ材を素材とし、堰部と
樹脂分断部とを組合せて形成された凹部であるキャビテ
ィを一主面上に有し、 前記キャビティは、前記樹脂の盛付領域内に位置すると
ともに、前記半導体素子を受け入れるものであり、 前記堰部と前記樹脂分断部は、前記回路基板に設けられ
た前記キャビティの側壁をなす基板の立ち上がり部によ
り構成されたものであって、 前記樹脂は、前記堰部及び前記樹脂分断部を越えること
なく前記凹部内に設けられ、 前記半導体素子は、前記回路基板の一主面上の前記凹部
に実装され、前記回路基板の裏面にて実装基板に接続さ
れるもの であることを特徴とする半導体装置。A plurality of semiconductor elements mounted on a circuit board;
A semiconductor device in which a semiconductor element is hermetically sealed with a resin, wherein the circuit board is made of a glass epoxy material,
Cavity, which is a recess formed by combining with a resin dividing part
The cavity on one main surface, and the cavity is located within the resin deposition area.
Both accept the semiconductor element, and the dam section and the resin dividing section are provided on the circuit board.
Of the substrate forming the side wall of the cavity.
Be one that is constituted Ri, the resin may exceed the weir portions and the resin divided portion
And the semiconductor element is provided in the concave portion on one main surface of the circuit board.
Mounted on the back of the circuit board and connected to the mounting board.
Wherein a is intended to be.
樹脂で半導体素子を気密封止した半導体装置であって、前記回路基板は、ガラスエポキシ材を素材とし、堰部と
樹脂分断部とを組合せて形成された凹部であるキャビテ
ィを一主面上に有し、 前記キャビティは、前記樹脂の盛付領域内に位置すると
ともに、前記半導体素子を受け入れるものであり、 前記堰部と前記樹脂分断部は、前記回路基板上に立上げ
て装着されて前記キャビティを形成する樹脂枠により構
成されたものであって、 前記樹脂は、前記堰部及び前記樹脂分断部を越えること
なく前記凹部内に設けられ、 前記半導体素子は、前記回路基板の一主面上の前記凹部
に実装され、前記回路基板の裏面にて実装基板に接続さ
れるもの であることを特徴とする半導体装置。2. A semiconductor device comprising: a plurality of semiconductor elements mounted on a circuit board;
A semiconductor device in which a semiconductor element is hermetically sealed with a resin, wherein the circuit board is made of a glass epoxy material,
Cavity, which is a recess formed by combining with a resin dividing part
The cavity on one main surface, and the cavity is located within the resin deposition area.
Both of them receive the semiconductor element, and the dam section and the resin dividing section rise on the circuit board.
The frame is formed by a resin frame
Was made, the resin is in excess of the weir portions and the resin divided portion
And the semiconductor element is provided in the concave portion on one main surface of the circuit board.
Mounted on the back of the circuit board and connected to the mounting board.
Wherein a is intended to be.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7014344A JP2861847B2 (en) | 1995-01-31 | 1995-01-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7014344A JP2861847B2 (en) | 1995-01-31 | 1995-01-31 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08213516A JPH08213516A (en) | 1996-08-20 |
| JP2861847B2 true JP2861847B2 (en) | 1999-02-24 |
Family
ID=11858462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7014344A Expired - Lifetime JP2861847B2 (en) | 1995-01-31 | 1995-01-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2861847B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100505391B1 (en) * | 1997-12-16 | 2005-11-14 | 주식회사 하이닉스반도체 | Semiconductor and manufacture method |
| JP5765488B2 (en) * | 2012-09-17 | 2015-08-19 | 株式会社村田製作所 | Circuit board module |
| JP6163886B2 (en) * | 2013-06-03 | 2017-07-19 | 株式会社デンソー | Mold package |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02101546U (en) * | 1989-01-27 | 1990-08-13 | ||
| JPH03227558A (en) * | 1990-07-26 | 1991-10-08 | Ibiden Co Ltd | Electronic component mounting board |
| JP2974819B2 (en) * | 1991-06-05 | 1999-11-10 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| JPH0521701A (en) * | 1991-07-11 | 1993-01-29 | Nec Corp | Hybrid integrated circuit device |
| JPH0629427A (en) * | 1991-12-24 | 1994-02-04 | Sumitomo Bakelite Co Ltd | Semiconductor mounting substrate |
-
1995
- 1995-01-31 JP JP7014344A patent/JP2861847B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08213516A (en) | 1996-08-20 |
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