JP2855899B2 - Function memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a functional memory for processing data such as images at high speed.

[0002]

2. Description of the Related Art Some algorithms for data processing perform the same processing on a large amount of data. However, when the amount of data is large, processing with a single processor takes a very long time. In the case of such processing, for example, in the case of image processing, there is a degree of parallelism corresponding to the number of pixels, and if the degree of parallelism can be utilized, processing can be performed at very high speed. Therefore, FIG.
As shown in FIG. 1, a memory unit 71, an arithmetic processing unit 72 composed of a large number of arithmetic units and register groups arranged one-dimensionally, and a row memory 73 for inputting / outputting row data at high speed on the same LSI. There is an integrated functional memory. This functional memory allows the arithmetic processing unit 72 to perform high-speed processing on data held in the memory unit 71 row by row. The arithmetic unit in the arithmetic processing unit 72 can transfer data with an adjacent arithmetic unit. Further, by using the row memory 73, row data can be continuously input / output at high speed sequentially from the end. This method is described in Japanese Patent Application No. 3-119543.

[0003] On the other hand, when processing two-dimensional data such as an image, there are two types: one that needs to input and output data at high speed in the row direction and one that needs to input and output data at high speed in the column direction. There is. Therefore, there is a memory called an orthogonal memory as shown in FIG. This is a technique in which data input / output between the outside and the memory cell 81 can be performed at once for both the row direction and the column direction for the bit width of the memory cell. This method is described in, for example, IEICE Electronics Device Research Group, EDD-85, 36-40, 13
Page 20.

[0004]

In the conventional method, FIG.
In the case of the functional memory shown in (1), there is a problem that the operation in units of rows of the image can be performed at high speed but the operation in units of columns cannot be performed, and there is a problem that the input / output of the column data cannot be performed at high speed. In the case of an orthogonal memory as shown in FIG.
The feature is that data of the width of the memory cell can be input and output at high speed in parallel in the row direction and column direction of the image.
As shown in FIG. 9, by arranging a number of processors 92 that perform processing in units of rows and a number of processors 93 that perform processing in units of columns outside the memory chip 91, the operations in units of rows and columns are performed at high speed. Can be done. But,
Since it is necessary to connect a large number of processors outside the memory chip 91, the scale of the device becomes large. Also, if the capacity of the memory cell 94 is increased, the number of input / output signal lines is increased. There is a problem that it is difficult to realize a high-capacity orthogonal memory.

SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem, to perform processing in units of rows and in units of columns at high speed, and to perform input / output of both row data and column data at high speed. It is to provide a functional memory capable of performing the following.

[0006]

A functional memory according to a first aspect of the present invention is a functional memory having a memory unit and an arithmetic processing unit on the same LSI, which holds data and simultaneously stores the data in a column direction and a row direction. Orthogonal memory cells capable of transferring data corresponding to the bit width, a row register group capable of holding data for a plurality of rows of the orthogonal memory cells, and means for selecting one row register from the row register group; , One or more row memories capable of holding data for one row of the orthogonal memory cell, and continuously output data on the row memory sequentially from the end, or continuously output data on the row memory sequentially from the end And a plurality of arithmetic units connected one-dimensionally, broadcast an external instruction to all the arithmetic units, and perform parallel arithmetic processing on data held in the row register group. And return the result A row arithmetic unit capable of writing data to a star group and transferring data between adjacent arithmetic units; a means for decoding a row address input from the outside to select one row on an orthogonal memory cell; One row of data on a cell is transferred to a row register group or a row memory at a time, or one row of data on a row register group or a row memory is transferred at a time to a selected row on an orthogonal memory cell. Means for transferring data to a plurality of columns of orthogonal memory cells, means for selecting one column register from the group of column registers, and means for transferring data for one column of orthogonal memory cells. One or more column memories that can be held, a means for continuously outputting data on the column memory sequentially from the end, and a means for continuously inputting data on the column memory sequentially from the end; Contact By a plurality of arithmetic units has, broadcast instruction from the outside to all of the arithmetic unit,
A column operation unit that can perform parallel arithmetic processing on the data held in the column register group, write the result to the column register group, and transfer data between adjacent operation units, and a column address input from the outside And a means for selecting one column on the orthogonal memory cell, transferring data of the selected one column on the orthogonal memory cell to the column register group or the column memory at a time, Means for transferring the data in the upper one column to a selected column on the orthogonal memory cell at a time.

A functional memory according to a second aspect of the present invention is the functional memory according to the first aspect, wherein data on the row memory is sequentially transferred from the end to the column memory, or data on the column memory is transferred to the row memory from the end. , And a means for sequentially transferring the data in order from.

A functional memory according to a third aspect of the present invention is the functional memory according to the first aspect of the present invention, wherein the functional memory has a plurality of row memories and column memories, and sequentially transfers data on an arbitrary row memory to an arbitrary column memory from an end in order. Or a means for sequentially transferring data from an arbitrary column memory to an arbitrary row memory sequentially from an end between a plurality of row memories and a column memory.

A functional memory according to a fourth aspect of the present invention is the functional memory according to the first aspect, wherein the selected one of the orthogonal memory cells is selected.
The data for one row is transferred to the column memory at one time, the data for one row on the column memory is transferred to the selected row on the orthogonal memory cell at one time,
It is characterized by having means for transferring data for a column to the row memory at a time, or transferring data for one row on the row memory to a selected column on the orthogonal memory cell at a time.

According to a fifth aspect of the present invention, there is provided a functional memory comprising:
Alternatively, the functional memory according to the fourth aspect of the present invention is characterized in that the functional memory has means for inputting / outputting data to / from an orthogonal memory element specified by an externally applied row address and column address.

According to a sixth aspect of the present invention, there is provided a functional memory comprising:
In the functional memory according to the third, fourth or fifth aspect of the present invention, the instruction for instructing data transfer between the orthogonal memory cell and the row register group, the row memory, the column register group, and the column memory; Instructions for instructing data transfer, instructions for instructing data transfer between adjacent computing units in row computing units and column computing units, and instructions for instructing computations in row computing units and column computing units A program memory for storing a series of instructions, a means for inputting a program to the program memory, and instructions stored in the program memory are read one by one in order, and the arithmetic unit performs an operation. It has means for instructing the data transfer circuit to instruct data transfer, means for instructing the start of the program from the outside, and means for notifying the end of the execution of the program to the outside.

[0012]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the functional memory according to the first invention. This function memory is
An orthogonal memory cell 11 for holding data, a row register group 12 capable of holding data for a plurality of rows of the orthogonal memory cell 11, a row register selection circuit 24 for selecting one row register from the row register group 12, One or more row memories 13 capable of holding data for one row of the orthogonal memory cell 11 and data in the row memory 13 are continuously output in order from the end, And a plurality of arithmetic units connected in a one-dimensional manner. The external instruction is broadcast to all the arithmetic units, and is stored in the row register group 12. The arithmetic operation is performed on the data in parallel, the result is written into the row register group 12, the data is transferred between the adjacent arithmetic units, and the row arithmetic unit 15 which can transfer the data is decoded. A row decoder 16 for selecting one row on the orthogonal memory cell 11, transferring the data for the selected one row on the orthogonal memory cell 11 to the row register group 12 or the row memory 13 at one time, A row transfer circuit 1 for transferring one row of data on the register group 12 or the row memory 13 to a selected row on the orthogonal memory cell 11 at a time
7, a column register group 18 capable of holding data of a plurality of columns of the orthogonal memory cell 11, and a column register group 18
Column selection circuit 2 for selecting one column register from
5, one or more column memories 19 capable of holding data for one column of the orthogonal memory cell 11, and a column memory 19
It has a column memory input / output circuit 20 for continuously outputting the above data in order from the end, and continuously inputting data to the column memory 19 in order from the end, and a plurality of one-dimensionally connected arithmetic units. Then, an external instruction is broadcast to all the arithmetic units, and the data held in the column register group 18 is processed in parallel, and the result is written to the column register group 18 or data is transferred between adjacent arithmetic units. Column computing unit 21 capable of performing
A column decoder 22 for decoding a column address input from the outside and selecting one column on the orthogonal memory cell 11;
Data of one column selected in the orthogonal memory cell 11 is transferred to the column register group 18 or the column memory 19 at a time, or data of one column in the column register group 19 or the column memory 18 is transferred to the orthogonal memory It comprises a column transfer circuit 23 for transferring data to a selected column on the cell 11.

In the functional memory having such a configuration, when the same arithmetic processing is performed on each data on a row in the memory, the processing is performed in the following procedure. First, a row address is given to the row decoder 16 to select a row on the orthogonal memory cell 11, and the row transfer circuit 17 transfers the row address from the orthogonal memory cell 11 to the row register in the row register group 12 selected by the row register selecting circuit 24. Transfer the data to be processed. If the data to be processed covers a plurality of rows, this is repeated a plurality of times while changing the row register selected by the row register selection circuit 24. Next, the row operation unit 15 sets the row register group 12 in accordance with the instruction sequence given from the outside.
The above data is processed in parallel. Finally, the row transfer circuit 17 stores the result of the operation on the row register selected by the row register selection circuit 24 on the row register group 12 in the row where the result on the orthogonal memory cell 11 selected by the row decoder 16 is to be stored. To transfer. Thus, the orthogonal memory cell 11
The above data can be processed in a row unit in parallel by the row calculator 15, and high-speed processing can be easily realized.

When the same arithmetic processing is performed on each data on a certain column in the memory, the processing is performed in the following procedure. First, a column address is given to the column decoder 22 to select a column on the orthogonal memory cell 11, and the column transfer circuit 23 transfers the column address from the orthogonal memory cell 11 to the column register selected by the column register selection circuit 25 in the column register group 18. Transfer the data to be processed. If the data to be processed covers a plurality of columns, this is repeated a plurality of times while changing the column register selected by the column register selection circuit 25. Next, the column operation unit 21 performs an arithmetic operation on the data on the column register group 18 in parallel according to an instruction sequence given from the outside. Finally, the column transfer circuit 23 stores the operation result on the column register selected by the column register selection circuit 25 on the column register group 18 in the column where the result on the orthogonal memory cell 11 selected by the column decoder 22 is to be stored. To transfer. In this manner, the data on the orthogonal memory cells 11 can be processed in parallel by the column operation unit 21 in column units, and high-speed processing can be easily realized.

Next, when sequentially outputting data of a certain row on the orthogonal memory cell 11 from the end to the outside, first,
The row decoder 16 decodes an externally applied row address, selects a row on the orthogonal memory cell 11, and the row transfer circuit 17 transfers data of the selected row to one of the row memories 13. Then, the row memory input / output circuit 14 continuously outputs data on the row memory 13 in order from the end.

When row data is successively input from the outside in order from the end and stored in a certain row on the orthogonal memory cell 11, first, the row memory input / output circuit 14 inputs data from the outside, and the row memory 13 In one of them. Next, the row address given from the outside is decoded by the row decoder 16, and a row on the orthogonal memory cell 11 is selected.
The row transfer circuit 17 transfers the above data to the selected row.

When sequentially outputting data of a certain column on the orthogonal memory cell 11 to the outside in order from the end, first, a column address given from the outside is decoded by the column decoder 22, and the column address on the orthogonal memory cell 11 is And the column transfer circuit 23 transfers the data of the selected column to one of the column memories 19. Then, the column memory input / output circuit 20 continuously outputs data on the column memory 19 in order from the end.

When column data is successively input from the outside in order from the end and stored in a certain column on the orthogonal memory cell 11, first, the column memory input / output circuit 20 inputs data from the outside and the column memory 19 In one of them. Next, the column address given from the outside is decoded by the column decoder 22, and a column on the orthogonal memory cell 11 is selected.
The column transfer circuit 23 transfers the above data to the selected column.

The row memory 13 and the column memory 19 store the SR
AM or shift register,
In the case of an SRAM, the row memory input / output circuit 14 and the column memory input / output circuit 20 access the SRAM while increasing the address one by one. In the case of a shift register, the row memory input / output circuit 14 and the column memory input / output circuit 20 transfer data between the shift register and the outside by applying a shift clock. When a shift register is used for the row memory 13 and the column memory 19, the data read from the orthogonal memory cell 11 is shifted by giving a shift clock an appropriate number of times, and then written to the orthogonal memory cell 11 again. The same effect as the data transfer between the computing units can be realized.

The above arithmetic processing and data input / output processing
As long as contention for access to the orthogonal memory cells 11 does not occur, all the operations can be performed in parallel.

A plurality of bits on the orthogonal memory cell 11 form one word, and the row register group 12 and the row memory 1
3, the row memory input / output circuit 14, the row operation unit 15, the column register group 18, the column memory 19, the column memory input / output circuit 20, and the column operation unit 21 are all configured in a word configuration, so that processing in word units can be performed. Function memory to be implemented.
FIG. 10 shows an example of the correspondence between the bits of the orthogonal memory cell 11 and the bits of the row memory 13 and the column memory 19 in the functional memory that performs such word-unit processing. FIG. 10 shows a 16 bit ×
FIG. 3 is a diagram for explaining a bit configuration of an orthogonal memory cell 101 having a 16-bit configuration and a row memory 102 and a column memory 103 having an 8-word configuration. However, one word is assumed to be 4 bits. As shown in FIG. 10, the orthogonal memory cell 101 is divided into 2 bits × 2 bits, and the 4 bits are assigned to one word. It is assumed that the order of the bits in the word is assigned in the order of writing on the orthogonal memory cell 101 in FIG.

A case where data in the row memory 102 is transferred to the orthogonal memory cell 101 in the functional memory having such a configuration will be described. First, the data of all the bits of the word on the row memory 102 are transferred to the row allocated to the data on the orthogonal memory cell 101 at one time. Next, the data with the bits of all the words on the row memory 102 is stored in the orthogonal memory cell 1.
01, the data is transferred at a time to the line next to the line transferred earlier, that is, the line assigned to the data. Thus, the data of all the words in the row memory 102 can be transferred to the orthogonal memory cells 101 by transferring the rows twice.

Next, a case where data stored in the orthogonal memory cell 101 is transferred to the column memory 103 will be described. First, of the two columns of the orthogonal memory cell 101 that hold data to be transferred to the column memory 103,
Is stored in the column memory 10
3 at a time and stored in the column memory 103 at the position indicated by. Next, the data of the column holding the bits and is transferred to the column memory 103 at once, and
3 and stored in the position of In this manner, data in the orthogonal memory cell 101 can be transferred to the column memory 103 by transferring the column twice.

Further, the transfer from the orthogonal memory cell 101 to the row memory 102 and the transfer from the column memory 103 to the orthogonal memory cell 101 are performed in the same manner. Also, the row register group 12 and the column register group 18 in FIG.

FIG. 2 is a block diagram showing the configuration of an embodiment of the functional memory according to the second invention. This function memory is
In addition to the configuration of FIG. 1, an inter-matrix data transfer circuit 26 for continuously transferring data between the row memory 13 and the column memory 19 in order from the end is provided.

In the functional memory having such a configuration, data in the orthogonal memory cell 11 is transferred to the column memory 19,
It is transferred to the row memory 13 by the matrix data transfer circuit 26.
, And by transferring it to the orthogonal memory cell 11, the column data of the two-dimensional data on the orthogonal memory cell 11 can be converted into row data.

The data in the orthogonal memory cell 11 is transferred to the row memory 13 and the data is transferred to the inter-matrix data transfer circuit 26.
Is transferred to the column memory 19, and further transferred to the orthogonal memory cell 11, whereby the orthogonal memory cell 1
The row data of the two-dimensional data on 1 can be converted to column data.

As described above, if the column data is converted to the row data or the row data is converted to the column data, the row operation unit 15
The matrix operation can be performed on the column operation unit 21.

The row memory 13 and column memory 19 to which data is transferred by the inter-matrix data transfer circuit 26
Data input / output by the row memory input / output circuit 14 or the column memory input / output circuit 20 is prohibited. However, the data being transferred is transferred to the row memory input / output circuit 14 or the column memory input / output circuit 2.
0 can be output simultaneously with the transfer. Also,
Data is input to the row memory 13 and the column memory 19 by the row memory input / output circuit 14 and the column memory input / output circuit 20, and at the same time, the data is transferred to the column memory 19 and the row memory 13 by the inter-matrix data transfer circuit 26. It is also possible.

FIG. 3 is a block diagram showing the configuration of an embodiment of the functional memory according to the third invention. This function memory is
A plurality of row memories 13 and a plurality of column memories 19 are provided. In addition to the configuration of FIG.
9 is provided with an inter-column data transfer circuit 31 for sequentially transferring data sequentially from the end.

In the functional memory having such a configuration, the inter-matrix data transfer circuit 31 is constituted by a crossbar switch, and data can be transferred in parallel by an arbitrary combination of the row memory 13 and the column memory 19.

The data on the orthogonal memory cell 11 is transferred to the column memory 19, transferred to the row memory 13 by the inter-matrix data transfer circuit 31, and further transferred to the orthogonal memory cell 11. 11 can be converted into row data.

The data in the orthogonal memory cell 11 is transferred to the row memory 13 and the data is transferred to the inter-matrix data transfer circuit 31.
Is transferred to the column memory 19, and further transferred to the orthogonal memory cell 11, whereby the orthogonal memory cell 1
The row data of the two-dimensional data on 1 can be converted to column data.

As described above, if the column data is converted to the row data or the row data is converted to the column data, the row operation unit 15
The matrix operation can be performed on the column operation unit 21.

FIG. 4 is a block diagram showing the configuration of an embodiment of the functional memory according to the fourth invention. This function memory is
In addition to the configuration of FIG. 1, data of one selected row on the orthogonal memory cell 11 is transferred to the column memory 19 at a time,
The data of one row on the column memory 19 is transferred to the selected row on the orthogonal memory cell 11 at one time, or the data of one selected column on the orthogonal memory cell 11 is transferred on the row memory 1 at a time.
3 or an inter-matrix parallel data transfer circuit 41 for transferring data of one row in the row memory 13 to a selected column in the orthogonal memory cell 11 at a time.

In the functional memory having such a configuration, the inter-parallel parallel data transfer circuit 41 has a signal line corresponding to the bit width of the orthogonal memory cell 11, and
It is realized by passing the wiring over. While the functional memory shown in FIGS. 2 and 3 sequentially transfers data to exchange data between rows and columns, the inter-parallel parallel data transfer circuit 41 Data can be transferred.

As described above, the column data can be converted into the row data and the row data can be converted into the column data at high speed, so that the matrix operation is performed at high speed on the row calculator 15 and the column calculator 21. be able to.

Since data can be transferred at high speed between rows and columns by the inter-matrix parallel data transfer circuit 41, the column register group 18, the column register selection circuit 25, the column memory 1
9, the functions of the column memory input / output circuit 20, the column operation unit 21, and the column data transfer circuit 23 are described by the row register group 12, the row register selection circuit 24, the row memory 13, and the row memory input / output circuit 1.
4. It can be realized by the row operation unit 15 and the row data transfer circuit 17, and the number of pins and the chip size can be reduced. FIG. 11 shows the configuration of such a functional memory. In the case of the functional memory having the configuration as shown in FIG. 11, the data on the orthogonal memory cell 11 includes both row data and column data.
Data transfer with the outside is performed using the row memory 13 and the row memory input / output circuit 14, and calculations are performed using the row register group 12, the row register selection circuit 24, and the row calculator 15.

FIG. 5 is a block diagram showing the configuration of an embodiment of the functional memory according to the fifth invention. This function memory is
In addition to the configuration of FIG. 1, a data input / output circuit 51 for inputting / outputting data between bits on the orthogonal memory cell 11 designated by the row decoder 16 and the column decoder 22 and the outside is provided.

In the functional memory having such a configuration, when none of the row register group 12, the row memory 13, the column register group 18, and the column memory 19 transfer data with the orthogonal memory cell 11, they are externally connected. The connected device can randomly access the orthogonal memory cell 11 through the data input / output circuit 51.

FIG. 6 is a block diagram showing the configuration of an embodiment of the functional memory according to the sixth invention. This function memory is
In addition to the configuration of FIG. 1, an instruction for instructing data transfer between the orthogonal memory cell 11 and the row register group 12, the row memory 13, the column register group 18, and the column memory 19,
A program memory 61 for storing a series of instructions such as an instruction for instructing an operation in the row arithmetic unit 15 and the column arithmetic unit 21; and a program memory input circuit for externally inputting a program to the program memory 61 62 and the instructions held in the program memory 61 are read out one by one in order, to instruct the row operation unit 15 and the column operation unit 21 for the operation, the row decoder 16, the row transfer circuit 17, and the row register selection circuit 24. , A sequencer 63 for instructing data transfer to the column decoder 22, the column transfer circuit 23 and the column register selection circuit 25, a start signal line 64 for instructing the start of the program from the outside, and an end signal for notifying the end of the execution of the program to the outside. A line 65 is provided.

In the functional memory having such a configuration, an instruction sequence of a process to be executed on the functional memory is stored in advance in the program memory 61 on the same LSI through the program memory input circuit 62, thereby realizing the LSI.
Since the processing can be performed without continuously giving instructions from the outside one by one, the external circuit configuration is simplified and the functional memory can be used more easily. When the execution of the program is started through the start signal line 64, the sequencer 63 sequentially fetches the instructions from the program memory 61, and
According to the contents of the instruction, the row operation unit 15 and the column operation unit 2
1. Instruct the row decoder 16, row transfer circuit 17, row register selection circuit 24, column decoder 22, column transfer circuit 23, and column register selection circuit 25 to operate. When the execution of the series of instructions is completed,
Notify the end of processing to the outside. Since this function memory has the sequencer 63 and the program memory 61 on the same LSI, a higher-speed clock can be used, so that the processing speed can be increased.

[0044]

As described above, according to the present invention, orthogonal memory cells, a plurality of one-dimensionally arranged operation units for row operation, and one-dimensionally arranged column operation are provided on the same LSI. By integrating a plurality of arithmetic units, a memory for continuous input / output of row data, and a memory for continuous input / output of column data, the data transfer bandwidth between the memory and the arithmetic unit can be increased in the row direction. Since the direction can be sufficiently wide, an algorithm of applying the same operation to a large amount of data in units of rows or columns can be executed in parallel and at high speed in the LSI. Data can be input and output at high speed both in the direction and in the column direction.
There is an effect that a function of converting the row direction and the column direction of the two-dimensional data on the LSI can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a functional memory according to the first invention.

FIG. 2 is a block diagram showing an embodiment of a functional memory according to the second invention.

FIG. 3 is a block diagram showing an embodiment of a functional memory according to the third invention.

FIG. 4 is a block diagram showing an embodiment of a functional memory according to the fourth invention.

FIG. 5 is a block diagram showing an embodiment of a functional memory according to the fifth invention.

FIG. 6 is a block diagram showing an embodiment of a functional memory according to the sixth invention.

FIG. 7 is a block diagram illustrating a configuration example of a conventional functional memory.

FIG. 8 is a block diagram illustrating a configuration example of a conventional orthogonal memory.

FIG. 9 is a block diagram illustrating a configuration example of a conventional orthogonal memory using system.

FIG. 10 is a diagram for explaining a configuration of orthogonal memory cells and bits of a row memory and a column memory on a functional memory;

FIG. 11 is a block diagram showing an embodiment of a functional memory according to the fourth invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Quadrature memory cell 12 Row register group 13 Row memory 14 Row memory input / output circuit 15 Row arithmetic unit 16 Row decoder 17 Row transfer circuit 18 Column register group 19 Column memory 20 Input / output circuit 21 Column arithmetic unit 22 Column decoder 23 Column transfer circuit 24 row register selection circuit 25 column register selection circuit 31 inter-matrix data transfer circuit 41 inter-matrix parallel data transfer circuit 51 data input / output circuit 61 program memory 62 program memory input circuit 63 sequencer 64 start signal line 65 end signal line 71 memory unit 72 Arithmetic processing unit 73 row memory 81 memory cell 91 memory chip 92 processor 93 processor 94 memory cell 101 orthogonal memory cell 102 row memory 103 column memory

Claims (5)

(57) [Claims] 1. A function memory having a memory unit and an arithmetic processing unit on the same LSI, which can hold data and transfer data of a bit width at a time in a column direction and a row direction at a time. A memory cell, a row register group capable of holding data of a plurality of rows of orthogonal memory cells, a unit for selecting one row register from the row register group, and holding data of one row of the orthogonal memory cell One or more row memories capable of continuously outputting data on the row memory sequentially from the end or a means for continuously inputting data on the row memory sequentially from the end, and one-dimensionally connected. It has a plurality of arithmetic units, broadcasts external instructions to all arithmetic units, performs parallel arithmetic processing on data held in the row register group, writes the result to the row register group,
A row arithmetic unit capable of transferring data between adjacent arithmetic units, means for decoding a row address input from the outside and selecting one row on the orthogonal memory cell, Means for transferring one row of data at a time to a row register group or a row memory, or transferring one row of data on a row register group or a row memory to a selected row on an orthogonal memory cell at a time; A column register group capable of holding data of a plurality of columns of orthogonal memory cells, means for selecting one column register from the column register group, and a column capable of holding data of one column of the orthogonal memory cells One or more memories, means for continuously outputting data on a column memory sequentially from an end, and means for continuously inputting data on a column memory sequentially from an end, and a plurality of one-dimensionally connected operations Have a container Broadcasting external instructions to all arithmetic units, processing data held in column registers in parallel, writing results to column registers, and transferring data between adjacent arithmetic units Column arithmetic unit, means for decoding an externally input column address and selecting one column on an orthogonal memory cell, and a column register group for simultaneously selecting one column of data on the orthogonal memory cell or to transfer to the column memory, means for transferring data for one column on the column register group or column memory to the selected column of the orthogonal memory cell at a time, from the end of the data in the row memory in column memory Roll continuously in order
Data from the column memory to the row memory sequentially from the end.
Means for transferring data continuously . 2. A memory unit and an arithmetic processing unit on the same LSI.
Data in a functional memory with
And data in the row direction at a time for that bit width.
Orthogonal memory cells that can be transmitted and orthogonal memory cells
Row register that can hold multiple rows of data
Group and a means to select one row register from the row register group
Column and holding one row of data in orthogonal memory cells
And one or more row memories that can
Output continuously from the end, or store data in row memory
A means for continuous input from the end and a one-dimensionally connected
It has multiple arithmetic units,
Broadcasts the data stored in the row registers
Operate on columns and write the result to row registers,
Row operation that can transfer data between adjacent operation units
And the row address input from the outside
Means for selecting one row on the intersection memory cell,
Row register group at a time with the data of one selected row on the
Alternatively, transfer to row memory, row register group or
One row of data on the row memory is stored on the orthogonal memory cells at a time.
Means for transferring data to a selected row, and
Column registers that can hold several columns of data
And means for selecting one column register from the column register group
Can hold data for one column of orthogonal memory cells.
One or more column memories that can be
From the end, and output data to the column memory.
Means for inputting continuously from
All of the computing units
And the data held in the column registers
And write the result to the column registers, or
Column arithmetic unit that can transfer data between adjacent arithmetic units
And decode the externally input column address
Means for selecting one column on a memory cell, and orthogonal memory cells
The above selected one column of data is also stored in the column registers at once.
Or to column memory, column registers or columns
One column of data on the memory is stored on the orthogonal memory cell at a time.
Means for transferring data to a selected column, and data on an arbitrary row memory having a plurality of row memories and column memories.
Data to any column memory sequentially from the end,
Data from any column memory to any row memory from end to end
Continuous transfer to multiple row and column memories
Function memo characterized by having means for performing parallel processing between
Ri. 3. A memory unit and an arithmetic processing unit on the same LSI.
Data in a functional memory with
And data in the row direction at a time for that bit width.
Orthogonal memory cells that can be transmitted and orthogonal memory cells
Row register that can hold multiple rows of data
Group and a means to select one row register from the row register group
Column and holding one row of data in orthogonal memory cells
And one or more row memories that can
Output continuously from the end, or store data in row memory
A means for continuous input from the end and a one-dimensionally connected
It has multiple arithmetic units,
Broadcasts the data stored in the row registers
Operate on columns and write the result to row registers,
Row operation that can transfer data between adjacent operation units
And the row address input from the outside
Means for selecting one row on the intersection memory cell,
Row register group at a time with the data of one selected row on the
Alternatively, transfer to row memory, row register group or
One row of data on the row memory is stored on the orthogonal memory cells at a time.
Means for transferring data to a selected row, and
Column registers that can hold several columns of data
And means for selecting one column register from the column register group
Can hold data for one column of orthogonal memory cells.
One or more column memories that can be
From the end, and output data to the column memory.
Means for inputting continuously from
All of the computing units
And the data held in the column registers
And write the result to the column registers, or
Column arithmetic unit that can transfer data between adjacent arithmetic units
And decode the externally input column address
Means for selecting one column on a memory cell, and orthogonal memory cells
The above selected one column of data is also stored in the column registers at once.
Or to column memory, column registers or columns
One column of data on the memory is stored on the orthogonal memory cell at a time.
Means for transferring data to a selected column, and data for a selected row on an orthogonal memory cell at a time
Transfer to the column memory or transfer one row of data in the column memory
Transfer to the selected row on the orthogonal memory cell at once,
Select one column of data on the orthogonal memory cells at once
Transfer to the row memory or transfer one row of data in the row memory
Means to transfer to selected columns on orthogonal memory cells at once
A functional memory comprising: 4. An externally applied row address and column
The orthogonal memory element and data specified by the address are
3. The system according to claim 1, further comprising means for inputting and outputting.
Or the functional memory according to 3. 5. An orthogonal memory cell, a row register group, and a row memory.
Memory, column registers and column memory
Instructions to indicate or data between row and column memory
Command to instruct data transfer, or row and column
Instructions for instructing data transfer between adjacent arithmetic units,
Instructions for instructing operations in row arithmetic units and column arithmetic units
Program memory for storing a series of instructions
Means for inputting a program to the program memory;
Read the instructions held in the program memory one by one
Start and instruct the arithmetic unit to calculate, or send data to the data transfer circuit.
A means for instructing data transfer and an external program
Means for instructing the execution of the
And means for notifying.
The functional memory according to 2, 3, or 4.