JP2853845B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with a MOS (metal-oxide-semiconductor) type mask ROM (read only memory) capable of obtaining a multi-value output level and a method of manufacturing the same.

[0002]

2. Description of the Related Art MOS type masks R which are currently commercialized
Most OMs store binary information in one memory cell.

In order to increase the capacity of the ROM and reduce the chip area, it is effective to store multi-valued information in one memory cell. For example,
JP-A-59-148360 and JP-A-61-2
No. 63263 discloses a method of obtaining a multi-level output level by implanting impurity ions into channel regions of a plurality of transistors constituting a memory cell to make the effective channel width different. FIG. 5 shows an example of a semiconductor device obtained by this method. In this figure, Wf indicates a channel width, W1 to W2 indicate an effective channel width, and a shaded portion indicates an impurity implanted region.
Each transistor constituting the memory cell is configured to perform impurity ion implantation in the entire channel width region (Tr4),
Impurity ion implantation into 2/3 regions (Tr3),
Impurity ion implantation into 1/3 region (Tr2),
And 4 without impurity ion implantation (Tr1)
Are divided into two states. By implanting impurity ions, the threshold voltage of the transistor becomes higher than the power supply voltage, so that the impurity implanted region does not have a function as a channel. Therefore, the effective channel width differs for each transistor, and a quaternary output level can be selected depending on the difference in the driving capability of each transistor. Therefore, this semiconductor device can store 2-bit information.

[0004]

In the above conventional method,
The effective channel width is changed by implanting impurity ions into the channel region. For this reason, even if the minimum impurity ion implantation region (for example, a region of の of the channel width) is formed with the minimum resolution, the channel width is required to be about three times as large. Since the size of the memory cell is about twice as large as that in the case where the memory cell is formed with the minimum size, even if 2-bit multi-valued information is stored in the memory cell, the effect of increasing the capacity and reducing the chip area is reduced. .

The present invention has been made in order to solve the above-mentioned problems, and realizes a multi-valued memory cell by connecting two transistors in parallel to form one memory cell, thereby increasing the capacity. -It is an object to provide a semiconductor device capable of reducing a chip area and a method for manufacturing the same.

[0006]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device in which a memory cell of a MOS type mask ROM is composed of a transistor and obtains a multi-level output level by differentiating the driving capability of the transistor, wherein the memory cell has a channel region on a surface layer of a semiconductor substrate. In a semiconductor device including a parallel circuit of one transistor and a second transistor including a thin film transistor stacked and formed on the first transistor so as to share a gate electrode with the first transistor, the semiconductor device may include a first transistor and a second transistor.
A source region or a drain region of the first transistor;
Are arranged in parallel, and the first wiring
The first wiring intersects the first wiring with one gate insulating film interposed therebetween.
A number of gate electrodes, and the first wiring of the gate electrodes
On the opposite side to the gate via a second gate insulating film
Intersecting the electrode and extending to the source region of the second transistor.
Or a plurality of second wirings serving as drain regions are juxtaposed,
Above the channel region of the first transistor,
A channel of the second transistor formed between the second wirings;
Has a tunnel area, the objects can be achieved.

[0007] The second transistor has its source
A second region on the opposite side to the gate electrode with the rain region
A first gate electrode and a second gate
A double gate structure in which electrodes are electrically connected may be employed .

The method of manufacturing a semiconductor device according to the present invention
A thin film transistor on one transistor
A second transistor is connected in parallel with the first transistor
Forming a semiconductor substrate that has been fabricated,
Then, impurities are added to the channel region of the first transistor.
Ions are implanted with high energy and the second transistor
Impurity ions are implanted at low energy into the channel region of
And writing data to each transistor.
Thus, the above object is achieved.

[0009]

[0010]

[0011]

[0012]

According to the present invention, a second transistor composed of a thin film transistor is formed on a first transistor having a channel region in a surface layer of a semiconductor substrate, and a memory cell is constituted by a parallel circuit of two transistors. When the driving capability of the thin film transistor is formed with the same dimensions (channel width and channel length), the driving capability of the thin film transistor is lower than that of the first transistor having the channel region on the surface layer of the semiconductor substrate.

By implanting impurity ions into the channel regions of the first transistor and the second transistor, the conduction / non-conduction state can be changed by changing the threshold voltage of each transistor. By performing the impurity ion implantation at high energy, impurity ion implantation can be performed at the channel region of the first transistor formed below the second transistor. Impurity ion implantation may be performed on the channel region of the formed second transistor.

By selectively performing ion implantation on the channel regions of the first transistor and the second transistor, two types of first transistors having different threshold voltages can be obtained.
By forming two types of second transistors having different threshold voltages, the driving capability of the memory cell can be set to four states.

The size of the memory cell can be reduced because the second transistor including the thin film transistor is formed on the first transistor.

The gate electrode of the first transistor can be formed as the same layer as the gate electrode of the thin film transistor. In this case, the circuit and the memory cell structure can be simplified.

When the second transistor has a double gate structure of a gate electrode shared with the first transistor and a second gate electrode, ON-OFF of the second transistor is performed.
The ratio can be increased.

The region above the channel region of the first transistor may be the channel region of the second transistor. In this case, the source of the second transistor
The wiring resistance of the drain region can be reduced.

The first and second transistors can be of the same conductivity type. For example, if one is an n-channel MOS, the other is also an n-channel MOS, and if one is a p-channel MOS, the other is also a p-channel MOS. By doing so, the ON / OFF of the first transistor and the ON / OFF of the second transistor are independently controlled, and the multi-value ROM
As a result, four states can be obtained.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3A is a diagram showing a semiconductor device according to one embodiment of the present invention. In this semiconductor device, a gate electrode 4 is provided on a first transistor constituting a memory cell.
, A thin film transistor (second transistor) is formed, and the first transistor and the thin film transistor are connected in parallel.

FIG. 1 shows a configuration of a memory cell of the semiconductor device. 1A shows a plan view, FIG. 1B shows an equivalent circuit, and FIG. 1C shows AA ′ in FIG. 1A.
1 (d) is a cross-sectional view taken along the line BB ′ of FIG. 1 (a), FIG. 1 (e) is a cross-sectional view taken along the line CC ′ of FIG. 1 (a),
FIG. 1F is a cross-sectional view taken along the line DD ′ of FIG.
Each of these figures shows a state before data writing.

This memory cell comprises a parallel circuit of a first transistor and a second transistor comprising a thin film transistor. A plurality of strip-shaped source / drain regions 2 are provided in the surface portion of the semiconductor substrate 1 in parallel with each other. This source / drain region 2 is a source / drain region of the first transistor. On top of that, the first
A plurality of strip-shaped gate electrodes 4 are arranged at predetermined intervals so as to cross the source / drain regions 2 with a gate insulating film (oxide film) 3 interposed therebetween. This gate electrode 4 has a first
The transistor and the thin film transistor are shared as a gate electrode. The substrate surface layer below the gate electrode 4 is a channel region of the first transistor. A second gate insulating film 5 is formed thereon, and a channel region and a source region of the second transistor are formed.
A polycrystalline silicon film 7 serving as a drain region 7a is formed. Then, the source / drain region 2 of the first transistor and the source / drain region 7a of the second transistor are formed by the contact hole 6 formed in the second insulating film 5.
And are connected.

Hereinafter, the manufacture of the semiconductor device will be described.

First, a band-shaped source / drain region 2 of a second conductivity type is formed on a surface layer portion of a semiconductor substrate 1 of a first conductivity type.
A plurality are arranged so as to be parallel to each other.

Next, a plurality of strip-shaped gate electrodes 4 are arranged at predetermined intervals so as to intersect the source / drain regions 2 with the first gate insulating film 3 interposed therebetween.

Thereafter, in order to perform element isolation of the first transistor, a gate electrode 4 is formed on the surface of the substrate 1 in the memory cell portion.
Is used as a mask to implant impurity ions of the first conductivity type in a self-aligned manner. The second gate insulating film 5 is formed so as to cover the substrate 1 in that state.

Next, a contact hole 6 serving as a connection portion between the first transistor and the second transistor is formed on the source / drain region 2 of the second gate insulating film 5 by photolithography and dry etching.
Then, a polycrystalline silicon film 7 is laminated so as to cover the substrate 1 in this state. As a method of forming the polycrystalline silicon film 7, there is a method of laminating polycrystalline silicon or a method of laminating amorphous silicon and polycrystallizing it by a solid phase growth method.

Next, impurity ions for controlling the threshold value of the second transistor are implanted into the entire surface of the wafer.
The second portion of the polycrystalline silicon film 7 except on the gate electrode 4
Impurity ion implantation of the first conductivity type is performed to perform element isolation of the transistor.

When patterning the polycrystalline silicon film 7 in a later step, regions other than the channel region and the source / drain regions are removed by etching.
The photolithography step and the ion implantation step for element isolation can be omitted.

Subsequently, impurity ions of the second conductivity type are implanted into the portion 7a of the polycrystalline silicon film to form source / drain regions 7a of the second transistor. These three types of ion implantation are performed under implantation conditions that do not affect the characteristics of the first transistor.

As described above, a parallel circuit of the first transistor and the second transistor as shown in FIG. 1 is formed.

Next, impurity ions for writing ROM data are implanted into the first transistor and the second transistor. This impurity ion implantation is performed in the first step.
After the transistor is formed (after the impurity ions of the first conductivity type are implanted in a self-aligned manner) and after the second transistor is formed, the steps may be performed separately. A method for performing this will be described. Performing the process after the formation of the second transistor is advantageous in that the process from writing of the ROM data to completion of the wafer is short, and the delivery time of the mask ROM is shortened.

FIG. 2A shows a process of writing ROM data to a second transistor formed of a thin film transistor, and FIG. 2B shows a process of writing ROM data to a first transistor.

Here, as the impurity ions, for example, B
⁺ Ions can be used. The impurity ion implantation 9 into the thin film transistor is performed at a low energy of about 15 to 50 keV, and the impurity ion implantation 1 into the first transistor is performed.
1 is performed at a high energy of about 180 to 400 keV. The implantation energy varies depending on the thickness of the gate electrode 4 and the polycrystalline silicon film 7 and the like, but it is necessary to select optimal implantation conditions so that the impurity concentration in the channel region of each transistor is reliably increased. In order to selectively perform implantation, resist masks 8 and 10 are formed in portions where implantation is not performed. As described above, the threshold voltage of the transistor in which the impurity is implanted into the channel region is higher than the threshold voltage of the transistor in which the impurity is not implanted, and the lower part of FIG. Such various ON / OFF states can be obtained.

Further, an interlayer insulating film 12, a metal wiring 13 and a protective film 14 are formed to obtain a semiconductor device as shown in FIG.

In the obtained semiconductor device, impurity ions are selectively implanted into channel regions of the first transistor and the second transistor in accordance with the ROM data.
The ON / OFF state of each transistor is changed. Table 1 shows combinations of ON / OFF states of the first transistor and the thin film transistor which constitute the memory cell.

[0038]

[Table 1]

In this semiconductor device, since the effective channel width of the second transistor formed of a thin film transistor and the effective channel width of the first transistor are substantially the same, the second transistor is driven more than the first transistor. Ability decreases. Therefore, the driving capability of the memory cell is <<>>, and a semiconductor device having four output levels can be obtained.

Further, since the second transistor including the thin film transistor is formed on the first transistor, the size of the semiconductor device can be reduced.

The semiconductor device of the present invention can have not only the configuration shown in FIG. 3A but also the configuration shown in FIG. This semiconductor device includes a third gate insulating film 15 and a second
The gate electrode 16 is formed, and the second transistor has a double gate structure of the first gate electrode 4 and the second gate electrode 16. With such a structure, the ON-OFF ratio of the second transistor can be increased, and the memory cell characteristics can be improved. This semiconductor device is manufactured by forming the third gate insulating film 15 and the second gate electrode 16 before forming the interlayer insulating film 12.
Can be performed in the same manner as described above.

Further, as shown in FIG. 3C, the gate electrode 4 is provided not to cross the source / drain region 2 but to face the channel region between the source / drain regions 2. It can also be configured. In the manufacture of this semiconductor device, after forming the gate electrode 4, the source / drain regions 2 can be formed by implanting impurity ions into the surface layer of the substrate 1.

[0043]

As is apparent from the above description, according to the present invention, the second transistor comprising the thin film transistor is provided on the first transistor having the channel region on the surface layer of the semiconductor substrate.
Transistors are formed to form a parallel circuit. Therefore, the memory cell at the multi-level output level can be reduced to a smaller memory cell size than before. Therefore, a large-capacity mask ROM can be manufactured.
Cost reduction can be achieved by reducing the chip area.

[Brief description of the drawings]

1A and 1B show a memory cell configuration of a semiconductor device of the present invention, wherein FIG. 1A is a plan view, FIG. 1B is an equivalent circuit diagram, and FIG.
(F) shows a sectional view of (a).

FIGS. 2A and 2B are diagrams showing a manufacturing process of the semiconductor device of the present invention.

FIG. 3A is a cross-sectional view showing one embodiment of the semiconductor device of the present invention, and FIG. 3B is a cross-sectional view showing another embodiment.

FIG. 4 is a sectional view showing another embodiment of the semiconductor device of the present invention.

FIG. 5 is a sectional view showing a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 source / drain region of first transistor 3 first gate insulating film 4 gate electrode 5 second gate insulating film 6 contact hole 7 polycrystalline silicon film 7a source / drain region of second transistor 8 photoresist 9 Data writing impurity for second transistor 10 Photoresist 11 Data writing impurity for first transistor 12 Interlayer insulating film 13 Metal wiring 14 Protective film 15 Third gate insulating film 16 Second gate electrode

Claims (3)

(57) [Claims] 1. A semiconductor device in which a memory cell of a MOS mask ROM is composed of a transistor, and a multi-level output level is obtained by making the driving capability of the transistor different, wherein the memory cell is provided on a surface layer of a semiconductor substrate. In a semiconductor device comprising a parallel circuit of a first transistor having a channel region and a second transistor formed of a thin film transistor formed on the first transistor and sharing a gate electrode with the first transistor , a semiconductor substrate is provided. A source region of the first transistor on a surface layer;
Alternatively, a plurality of first wirings serving as drain regions are juxtaposed,
On the first wiring, a first gate insulating film is interposed between the first wirings.
A plurality of gate electrodes are arranged crossing the first wiring, and the gate
A second gate insulating film on a side of the gate electrode opposite to the first wiring;
Intersects the gate electrode with a
Multiple source or drain regions
Two wirings are arranged side by side, and the channel of the first transistor is
The upper part of the first region is formed between the second wirings.
Specially, it is a channel region of two transistors.
Semiconductor device. 2. The method according to claim 1, wherein the second transistor has a source
On the side opposite to the gate electrode with the drain region interposed,
Two gate electrodes, and a first gate electrode and a second gate electrode.
Double gate structure where the electrodes are electrically connected
Wherein the is, the semiconductor device according to claim 1. 3. A method for manufacturing a semiconductor device according to claim 1.
A is, on the first transistor, it from a thin film transistor
The second transistor is in parallel with the first transistor.
Forming a column-connected semiconductor substrate; and forming a channel of the first transistor on the semiconductor substrate.
Implanting impurity ions at high energy into the
Low impurity ions in the channel region of the second transistor
Inject with energy and write data to each transistor
And manufacturing the semiconductor device.
Construction method.