JP2853738B2 - Clock phase control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock phase control circuit, and more particularly to a clock phase control circuit for a computer device.

[0002]

2. Description of the Related Art Conventionally, as a clock phase control circuit of this kind, there is, for example, an "clock skew automatic adjustment circuit" disclosed in Japanese Patent Application Laid-Open No. 5-100768. In this clock phase control circuit, a phase comparison between a reference clock as a phase reference and an output clock is performed, and a counter increases or decreases the value according to the result to increase or decrease the delay amount of the delay circuit. If the phase control is constantly performed during the operation of the system or the like, the fluctuation of the clock edge (hereinafter, referred to as jitter) caused by the noise of the power supply becomes large. Therefore, in the conventional clock phase control circuit,
In order to prevent an increase in jitter, an input terminal for a hold signal for holding the value of the counter is provided, and the counter is controlled by operating or holding as necessary.

FIG. 5 is a circuit block diagram showing an example of a conventional clock phase control circuit. The main part of the clock phase control circuit includes a phase comparison circuit 11, a counter 13, and a delay circuit 14.

[0006] The phase comparison circuit 11 outputs an output clock COU.
T is compared with the phase of the reference clock REF, and when the phase of the output clock COUT is ahead of the phase of the reference clock REF, the count-up instruction signal u is output as 1 and the count-down instruction signal d is output as 0, When the phase of the output clock COUT is after the phase of the reference clock REF, the count-up instruction signal u is output as 0 and the count-down instruction signal d is output as 1.

When the hold signal HOLD supplied from the input terminal is 0, the counter 13
Counts up when the count-up instructing signal u output is 1 and the count-down instructing signal d is 0, counts down when the count-up instructing signal u is 0 and the count-down instructing signal d is 1, and is supplied from the input terminal. When the hold signal HOLD is 1, the value is held.

The delay circuit 14 increases or decreases the delay amount of the input clock CIN in accordance with the value of the counter 13, and adjusts the phase of the output clock COUT back and forth.

Next, the operation of such a conventional clock phase control circuit will be described.

When 0 is supplied to the input terminal of the hold signal HOLD when the noise of the power supply is small when the system is stopped or the like, the phase comparison circuit 11 changes the phase of the output clock COUT to the phase of the reference clock REF during that time. And the count-up instruction signal u is output as 1 and the count-down instruction signal d is output as 0.
When the phase of OUT is behind the phase of the reference clock REF, the count-up instruction signal u is output as 0 and the count-down instruction signal d is output as 1.

The counter 13 counts up when the count-up instruction signal u output from the phase comparison circuit 11 is 1 and the count-down instruction signal d is 0, and the count-up instruction signal u is 0 and the count-down instruction signal d is 1
Count down when.

The delay circuit 14 increases or decreases the amount of delay according to the value of the counter 13, and brings the phase of the output clock COUT closer to the phase of the reference clock REF.

Next, when the clock phase control is performed for a certain period, 1 is supplied to the input terminal of the hold signal HOLD,
The value of the counter 13 is held, and the delay amount of the delay circuit 14 is fixed.

[0012]

The first problem in the above-mentioned prior art is that it requires time and effort to generate and supply a hold signal externally by manual operation or the like. The reason is that it does not have a function of automatically generating a hold signal.

A second problem is that when a system is configured, hardware for externally supplying a hold signal to each clock phase control circuit is required. The reason is that each clock phase control circuit does not have a function of generating a hold signal.

A first object of the present invention is to automatically generate a hold signal for holding the value of a counter in a clock phase control circuit, thereby eliminating the trouble of manually generating and supplying a hold signal externally by a manual operation or the like. It is to provide a phase control circuit.

A second object of the present invention is to provide a function for generating a hold signal in each clock phase control circuit so that the hold signal is supplied to each clock phase control circuit even when a system is configured. To provide a clock phase control circuit that does not require hardware for the clock phase control.

[0016]

[0017]

Means for Solving the Problems] clock phase control circuit of the present invention compares the phase of the output clock and the reference clock after the phase adjustment, when the phase of the output clock is in front with respect to the phase of the reference clock , The count-up instruction signal is output as 1 and the count-down instruction signal is output as 0. If the phase of the output clock is after the phase of the reference clock, the count-up instruction signal is output as 0 and the count-down instruction signal is output as 1. Receives a phase comparison circuit, a count-up instruction signal, a count-down instruction signal, and a reset signal output from the phase comparison circuit, and takes in 1 when the count-up instruction signal changes from 0 to 1 when the reset signal is 1. A first flip-flop that resets the value to 0 when the reset signal is 0; When the countdown instruction signal changes from 0 to 1, the second flip-flop resets the value to 0 when the reset signal is 0, and outputs of the first flip-flop and the second flip-flop. the consists of a logical product circuit for ANDing a counter optimum value detecting circuit which both count-up instruction signal and count-down instruction signal and outputs a 1 as a hold signal when changed from at least one 0 to 1, the counter optimum The hold signal output from the value detection circuit is received. When the hold signal is 0, the count-up instruction signal output from the phase comparison circuit is 1, and when the count-down instruction signal is 0, the count-up is performed. Counts down when the countdown instruction signal is 0, and the hold signal There has a counter for holding the value when one performs an increase or decrease in the delay amount of the input clock according to the value of this counter, a delay circuit for adjusting the phase of the output clock before and after.

Further, the clock phase control circuit of the present invention compares the phase of the output clock after the phase adjustment and the phase of the reference clock, and, if the phase of the output clock is ahead of the phase of the reference clock, the first A phase comparison circuit that outputs a count-up instruction signal as 1 and outputs a first count-up instruction signal as 0 when the phase of the output clock is after the phase of the reference clock; Upon receiving the first count-up instruction signal and the reset signal output from the comparison circuit, receiving the first count-up instruction signal output from the phase comparison circuit at the rise of the reference clock, and receiving the second count-up instruction signal And a second clock output from the first flip-flop at the rise of the reference clock. A second flip-flop for receiving a start-up instruction signal and outputting a third count-up instruction signal, and a count-up instruction signal output from the phase comparison circuit and a count-up instruction signal output from the first flip-flop. A first exclusive OR circuit that performs an exclusive OR operation and outputs a first exclusive OR signal;
A second count-up instruction signal output from the second flip-flop and a third count-up instruction signal output from the second flip-flop to perform an exclusive OR operation to output a second exclusive OR signal An exclusive OR circuit;
First exclusive OR signal and said second second exclusive OR signal ANDed to output a logical product signal by ANDing the output of the exclusive OR circuit which outputs the exclusive-OR circuit When the AND signal output from the AND circuit changes from 0 to 1 when the reset signal is 1, it takes in 1 and outputs it as a hold signal, and resets the value to 0 when the reset signal is 0 A counter optimum value detecting circuit for detecting that the first count-up instruction signal has changed from 1 → 0 → 1 or 0 → 1 → 0, and outputting 1 as a hold signal. When the hold signal output from the counter optimum value detection circuit is input, the count-up instruction signal output from the phase comparison circuit is 1 when the hold signal is 0, and when the count-down instruction signal is 0 when the hold signal is 0. A counter that counts up, counts down when the count-up instruction signal is 0, counts down when the count-down instruction signal is 1, and holds a value when the hold signal is 1, and increases or decreases the amount of delay of the input clock according to the value of the counter. And a delay circuit for adjusting the phase of the output clock back and forth.

[0019]

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the clock phase control circuit according to the first embodiment of the present invention.
The main part of the clock phase control circuit according to the present embodiment includes a phase comparison circuit 11, a counter optimum value detection circuit 12, a counter 13, and a delay circuit 14.

The phase comparison circuit 11 compares the phase of the output clock COUT after the phase adjustment and the phase of the reference clock REF, and determines that the phase of the output clock COUT is the reference clock REF.
, The count-up instruction signal u is output as 1 and the count-down instruction signal d is output as 0, and the phase of the output clock COUT is changed to the reference clock REF.
If the phase is after, the count-up instruction signal u is output as 0, and the count-down instruction signal d is output as 1.

The counter optimum value detection circuit 12 receives the count-up instruction signal u, the count-down instruction signal d, and the reset signal RESET output from the phase comparison circuit 11, and receives the count-up instruction signal when the reset signal RESET is 1. when u is changed from 0 to 1 captures 1, the flip-flop H ₁₁ to the reset signal rESET is 0 resets the value to 0, the reset signal RES
When ET is 1, the countdown instruction signal d changes from 0 to 1
, A flip-flop H that takes in 1 and resets the value to 0 when the reset signal RESET is 0
_12, becomes the output of the flip-flop H ₁₁ and H ₁₂ from the AND circuit A ₁₁ Metropolitan to logical <br/>, change the count up instruction signal u and the countdown indication both signal d at least once 0 to 1 1 when the hold signal HO
Output as LD. Reference numeral I ₁₁ denotes an inverter.

The counter 13 receives the input of the hold signal HOLD output from the counter optimum value detection circuit 12, and when the hold signal HOLD is 0, the count-up instruction signal u output from the phase comparison circuit 11 is 1, and the count-down instruction signal d Is 0, the count-up instruction signal u is 0, and the count-down instruction signal d
Counts down when is 1 and the hold signal HOLD
When the value is 1, the value is held.

The delay circuit 14 increases or decreases the amount of delay of the input clock CIN in accordance with the value of the counter 13, and adjusts the phase of the output clock COUT back and forth.

FIG. 2 is a time chart showing the operation of the clock phase control circuit according to the first embodiment shown in FIG.

Next, the operation of the clock phase control circuit according to the first embodiment thus configured will be described with reference to FIG.
This will be described in detail with reference to FIG.

The waveform 2-1 is input to the input clock CIN and the waveform 2-3 is input to the reference clock REF. At this time, the rising edge R ₀ of the reference clock REF (waveform 2-3)
The rising edge of output clock COUT
_{If it} is located at the position of ₀ (waveform 2-2), the phase comparison circuit 11 changes the count-up instruction signal u to 1 (waveform 2-2).
4) The countdown instruction signal d is output as 0 (waveform 2-5).

In this state, the reset signal RESET causes the flip-flop H in the counter
Once you reset the ₁₁ and H _12, counter 13 1
The stage counts up, and the delay circuit 14 increases the delay amount by one stage. Thus, the phase relationship between the output clock COUT and the reference clock REF, C ₁ waveform 2-2 and waveform 2
Although the third relationship of R _1, since the phase of the output clock COUT does not change state in front with respect to the phase of the reference clock REF, the phase comparator circuit 11 continues 1 count up instruction signal u, count down instruction signal d is output as 0, the counter 13 counts up one stage, and the delay circuit 14 increases the delay amount by one stage.

By repeating this series of operations, when the output clock COUT is C _{4 of} the waveform 2-2 and the reference clock REF is R ₄ of the waveform 2-3, the phase of the output clock COUT is different from the phase of the reference clock REF. Therefore, the phase comparison circuit 11 outputs the count-up instruction signal u as 0 and the count-down instruction signal d as 1. At this time,
Since countdown indication signal d as shown in a waveform 2-5 is changed from 0 to 1, the flip-flop H ₁₂ counter optimum value detecting circuit 12 is set to 1 as shown in a waveform 2-7,
Since flip-flop H ₁₁ remains 0 as shown in a waveform 2-6, the hold signal H which is the output of the AND circuit A ₁₁
OLD remains at 0 as shown in waveform 2-8.

[0030] Thus, the counter 13 counts down one step, a delay circuit 14 is decremented by one step the delay amount, the output clock COUT and the reference clock REF and the R of C ₅ and waveform 2-3 phase relationship waveforms 2-2 _Since the phase of the output clock COUT is again earlier than the phase of the reference clock REF as in ₅ , the phase comparison circuit 11 outputs the count-up instruction signal u as 1 and the count-down instruction signal d as 0. At this time, since the count-up instruction signal u as waveform 2-4 is changed from 0 to 1, the flip-flop H ₁₁ counter optimum value detecting circuit 12 is waveform 2-
Becomes 1 as 6, the value of the flip-flop H ₁₂ is originally 1, the hold signal HOLD, which is the output of the AND circuit A ₁₁ is changed to 1 as waveform 2-8. Therefore, the counter 13 holds the value and the delay circuit 14
Is fixed.

[0031] When 0 is entered as the reset signal RESET, the value of the flip-flops H ₁₁ and H ₁₂ are reset together 0, since the hold signal HOLD, which is the output of the AND circuit A ₁₁ is 0, the clock phase The control circuit starts the phase control of the output clock COUT again.

FIG. 3 is a block diagram showing a configuration of a clock phase control circuit according to a second embodiment of the present invention.
The clock phase control circuit according to the present embodiment replaces the counter optimum value detection circuit 12 in the clock phase control circuit according to the first embodiment shown in FIG. 1 with a counter optimum value detection circuit 12 '. It was done. Therefore, the phase comparison circuit 11, the counter 13, and the delay circuit 14 are configured and operate in the same manner as in the clock phase control circuit according to the first embodiment.
The same reference numerals are given and their detailed description is omitted.

The counter optimum value detection circuit 12 'receives the reference clock REF, the count-up instruction signal u output from the phase comparison circuit 11 and the reset signal RESET, and outputs the output of the phase comparison circuit 11 at the rise of the reference clock REF. flip and flop F _31, the count-up instruction signal captures the count-up instruction signal u ₁ output from the flip-flop F ₃₁ at the rising edge of the reference clock REF to output a count up instruction signal u ₁ takes in the count-up instruction signal u to a flip-flop F ₃₂ for outputting u _2, exclusive signals by exclusive OR a count up instruction signal u ₁ output from the count-up instruction signal u and the flip-flop F ₃₁ for outputting the phase comparison circuit 11 e an exclusive OR circuit E ₃₁ for outputting a _1, output of the flip-flop F ₃₁ Count up instruction signal u to
₁ and Increment instruction signal u ₂ and the exclusive OR circuit E ₃₂ for outputting an exclusive and exclusive logical sum e ₂ of the output of the flip-flop F _32, exclusive of the output of the exclusive OR circuit E ₃₁ a logical product circuit a ₃₁ outputs a logical product signal h and the exclusive OR signal e ₂ by the logical product of the output of the sum signal e ₁ exclusive OR circuit E _32, logical product when the reset signal rESET is 1 The AND signal h output from the circuit A ₃₁ is 0
When the signal changes from “1” to “1”, the value of “1” is captured and
Output as OLD, becomes a value when the reset RESET is 0 from the flip-flop H ₃₁ Metropolitan to 0 resets,
When the count-up instruction signal u is 1 → 0 → 1 or 0 → 1 →
Upon detecting the change to 0, 1 is output as the hold signal HOLD. Reference numeral I ₃₁ denotes an inverter.

FIG. 4 is a time chart showing the operation of the clock phase control circuit according to the second embodiment shown in FIG.

[0035] In the clock phase control circuit according to the second embodiment, the counter optimum value detecting circuit 12 ', the count-up instruction signal u to the output of the phase comparator circuit 11 at the rising flip-flop F ₃₁ is the reference clock REF
Captures and outputs a count-up instruction signal u _1, and outputs a count-up instruction signal u ₂ takes in the count-up instruction signal u ₁ output from the flip-flop F ₃₁ on the rising flip-flop F ₃₂ is the reference clock REF. Exclusive OR circuit E ₃₁ the count-up instruction signal u and the flip-flop F ₃₁ for outputting the phase comparison circuit 11
Is exclusive-ORed with the count-up instruction signal u ₁ output from the circuit E1 to output an exclusive-OR signal e ₁ , and the exclusive-OR circuit E
₃₂ outputs an exclusive OR signal e ₂ a count up instruction signal u ₂ outputs the count-up instruction signal u ₁ and flip-flop F ₃₂ to the output of the flip-flop F ₃₁ and exclusive OR. The AND circuit A ₃₁ is provided with an exclusive OR signal e ₁ output from the exclusive OR circuit E ₃₁ and the exclusive OR circuit E _31.
32 outputs to the exclusive OR signal e ₂ of ANDing outputs a logical product <br/> signal h. Flip-flop H ₃₁ is reset signal RESET is outputted from the AND circuit A ₃₁ at 1
When the logical product signal h changes from 0 to 1, 1 is fetched and output as the hold signal HOLD. This allows
When the count-up instruction signal u changes from 1 → 0 → 1 or 0 → 1 → 0, the counter optimum value detection circuit 12 ′ detects this and outputs 1 as the hold signal HOLD. In addition, the flip-flop H _31, the reset RESE
When T is 0, the value is reset to 0.

[0036]

Next, an example of the clock phase control circuit according to the first embodiment shown in FIG. 1 will be described.

In the clock phase control circuit of the present embodiment, the counter 13 is a 4-bit counter that counts 16 steps from 0000 to 1111.

The delay circuits 14 have 1600 ps,
It is composed of delay gates of 800 ps, 400 ps and 200 ps, and a selector for selecting either a clock that has passed through each delay gate or a clock that has not passed.
The delay amount of N is adjusted from 0 ps to 3000 ps in increments of 200 ps.

In operation, an input terminal of the input clock CIN (waveform 2-
1) is input, and a reference clock REF (waveform 2-3) having the same cycle and a delay of about 4 ns is input to an input terminal of the reference clock REF. At this time, the value of the 4-bit counter 13 is 0100, and the delay amount of the delay circuit 14 is 80.
If the output clock COUT is 0 ps and the rising edge C _{0 of the} output clock COUT (waveform 2-2) is 650 ps before the rising edge R ₀ of the reference clock REF, the phase comparison circuit 11 outputs the count-up instruction signal u As 1 and the countdown instruction signal d as 0.

[0040] In this state, when the zero value of the flip-flops H ₁₁ and H ₁₂ in the counter optimum value detecting circuit 12 in the temporarily zero reset signal RESET, 4-bit counter 13 counts up one step value 0101, and the delay circuit 14 increases the delay amount by one step (200 ps) to 1000 ps. Thereby, the output clock C
The phase difference between the rising edge R ₁ of OUT rising edge C ₁ and the reference clock REF is becomes 450 ps, the phase of the output clock COUT does not change state in front with respect to the phase of the reference clock signal REF, the phase comparator The circuit 11 continues to output the count-up instruction signal u as 1 and the count-down instruction signal d as 0, and the counter 13 counts up one stage to a value 0110, and the delay circuit 1
4 increases the delay amount by 200 ps to 1200 ps,
The phase difference between the rising edge R ₂ of the rising edge C ₂ and the reference clock REF of the output clock COUT is 250p
s.

By repeating this series of operations, the counter 1
3 is 0111 and the delay amount of the delay circuit 14 is 1400p
s, the rising edge C ₃ of the output clock COUT
Phase difference rising edge of the output clock COUT of the rising edge C ₄ and the reference clock REF when next 50 ps, the delay amount of the delay circuit 14 by the value of the counter 13 is 1000 of 1600ps the edge R ₃ rising edge of the reference clock signal REF and phase difference between R ₄ becomes -150 ps.
Here, for the first time, the phase of the output clock COUT is later than the phase of the reference clock REF, and the phase comparison circuit 11
Outputs a count-up instruction signal u of 0 and a count-down instruction signal d of 1.

[0042] At this time, since the count-down instruction signal d as shown in a waveform 2-5 is changed from 0 to 1, the flip-flop H ₁₂ counter optimum value detecting circuit 12 is waveform 2-
7 incorporate 1 as but since flip-flop H ₁₁ remains 0 as shown in a waveform 2-6, the logical product circuit A ₁₁
The hold signal HOLD, which is the output of, remains at 0 as shown in the waveform 2-8. Thus, the counter 13 becomes a value 0111 counts down one step, a delay circuit 14 1400ps becomes reduced 200ps delay amount, the output clock COUT of the rising edge C ₅ reference clock R
Since prior 50ps rising edge R ₅ of EF, the phase comparator circuit 11 is 1 count up instruction signal u again,
The countdown instruction signal d is output as 0.

[0043] At this time, since the count-up instruction signal u varies from 0 to a waveform 2-4 1, flip-flop H ₁₁ counter optimum value detecting circuit 12 is waveform 2-
Captured, one as 6, the hold signal HOLD, which is the output of the AND circuit A ₁₁ the value of the flip-flop H ₁₂ is originally 1 changes to 1 as waveform 2-8.
Therefore, the counter 13 holds the 4-bit value 0111, and the delay amount of the delay circuit 14 is fixed at 1400 ps.

[0044]

As described above, the first effect of the present invention is that the phase of the output clock and the phase of the reference clock are closer from the result of the phase comparison between the output clock and the reference clock in the clock phase control circuit. Automatically generates a hold signal to hold the value of the counter that increases or decreases the amount of delay in the delay circuit, so there is no need to supply the hold signal from the outside, and the hold signal is generated outside by hand or the like. This eliminates the need for supply.

The second effect is that, since each clock phase control circuit has a function of generating a hold signal, even when a system is configured, it is possible to supply a hold signal to each clock phase control circuit externally. Hardware is not required.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating a configuration of a clock phase control circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation of the clock phase control circuit according to the first embodiment.

FIG. 3 is a circuit block diagram illustrating a configuration of a clock phase control circuit according to a second embodiment of the present invention.

FIG. 4 is a time chart illustrating an operation of the clock phase control circuit according to the second embodiment.

FIG. 5 is a circuit block diagram illustrating an example of a conventional clock phase control circuit.

[Explanation of symbols]

11 the phase comparator circuit 12, 12 'counter optimum value detecting circuit 13 counter 14 delay circuit A _11, A ₃₁ logical product circuits E _31, E ₃₂ exclusive OR circuits F _31, F ₃₂ flip-flop H _11, H ₁₂ flip-flop I ₁₁ , I ₃₁ inverter

Claims (2)

(57) [Claims] The phase of the output clock after the phase adjustment is compared with the phase of the reference clock. If the phase of the output clock is ahead of the phase of the reference clock, the count-up instruction signal is set to 1, and the count-down instruction signal is set to 1 Output as 0,
When the phase of the output clock is later than the phase of the reference clock, a phase comparison circuit that outputs a count-up instruction signal as 0 and a count-down instruction signal as 1, and a count-up instruction signal and a count-down output from the phase comparison circuit. A first flip-flop that receives an instruction signal and a reset signal, captures 1 when the count-up instruction signal changes from 0 to 1 when the reset signal is 1, and resets the value to 0 when the reset signal is 0 A second flip-flop that captures 1 when the countdown instruction signal changes from 0 to 1 when the reset signal is 1, resets the value to 0 when the reset signal is 0, the first flip-flop and the second flip-flop. An AND circuit for performing an AND operation on the output of the second flip-flop, and A counter optimum value detection circuit that outputs 1 as a hold signal when both the indication signal and the countdown instruction signal change from 0 to 1 at least once, and a hold signal output from the counter optimum value detection circuit, When the hold signal is 0, the count-up instruction signal output from the phase comparison circuit is 1, and when the count-down instruction signal is 0, the count-up is performed. When the count-up instruction signal is 0 and the count-down instruction signal is 1, the count-down is performed. A clock comprising: a counter for holding a value when a hold signal is 1; and a delay circuit for increasing or decreasing a delay amount of an input clock in accordance with a value of the counter, and adjusting a phase of an output clock forward or backward. Phase control circuit. 2. The phase of the output clock after the phase adjustment is compared with the phase of the reference clock. If the phase of the output clock is ahead of the phase of the reference clock, the first count-up instruction signal is output as 1 When the phase of the output clock is later than the phase of the reference clock, a phase comparison circuit that outputs the first count-up instruction signal as 0, a first count output by the reference clock and the phase comparison circuit A first flip-flop receiving an input of an up instruction signal and a reset signal, receiving a first count up instruction signal output from the phase comparison circuit at the rise of a reference clock, and outputting a second count up instruction signal; Captures the second count-up instruction signal output from the first flip-flop at the rise of the reference clock, and Second outputting a Ntoappu instruction signal
And a count-up instruction signal output from the phase comparison circuit and a count-up instruction signal output from the first flip-flop are subjected to an exclusive OR operation to output a first exclusive OR signal. 1 exclusive-OR circuit, and a second count-up instruction signal output from the first flip-flop and a third count-up instruction signal output from the second flip-flop are exclusive-ORed to form a second
A second exclusive OR circuit that outputs the exclusive OR signal of the first and second exclusive OR signals, and a second exclusive OR signal that is output from the first exclusive OR circuit and a second exclusive OR signal that is output from the second exclusive OR circuit. 2
Change of the exclusive OR signal and AND circuit for outputting a logical product signal by logical, in one logical product signal from 0 to the reset signal output of the logical product <br/> circuit when the 1 And a third flip-flop that resets the value to 0 when the reset signal is 0, and the first count-up instruction signal is 1 →
A counter optimum value detection circuit for detecting that the change has occurred from 0 → 1 or 0 → 1 → 0 and outputting 1 as a hold signal; and receiving a hold signal output from the counter optimum value detection circuit, When the count signal is 0, the count-up instruction signal output from the phase comparison circuit is 1, and when the count-down instruction signal is 0, the count-up is performed. When the count-up instruction signal is 0 and the count-down instruction signal is 1, the count-down is performed. A clock phase control circuit comprising: a counter for holding a value when the value is 1; .