JP2851045B2 - Video digital transmission system and its receiving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a digital video transmission system for digitizing a video signal and transmitting the digitalized video signal through, for example, an optical transmission line, and a receiving apparatus therefor.

(Prior art) Conventionally, in this type of system, for example, a video signal is digitized on a transmission side at a clock frequency (for example, 4f _SC = 14.31818 MHz) synchronized with its color subcarrier frequency f _SC , and this digital video signal is separately digitized. After time-division multiplexing with the multiplexed video / audio signal, the signal is transmitted to a communication line at a transmission speed synchronized with the chrominance subcarrier frequency f _SC (for example, 40 f _SC = 143.1818 Mbps), and the clock frequency reproduced from the received signal on the receiving side And performs inverse conversion of the received digital video signal to reproduce the original video signal and video / audio signal.

(Problems to be Solved by the Invention) However, in such a conventional transmission system, since the transmission speed of the communication line is set to a speed synchronized with the digitized clock frequency of the video signal, a transmission / reception unit such as a modem is required. A special device corresponding to the above transmission speed must be used. For example, a digital tertiary group (transmission speed f ₀ = 32.064 Mbps)
And a general-purpose communication line such as a digital quaternary group (transmission speed f ₀ = 97.728 Mbps) cannot be used.

On the other hand, in order to solve this problem, a method of digitizing a video signal with a clock frequency synchronized with the transmission speed of a general-purpose communication line and transmitting this digital video signal through the general-purpose communication line has been considered. However, in such a system, the video signal cannot be properly digitized, so that there is a problem that the quality of the video signal is degraded, which is not suitable for practical use.

In each of the above methods, the receiving side reproduces the clock from the received signal and performs DA conversion of the digital video signal. Therefore, the converted video signal is affected by the jitter of the communication line, and as a result, the reproduced video is reproduced. The quality was degraded.

The present invention pays attention to this point, and a video digital transmission system that can use a general-purpose digital communication line without deteriorating the quality of the video signal and can improve the quality of the video signal without affecting the jitter of the communication line. It is to provide the receiving device.

[Means for Solving the Problems] According to the present invention, on the transmitting side, a video signal is digitized at a predetermined video clock frequency synchronized with the signal frequency, and the video clock frequency of the digital video signal is changed. The digital video signal is converted into a transmission clock frequency synchronized with the transmission speed of the digital communication line, and a stuff bit for making the phase difference between the video clock and the transmission clock close to zero is added to the converted digital video signal. The stuff bit addition information indicating the addition state of the stuff bit is multiplexed to the digital video signal to which the bit has been added, and the stuff bit additional information is transmitted to the digital communication line. The stuff bit additional information is separated from the multiplexed digital video signal The stuff bits in the digital video signal are removed according to the stuff bit addition information, and a video clock is generated independently of the multiplexed digital video signal arriving from the transmitting side. By writing to the buffer memory in synchronization with the transmission clock reproduced from the video signal and reading out the written digital video signal from the buffer memory in synchronization with the video clock, the clock frequency of the digital video signal is changed from the transmission clock frequency. The phase difference between the write position and the read position on one field is detected during the writing and reading operations of the digital video signal in the buffer memory, and the phase difference is equal to or more than a predetermined amount. 1 fee when approaching The digital video signal before reading is repeatedly read out. On the other hand, when the phase difference is more than a predetermined amount, the digital video signal is controlled so as to skip one field and read out. The signal is converted into an analog video signal by the independently generated video clock, thereby reproducing the video signal.

(Operation) As a result, the video signal is digitized at the clock frequency most suitable for the digitization, and is transmitted on the transmission line according to the transmission speed of the communication line. It is possible to digitally transmit a video signal using the communication line. Also, since the digital-to-analog conversion on the receiving side is performed according to a stable video clock generated independently instead of the clock on the transmission line, the effect of jitter on the communication line is eliminated, thereby improving the quality of reproduced video. Can be.

According to the present invention, on the receiving side, the field synchronization is performed together with the conversion of the clock frequency of the digital video signal, so that the frequency difference between the transmission clock and the video clock is appropriately absorbed in units of fields to achieve optimal video reproduction. Can be realized. Further, since the conversion of the clock frequency of the digital video signal and the field synchronization are performed using a common buffer memory, the conversion of the clock frequency and the field synchronization are performed by separate circuits. Therefore, there is an advantage that it can be realized with a simple circuit configuration.

(Embodiment) FIG. 1 shows a configuration of a video transmission system to which a video digital transmission system according to an embodiment of the present invention is applied.
In the figure, reference numeral 1 denotes a transmitting device, and 3 denotes a receiving device connected to the transmitting device 1 via a communication line 2 such as an optical transmission line.

The transmitting device 1 includes an analog / digital converter (A / D) 11
And a video clock generator 12 for generating a video clock frequency 4f _SC four times the color subcarrier frequency f _SC of the video signal VIN. Then, a video signal VIN output from, for example, an imaging device or a video playback device (not shown) is
In step 1, digitization is performed in accordance with the video clock 4f _SC . The transmitting device 1 includes a buffer memory 13, and a transmission clock generator 14 for generating a transmission clock f ₁ in synchronism with the transmission rate of the digital communication line 2. Buffer memory 13, after writing the digital video signal outputted from the A / D11 in synchronism with the video clock 4f _SC, in which read in synchronism with the transmission clock f _1, thereby the digital video signal Is performing asynchronous conversion. The buffer memory 13 has a stuff bit insertion portion, thereby added stuff bits corresponding to the phase difference between the digital video signal described above asynchronous conversion and the video clock 4f _SC and the transmission clock f _1. Further transmitter 1 includes a frame generator 15 for generating a frame signal based on the transmission clock f _1, multiplexer and (MUX) 16. The multiplexing unit 16 includes a digital video signal to which stuff bits have been added, output from the buffer memory 13, information indicating whether or not stuff bits have been added, also output from the buffer memory 13, and a separately digitized video signal. The audio signal DIN is time-division multiplexed in accordance with the frame signal, and the multiplexed video information is transmitted to the digital communication line 2.

On the other hand, the receiving device 3 includes a frame detecting unit 31 for detecting a frame from the multiplexed video information arriving from the transmitting device 1 via the digital communication line 2, and a separating unit (DMUX) 32. 32 separates the multiplexed video information into a digital video signal, information indicating whether a stuff bit is added, and a digitized video / audio signal.
The receiving device 3 includes an AND gate 33 for removing stuff bits, a buffer memory 34, a video clock generator 35 for generating a video clock 4f _SC , and a digital / analog converter (D / A) 36. I have. Of which AND gate 33
Becomes a gate closed state during a period in which information indicating the presence or absence of a stuff bits separated by the separating portion 32 is outputted, prohibiting the passage of the transmission clock f ₁ output from the frame detector 31 in the period Things. The buffer memory 34 converts the digital video signal output from the separation unit 32 into a transmission clock f ₁ supplied from the AND gate 33.
After written in synchronism with, but reading in synchronism with the video clock f ₁ generated from the video clock generator 35,
Thus, stuff bits are removed and digital video signals are field-synchronized. D / A36 is
The digital video signal outputted from the buffer memory 34 and converts the analog signal in accordance with said video clock f _1, and supplies this converted reproduced video signal not shown VOUT for example, a monitor device. DOUT is a digital video / audio signal separated by the separation unit 32.

With such a configuration, the video signal VIN output from an imaging device or the like (not shown) is first digitized by the A / D 11 by the video clock 4f _SC whose frequency is four times the color subcarrier frequency. Is converted into a signal synchronized with the transmission speed of the digital communication line 2. Then, it is time-division multiplexed with the information indicating the presence or absence of the stuff bit and the digital video / audio signal by the multiplexing unit 16 and then transmitted to the digital communication line 2 as multiplexed video information.
That is, the digital video signal is digitized at an optimum clock frequency, and furthermore, a general-purpose digital communication line 2
Will be transmitted at the transmission speed.

On the other hand, in the receiving device 3, when multiplexed video information arrives from the transmitting device 1 via the digital communication line 2,
This multiplexed video information is converted into a digital video signal by the separation unit 32,
It is separated into information indicating whether a stuff bit is added or not and a digital video / audio signal. The digital video signal of which is written into the buffer memory 34 in synchronism with the reproduced transmission clock f ₁ output through the AND gate 33. In this case the AND gate 33 becomes a gate closed state during a period in which information from the separation unit 32 represent there stuff bits are output, thereby to prohibit the passage to the transmission clock f _1. For this reason, the writing of the digital video signal to the buffer memory 34 is prohibited during the above period, and the stuff bit is thereby removed.

On the other hand, the digital video signal written in the buffer memory 34 is read out in synchronization with the video clock 4f _SC generated from the video clock generator 35. That is, thereby, the digital video signal is converted from the transmission clock frequency to the video clock frequency, and the field synchronization is performed. For example, a field phase difference detected based on each count value of a write clock and a read clock, that is, an arbitrary field of a digital video signal is written to a buffer memory, and a write when reading the written field in parallel is performed. When the difference between the address and the read address approaches by a certain amount or more, the digital video signal one field before is repeatedly output, and when the difference is more than a certain amount, the digital video signal is skipped by one field. Output. The digital video signal output from the buffer memory 34 is converted into an analog signal by the video clock 4f _SC at the D / A 36, and is output as a reproduced video signal VOUT.

If this way an embodiment, the transmitting apparatus 1, the digital communication line 2 by adding a stuff bit and converts the buffer memory 13 After digitizing the video signal by the video clock 4f _SC to the transmission clock f ₁ After transmitting and removing the stuff bit from the received digital video signal in the receiving device 3, conversion from the transmission clock to the video clock and field synchronization are performed in the buffer memory 34, and then the analog signal is converted into the analog signal in the D / A 36. Since the video signal is returned and output, the video signal can be digitized at the optimum clock frequency and transmitted at the transmission speed of the general-purpose digital communication line 2. Therefore, video digital transmission can be performed using a general-purpose and inexpensive system without deteriorating the quality of the video signal. Further, since the receiving apparatus 3 is provided with the video clock generator 35, and the clock frequency conversion and D / A are performed by the video clock generated from the video clock generator 35, the effect of the jitter on the transmission line is eliminated, and the high quality reproduced video is eliminated. A signal can be obtained. Further, according to the present embodiment, the conversion of the clock frequency of the digital video signal and the field synchronization are performed by the single buffer memory 34 in the receiving device 3, so that the circuit configuration can be simplified.

The present invention is not limited to the above embodiment,
For example, the value of video clock frequency or transmission clock frequency,
Configuration of clock frequency conversion means on the transmission side and reception side,
The configuration and the like of the circuit for adding and removing stuff bits can be variously modified and implemented without departing from the gist of the present invention.

[Effects of the Invention] As described above in detail, according to the present invention, on the transmission side, a video signal is digitized at a predetermined video clock frequency synchronized with the signal frequency, and the video clock frequency of the digital video signal is digitally communicated. In addition to converting to a transmission clock frequency synchronized with the transmission speed of the line, a stuff bit for making the phase difference between the video clock and the transmission clock close to zero is added to the converted digital video signal. The stuff bit additional information indicating the stuff bit addition state is multiplexed with the added digital video signal and transmitted to the digital communication line. On the other hand, on the receiving side, the multiplex signal received from the transmitting side via the digital communication line is transmitted. The stuff bit additional information is separated from the digitized digital video signal, In addition to removing stuff bits in the digital video signal according to the additional bit information, a video clock is generated independently of the multiplexed digital video signal arriving from the transmitting side, and the digital video signal after the stuff bit removal is multiplexed into a multiplexed digital video signal. By writing the digital video signal into the buffer memory in synchronization with the transmission clock reproduced from the signal and reading out the written digital video signal from the buffer memory in synchronization with the video clock, the clock frequency of the digital video signal is changed from the transmission clock frequency to the video clock. A clock frequency is converted, and a phase difference between a write position on one field and a read position on one field is detected during the writing and reading operations of the digital video signal in the buffer memory. One field before The digital video signal is repeatedly read, and if the phase difference is separated by a certain amount or more, the digital video signal is controlled so as to be skipped by one field and read out. Further, the digital video signal read out from the buffer memory is By converting the independently generated video clock into an analog video signal and thereby reproducing the video signal, a general-purpose digital communication line can be used without deteriorating the quality of the video signal, and the communication line It is possible to provide a video digital transmission system capable of improving the quality of a video signal by eliminating the influence of the jitter of the video signal and a receiver thereof.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of a video digital transmission system to which a video digital transmission system according to an embodiment of the present invention is applied. 1 ... transmitting device, 2 ... digital communication line, 3 ... receiving device, 11 ... analog-to-digital converter (A / D), 12, 35
…… Video clock generator, 13,34 …… Buffer memory, 1
4 ... Transmission clock generator, 15 ... Frame generator, 16
...... Multiplexer (MUX), 31 ... Frame detector, 32 ...
Separator (DMUX), 33 ... AND gate, 36 ... Digital / analog converter (D / A).

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 7/00-7/088 H04N 7/10 H04J 3/07

Claims (2)

(57) [Claims] 1. A video digital transmission system for digitizing a video signal and transmitting the digitized video signal via a communication line having a predetermined transmission rate, the transmission side transmits the video signal at a predetermined video clock frequency synchronized with the signal frequency. Analog-to-digital conversion means for converting a digital video signal output from the analog-to-digital conversion means into a transmission clock frequency synchronized with the transmission speed of the digital communication line; Transmission clock frequency conversion means for adding a stuff bit for making the phase difference between the video clock and the transmission clock close to zero to the video signal; and adding the stuff bit to the digital video signal output from the transmission clock frequency conversion means. The stuff bit additional information indicating the status is multiplexed to Multiplexing means for transmitting the stuff bit additional information from the multiplexed digital video signal arriving from the transmission side via the digital communication line; and A video clock generating means for generating a video clock independently of the multiplexed digital video signal; and a stuff bit according to the stuff bit additional information from the digital video signal after the stuff bit additional information is separated by the separating means. Means for removing the stuff bit by the stuff bit removing means and writing the digital video signal into the buffer memory in synchronization with the transmission clock reproduced from the multiplexed digital video signal, and A signal is generated from the video clock generating means. Receiving clock frequency conversion means for converting the clock frequency of the digital video signal from the transmission clock frequency to the video clock frequency by reading from the buffer memory in synchronization with the received video clock, and writing and reading the digital video signal in the buffer memory During operation, a phase difference between a write position on one field and a read position thereof is detected, and when the phase difference approaches by a certain amount or more, the digital video signal of one field before is repeatedly read, while the phase difference is a certain amount. A field synchronization means for controlling the digital video signal so as to skip one field when it is separated, and a video clock generated by the video clock generation means for transmitting the digital video signal read from the buffer memory To analog video signal Digital video transmission system, characterized in that a digital-to-analog conversion means. 2. A transmitting apparatus, wherein a video signal is digitized at a predetermined video clock frequency synchronized with the signal frequency, and the video clock frequency of the digital video signal is converted into a transmission clock frequency synchronized with a transmission speed of a digital communication line. The stuff bit for bringing the phase difference between the video clock and the transmission clock close to zero and stuff bit additional information indicating the additional state of the stuff bit are multiplexed with the digital video signal after the speed conversion. The receiving apparatus used in a system for transmitting the multiplexed digital video signal to a receiving apparatus via a digital communication line, wherein a stuff bit is added from the multiplexed digital video signal arriving from the transmitting apparatus via the digital communication line. Demultiplexing means for demultiplexing information; and multiplexing coming from the transmitting device. A video clock generating means for generating a received video clock independently of the digital video signal; and removing a stuff bit from the digital video signal after the stuff bit additional information is separated by the separating means in accordance with the stuff bit additional information. A stuff bit removing means for writing the digital video signal after the stuff bit removal by the stuff bit removing means into a buffer memory in synchronization with a transmission clock reproduced from the multiplexed digital video signal, and A reception clock frequency conversion unit that converts a clock frequency of the digital video signal from a transmission clock frequency to a video clock frequency by reading from a buffer memory in synchronization with a video clock frequency generated by the video clock generation unit; During the writing and reading operation of the digital video signal in the memory, the phase difference between the writing position on one field and the reading position is detected, and when this phase difference approaches by a certain amount or more, the digital video signal of the previous field is detected. Field synchronization means for controlling so that the digital video signal is skipped by one field when the phase difference is separated by a certain amount or more, and the digital video signal read from the buffer memory, A digital-to-analog converter for converting an analog video signal into an analog video signal by a video clock generated from the video clock generator.