JP2847316B2 - Processor - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to an instruction decoding device used in a microprocessor.

[Background of the Invention]

Microprocessors and other computers use macros
Often, a decoder must be used to decode the level instructions. In effect, the instructions are translated by a decoder, and the decoder determines what to do in the processor to execute the instructions. Often, a microprocessor includes a memory for storing micro-level instructions (microcode), and a decoder provides the microcode with a look-up function.

In some microprocessors, macro-level instructions are of fixed length (eg, 32 bits), while in other microprocessors, instructions are of different lengths. For example, it is much easier for a decoder to decode fixed length instructions where the location of a given field in the instruction is known. In contrast, for a variable length instruction, for example, there may or may not be a direct data field, and the starting point of the instruction will change.

Intel 386 microprocessor (Intel and 386
Is a registered trademark of Intel Corporation)
Is an example of a microprocessor having a variable length instruction. The instruction width is 1 for some MOVE instructions
Can be bytes, up to 8 bytes (no prefix)
Is possible up to. Further, with an instruction prefix or override, the length of the instruction may be substantially longer (eg, 15 bytes). A single decoder that decodes these variable length instructions in a single pass is relatively complex and consumes relatively large board area.

On the Intel 386, variable-length instructions are decoded over several computer cycles. Instruction prefixes followed by other fields are examined first. Instruction execution begins after decoding is complete. For many instructions, the Intel 386 requires several cycles to decode.
For example, LOAD is 4 for the instruction to be decoded.
STORE requires two cycles, STORE requires two cycles, and JUMP requires three to 4.25 cycles. Before decoding the instruction completely, on average about 3
A cycle is needed. However, as described below, in the present invention, due to the manner in which the instructions are decoded and the pipeline, these times are greatly reduced and the decoding time is reduced to an average of about 1.8 cycles.

The invention is used in microprocessors that have improved versions of the Intel 386 microprocessor. Intel 386 microprocessors have been described in many printed publications. The programming of this microprocessor was described in SYBEX in 1987.
In "Programming the 80386" by Crawford and Gersinga.

[Summary of the Invention]

An improved microprocessor having a storage device for storing prefetched instructions and a decoding device for decoding instructions of different lengths is described.
The improved microprocessor uses a decoding means that includes two stages or sections. The first section decodes the first field of one instruction simultaneously while the second section sets up execution based on the second field of the previous instruction. That is, the first and second sessions pipeline the instruction and operate it in parallel.

In this embodiment, the first section decodes the Op code and the bits representing the address mode, scaling factor and base and index registers. The second section controls the use of address displacement and direct data fields. The first section generates a pointer for the device so that each section can receive the correct fields of the instruction. Each section can receive any bytes from storage.

Other features of the present invention will be apparent from the detailed description of the invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

〔Example〕

A microprocessor instruction decoding apparatus that is particularly useful for prefetched instructions is described. In the following description, many specific details, such as a specific number of bits, are for assisting an understanding of the present invention, and it is understood by those skilled in the art that the present invention is not limited to these detailed descriptions. Will be obvious to you. In addition, detailed descriptions of well-known processing techniques, decoding techniques, and circuits are omitted so as not to obscure the description of the present invention.

The present invention was derived during the design of the next microprocessor after the Intel 286 and 386 family of microprocessors. Therefore, by understanding the Intel 386 microprocessor, the intention of the present invention can be fully recognized. This behavior has been documented in many publications on this microprocessor, as well as in 1987 SYBEX
In "Programming the 80386" by Crawford and Gersinga.

<< Outline of Microprocessor Implementing the Present Invention >> The microprocessor embodying the present invention is a 32-bit microprocessor manufactured by complementary metal oxide semiconductor (CMOS) technology. This means that on a single board, not only the equipment associated with the central processing unit (CPU) but also the cache
It has memory and floating point units. With the improved instruction decoding apparatus of the present invention, single cycle instruction execution can be realized for many instructions.

In FIG. 1, a bus interface device 10 is shown as a main device of the microprocessor. This device provides the necessary interface between the microprocessor's internal buses, such as cache memory 11 and prefetcher 12, and a responsive external bus for fetching data from an external data memory device. An external 32-bit address bus and 32-bit data bus are used. The particular interface device 10 used in the microprocessor shown here is not critical to the present invention. This device is disclosed in Japanese Patent Application No. 227,07, filed August 1, 1988, assigned to the assignee of the present invention.
No. 8 (U.S. Pat. No. 5,073,969) is shown under the title "Microprocessor Bus Interface Device". The prefetched instruction stored in the prefetcher 12 can be transmitted from the bus interface device 10 or the cache memory 11 to the prefetcher.

The pacing device 13 and the segmentation device 15 are almost the same as those used for the Intel 386. However, the timing has been changed to support one clock execution. Another relationship between the interconnection of the segmentation device and the prefetcher 12 and the instruction decoder device 14 is shown in FIG.

The instruction decoding device decodes an input instruction, and differs from the decoding device with an Intel 386 instruction in that decoding and pipelining are performed in parallel as described later. The instruction decoding unit has two stages or sections, producing one decoded instruction per computer clock cycle for most instructions.
The first section basically consists of the Op code and address mode, scaling factor, and base and index register bits (collectively, the register and address mode specifier (spec
), and the second section mainly manages the use of address displacement or direct data fields.

The control device 19 has a memory for storing microcode instructions (microcode) of the microcomputer. This will be described later. Since the first line of microcode is provided by the instruction decoding unit 14, control of the microprocessor is shared with the instruction decoding unit. The controller 19 is responsive to instruction boundary processing, such as interrupt / exception arbitration, or to halting the instruction decoding device 14, as needed. The controller 19 handles most frozen states, such as cache memory misses.

The data path (path) device 17 is a main execution data path of the microprocessor. This includes arithmetic logic units, register files, barrel shifters, constant ROMs, and flags.

The microprocessor further has a floating point unit 18. The device has logic for executing floating point instructions.

<< Description of Embodiment of the Present Invention >> The instruction decoding device 14 shown in FIG.
Shown between 46,47. This device and certain circuits of the prefetcher 12 work together to provide the benefits of the present invention.

The prefetcher 12 has three main sections: a register 26, a multiplexer 27, and associated logic 28. The register or latch 26 is
Receive prefetched instructions from either memory or bus interface devices. This is indicated by bus 48 in FIG. The width of the register 26 is 32 bytes in this embodiment. The instruction stored in register 26 can be sent to either bus 29 (K1Q) or bus 30 (K2Q). These instructions are sent to these buses via multiplexer 27. Any three adjacent (consecutive) bytes in register 26 can be provided on bus 29. Also, any adjacent (consecutive) 4 bytes can be supplied to the bus 30.

The signal on line 44 from code controller 36 is
Provides a pointer (K1P) to the first byte of a 24-bit field that is continuous with 29. “(5)” after “K1P”
It indicates that 5 bits are used to indicate this pointer, which is necessary to indicate a single byte of 32 bytes stored in register 29. A second pointer (K2P) connected to the prefetcher 12 on line 43 points to the first byte of a 32-bit field connected to the bus 30. As described below, the fields connected to buses 29 and 30 may overlap. That is, the first byte connected to bus 29 in one clock cycle can be connected to bus 30 in a subsequent clock cycle.

The five bits connected to the prefetcher 12 on line 41 (K1PJ) provide a jump pointer to the code control circuit 36. This occurs after a new instruction has been loaded into register 26 (after the JUMP command). This pointer indicates to the control circuit 36 the start byte of the new instruction. line
The signal at 42 (K1V and K2V) is
Shows whether 2Q data is valid. Line 40
(Isx8 and izx16) are control signals for directly controlling the connection of the data field.

Decoder 31 is a conventional programmed logic array (PLA) circuit (including logic gates) programmed to perform conventional decoding. As shown below, O
The p-code and registers and address mode specifier are connected from register 26 to decoder 31 (unless it includes an instruction prefix). From this data, the decoder 31 via the code controller 36 determines the length of the field actually required by the decoder 31 and the point at which the pointer on the K2Q bus should point in the register 26. The decoder always receives 24 bits, even if an 8-bit instruction is present in register 26. Decoder 31 performs an execution setup stage that identifies the type of address required to execute the instruction.
Supply signal to 34. As described below, the decoder 31 and the execution set-up stage 34 operate in parallel, but the decoder 31 operates while the stage 34 operates on the previous instruction.
Operate on one instruction.

By means of a latch 35 connected to the output of the decoder 31, the signal obtained from the decoding is clocked via the latch 35 and can be timed with the subsequent "decoding" performed by the stage 34. The latch output includes a special ALU control signal and an enable signal for the source / destination register. The output of the latch includes the entry point (lookup) of the "first" line of microcode in the microcode memory of device 19.

However, in practice, since the decoder 31 supplies the first two lines of microcode with the latch 35, the entry point indicates the third valid line of microcode. For example, this occurs in a store instruction or when the decoder 31 sets up the address calculation in one cycle. In the following clock cycle, a second line of microcode is provided by latch 35 to begin a bus cycle (received from memory). For the next clock cycle, the third line of code is provided by the microcode memory (controller 19 of FIG. 1). The third line of code is latched when latch 35 is supplying the first line of microcode.
Is selected based on the entry point provided by.

All instructions use at least one line of microcode from controller 19. In some cases, this microcode may simply indicate the completion of an instruction cycle. In many cases, the first line of microcode from decoder 31 is "NOOP".

As described above, the execution setup stage 34, which can be viewed as the second stage of decoding,
It mainly controls address generation, that is, sequencing related to address generation. Thus, it is implemented primarily as a state machine. The actual address calculation is
This is performed by the segmentation device 15. Decoder 31
Supplies the linear address requirements to and from stage 34 and determines how many cycles are required for the instruction. In general, one cycle is required if there is only a basis and displacement, and 2 if there is a basis, a scaled index address factor, and a displacement.
Cycle required. The load signal and the field sizing signal are supplied to the segmentation device 15 via the control circuit 36.

Code controller 36 includes a state machine, adders and counters, and associated logic. The signal is supplied from the decoder 31 to the code controller 36 and indicates the type of the decoded instruction. From this information, the code control device 36 uses the adder and the counter to
Determine where P, K2P should indicate. Code control device 3
The control performed by 6 will be apparent from the description of the pointer in FIG.

The code control device 36 also performs other functions in this embodiment. For example, a violation bit indicating a segmentation violation or other violation is detected by the prefetcher 12 and sent to the code controller 36. The code controller 36 also determines the properties of the violation in some examples.

The pipeline control circuit 37 is also a state machine that controls the entire pipeline of the instruction decoding device. This circuit recognizes from the signal sent to it from the decoder 31 that the instruction contains a prefix,
Determine the number of extra cycles required to process a particular instruction. For example, several cycles are required, as described below with respect to FIG. Execution setup stage 34 controls these additional cycles. The pipeline control circuit 37 sends an "advance signal" to the decoder 31 and execution setup stage 34 on line 49,
It provides a "flash pipeline" or reset signal and a signal that indicates when a particular stage has completed an operation on an instruction.

The entire circuit shown in FIG. 2 can be constituted by an ordinary circuit. Control signals which are not so important for understanding the present invention are omitted in FIG. In addition, functions that are less necessary for understanding the present invention (eg, test functions) are not shown to facilitate understanding of the present invention.

<< Instructions Operated by the Device of the Present Invention >> FIG. 3 shows general types of instructions relating to the Intel 386. These are instructions that are decoded in the decoding device of the example of the present invention. The instruction consists of an Op code, possibly another address field 50,
It includes a displacement field 51 and a direct field 52.
The lengths of these fields are different as described in FIG. In some cases, an additional prefix 55 is used.

FIG. 4 shows typical instructions. The Op code field is one or two bytes long. For example, the entire instruction may consist of only one byte where the first five bits indicate MOVE and the last three bits indicate register indication. A typical Op code has two bytes 57,58 in FIG. Address mode byte 59 indicates address mode and "register / memory" and byte 60 is a scale factor for the scaled index addressing mode (SS), a general factor used as an index register (index). Registers, and general registers used as base registers. Bytes 59 and 60 are
Shown as Register and Address Mode Specifier. Field 61 is the address displacement, which may not be present in all instructions, and is otherwise 1, 2 or 4 bytes long.
Similarly, the direct data field 62 may not be present in all instructions, and is otherwise 1, 2 or 4 bytes long. Other changes may also occur. For example, bits may be used in conditional instructions to specify a condition to be asserted or negated when the segment register specifier for a register occurs in the Op code field.

What is important in FIG. 4 is that the first three bytes of all instructions (except those that have a prefix) are:
It contains sufficient information to determine the required instruction and the total length of the instruction. In each case, these three bytes are supplied to the decoder 31. From the remaining bytes of each instruction, the address can be calculated by the segmentation device 15 of FIG. The first three bytes are
It contains the information needed by decoder 31 to determine the number of cycles and address mode needed to calculate the address. For example, if there is a basis, index and displacement, two cycles are usually required.

<< Timing Diagram of FIGS. 5 and 6 >> From FIG. 5, the general pipelining of the apparatus of the present invention can be understood. The cycle is shown at the top of the table. Each cycle corresponds to a computer cycle. For example, microprocessor internal clock cycles occur at a rate of 25 MHz. The left column shows the stages in the pipeline. The numbers in the table indicate the instruction numbers. For example, in cycle 1, instruction 11 is transferred from prefetcher 12. That is, it is supplied to the decoder 31. In the same cycle (ie, at the same time as this transfer), decoder 31 is decoding instruction 10, which is the instruction before instruction 11. Similarly, during this period, the execution setup stage 34 of FIG. 2 controls the sequencing of address calculations for instruction 9. At the same time, execution is performed for instruction 8 and write back
Is performed for instruction 7. (Not all instructions have write-back, but some single-byte instructions require write-back.) As shown in cycle 2, the transfer to decoder 31 Performed on 12, the decoder 31 is decoding the instruction 11, and the execution set-up is operating on the instruction 10.

As described above, the prefix (the prefix 55 in FIG. 3) may exist. In cycle 3, by decoding the first 24 bits of instruction 13, decoding determines that the prefix is present. Assume that This information is supplied to a pipeline control circuit 37, which includes all prefixes,
Determines how many cycles are required to transfer the Op code and register and address mode specifier to decoder 31. This is done in cycles 3, 4, and 5, as shown in FIG. Decoding is performed in cycles 4, 5, and 6, and execution setup is performed in cycle 7. Execution is cycle 8
In this instruction. In cycles 5 and 6, the execution setup stage 34 does not operate, and similarly the execution stage does not operate in cycles 6 and 7.

Instruction 14 is transferred to decoder 31 in cycle 6 and decoded by decoder 31 in cycle 7,
Two cycles 8, 9 are required for address calculation. As mentioned above, this occurs when the address includes a base, index, and displacement. Since two cycles are required, as shown in cycle 8, the decoder 31
Is not transferred, but in cycle 9, the instruction
16 is transferred to the decoder.

FIG. 6 shows a part of the register 26 of FIG.
This register contains several instructions, such as instructions 1-4.
Is stored. Instruction 1 has a 2-byte Op code, a register, and an address mode specifier. ("Op" in FIG. 6 represents the actual Op code and register and address mode specifier fields in FIG. 4.) Instruction 1 has an 8-bit direct field. Instruction 2 is a 16-bit
It has an Op code and a 32-bit direct field. Instruction 3 has only an 8-bit Op code. Instruction 4
Has a 24-bit Op code and a 32-bit displacement field. First, K1 supplied to the prefetcher 12
The P pointer (pointer 67) is
Indicates a byte. Therefore, the first 24 bits of the register are transferred to the decoder 31. This field is a number
Shown at the right of cycle 1 by 68. By decoding this field, the decoder 31
It determines that the bit is an Op code and provides an appropriate signal (typically to latch 35) to begin execution of this code. The code control circuit 26 sets the IK2P pointer 69 to instruction 1
Should indicate the beginning of the direct field in. This pointer allows the 4
The bytes are transferred under the control of the setup stage 34. This field is indicated by bracket 70 on the right side of cycle 2 in FIG. Code control circuit 36
Supplies the pointer 71, so in cycle 2
The 24 bits after the pointer 71 are transferred to the decoder 31. This field is generally designated by the number 72.
The eight bits of the direct field of instruction 2 are transferred to the decoder, but these bits are actually ignored. Since pointer 73 is set at the beginning of this field, in the next cycle all direct fields for instruction 2 will be transferred. (The displacement field is transferred to the segmentation device and the direct field is transferred into the cache device.) The field is shown as cycle 3 at 74. The control circuit 36 supplies a pointer 74,
The 24 bits after the pointer 74 are transferred to the decoder 31 in cycle 3. This instruction has no direct or displacement fields, and no 1K2P pointer for instruction 3 is needed. This is generally indicated as cycle 4 by the number 75. This process continues as shown in FIG. 6, with the control circuit 36 providing a pointer for instruction 4 and the appropriate fields being transferred.

The lower part of FIG. 6 shows the execution of the instruction. In cycle 3, instruction 1 is executed. In cycle 4, instruction 4 is executed, and so on.

As described above, the instruction and decoding apparatus of the present invention improves the characteristics of a microprocessor using variable length instructions.

[Brief description of the drawings]

FIG. 1 is a general block diagram of a microprocessor in which the present invention is used, and FIG. 2 is a block diagram showing an instruction decoding device of the present invention and connections to a prefetcher and a segmentation device. FIG. 3 is a diagram showing the most general format of an instruction decoded by the apparatus of the present invention, and FIG. 4 is a diagram showing the format of the instruction in more detail and showing the variable length field of the instruction. FIG. 5 is a diagram used to illustrate the pipeline flow and timing associated with the present invention, and FIG. 6 is a detailed diagram illustrating the instruction flow and timing associated with the present invention. is there. 10 ... Bus interface device, 11 ... Cache
Memory 12 Prefetcher 13 Paging device 14 Instruction decoder device 15 Segmentation device 17 Data path device 18 Floating point device 19 Control device 26 Register , 27 multiplexer, 31 decoder, 34 execution setup stage, 35 latch, 36 code control circuit, 37 pipeline control circuit.

Continuation of the front page (56) References JP-A-63-113634 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 9/38 G06F 9/32 G06F 9/30

Claims (11)

(57) [Claims] 1. Decoding means for storing a plurality of prefetched instructions, wherein said plurality of instructions have at least two types of lengths, and decoding said plurality of instructions from said storage means. And an execution device that executes the plurality of instructions, wherein each of the plurality of instructions includes a plurality of bytes and has a first field and a second field; The decoding means is provided with at least two sections, a first section of the at least two sections being coupled to receive n bytes from the plurality of instructions, and from the n bytes to the plurality of sections. Decoding the first field of one of the instructions of the first section, wherein the first field is associated with the first section. Providing a first pointer to said storage means for selecting a second field of said one of said plurality of instructions from said storage means; Providing a second pointer to the storage means for selecting a first field of an instruction following the one of the plurality of instructions, wherein the second field comprises the second field for generating an address; Having information used by a section, the first section further comprising means for indicating to the second section a type of address calculation to be performed on the one of the plurality of instructions. The second section receives m-byte instruction data from the storage unit in accordance with an instruction from the first pointer, and receives the second byte from the storage unit. Coupled to perform setup of the one of the plurality of instructions with respect to a field, wherein the second section indicates a type of address calculation to be performed with respect to the one of the plurality of instructions. Controlling the address calculation in response to the section so that the address calculation is sequenced, and wherein the first section is configured to execute the plurality of instructions while the second section performs setup of the one of the plurality of instructions. Decoding the first field of the instruction following the one instruction of the second section, wherein the second section comprises the first section and the second section.
Includes means to synchronize results from sections,
Wherein the one of the plurality of instructions is decoded and provided to the execution unit while the second section is performing address calculation sequencing for the instruction following the one instruction; A microprocessor wherein the first section, the second section, and the execution device operate in synchronization. 2. The microprocessor according to claim 1, wherein said first field includes an Op code, a register and an address mode specifier. 3. The microprocessor of claim 1 wherein said microprocessor uses microcode and includes memory for storing some of said microcode, and said first section provides a lookup function for said microcode. The microprocessor according to claim 1. 4. The microprocessor of claim 3, wherein said first section provides at least one line of microcode for certain of said instructions. 5. The invention of claim 1 wherein said first section provides at least a first line of microcode for some of said instructions and provides a lookup function for other microcode. A microprocessor as described in section. 6. An instruction decoding device, comprising: a register for storing a plurality of instructions supplied to the instruction decoding device; and an execution device for executing the plurality of instructions each having a plurality of bytes. A microprocessor operable with instructions of a predetermined length, the instruction decoding device having first and second stages, the first stage receiving a plurality of instruction bytes during a first computer cycle. Decodes an Op code, a register, and an address mode specifier (first field) of one of the plurality of instructions to the second instruction; and decodes the Op code of the plurality of instructions to the second stage. By notifying the address displacement or the direct data field of one instruction, the Op code and the record of the instruction following the one of the plurality of instructions are notified. Star and address
Determining a position of a mode specifier (first field), wherein data in an address displacement field or a direct data field of the one of the plurality of instructions is received directly from the register by the second stage; And wherein the first stage indicates to the second stage a type of address calculation to be performed on the one of the plurality of instructions, and wherein the second stage is of the plurality of instructions. Controlling the use of the address displacement field or the direct data field (the second field) of the one instruction, wherein the plurality of instructions are performed during a second computer cycle that is temporally subsequent to the first computer cycle. Said one of the
Responsive to the first stage indicating the type of address calculation to be performed on the one instruction, the first stage may include an Op code, a register, and an address mode specification of an instruction following the one of the plurality of instructions. The address calculation is sequenced while decoding the fire, the instruction decoding device having means for synchronizing the results from the first and second stages, wherein the one of the plurality of instructions is Wherein the one of the plurality of instructions is decoded and provided to the execution unit while the second stage is performing address calculation sequencing for the instruction following the instruction;
A microprocessor wherein the first stage, the second stage, and the execution device are operated in synchronization. 7. The first stage is coupled to receive the first field under a first pointer, and the second stage uses the second field under a second pointer. 7. The processor according to claim 6, wherein the first and second pointers are generated by a signal from the first stage. 8. The processor according to claim 7, wherein said first stage activates execution of a certain instruction of said plurality of instructions. 9. The microprocessor of claim 1, wherein said microprocessor uses microcode and includes memory for storing at least some of said microcode, and said first stage provides a look-up for said microcode through a latch. A microprocessor according to claim 6, wherein said microprocessor is a microprocessor. 10. The microprocessor according to claim 9, wherein said first stage provides two lines of microcode for a certain instruction of said plurality of instructions. 11. The microprocessor according to claim 10, wherein said first stage controls activation of a bus cycle.