JP2842770B2 - Semiconductor integrated circuit and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (Dynamic Random Access Memory) having both a capacitor for holding information and a capacitor for removing power supply noise.
ry).

[0002]

2. Description of the Related Art Conventionally, as a capacitor formed in a semiconductor integrated circuit, a capacitor having a MOS structure in which an SiO ₂ film is interposed between a substrate and an electrode made of polysilicon has been known. In this MOS structure capacitor, an SiO ₂ film is formed on the surface of a Si substrate as a lower electrode by subjecting the substrate to a thermal oxidation treatment, and a conductive layer such as polysilicon as an upper electrode is laminated on the SiO ₂ film. It can be obtained by:

[0003] This type of capacitor is a DRAM.
And the like, it is used as a memory cell capacitor for holding a voltage corresponding to information to be stored.

[0004]

By the way, in a semiconductor integrated circuit, noise is generated between a power supply and a ground as a transistor or the like in the semiconductor integrated circuit performs a switching operation. Particularly, in a DRAM or the like, this noise is absorbed. Requires a power supply bypass capacitor. If the polysilicon layer as the upper electrode is connected to the power supply Vcc and the Si substrate as the lower electrode is connected to the ground Vss, the MO
A power supply bypass capacitor can be formed by the capacitor having the S structure.

However, in the above-mentioned MOS-structured capacitor, since the Si substrate as the lower electrode is an inversion layer of the MOS transistor, the sheet resistance is generally several K.
It is as high as Ω / □. Therefore, this type of capacitor has a problem that since the electrode itself has a relatively high resistance, it cannot sufficiently remove noise when used as a power supply bypass capacitor.

As the dielectric film of a capacitor having a MOS structure, an SiO ₂ film obtained by thermally oxidizing a Si substrate as described above is generally used. _{The two} films usually have defects at a rate of about ² defects / cm ² . Therefore, when a capacitor having a large electrode area is formed to obtain a relatively large capacitance such as a power supply bypass capacitor, or when a large number of capacitors such as a memory cell capacitor of a DRAM are formed on a Si substrate, defects are included. The probability of forming a capacitor becomes extremely high, and there is a problem that the production yield of a semiconductor integrated circuit is reduced by forming a defective capacitor in this manner.

In particular, the power supply bypass capacitor requires a high withstand voltage since the power supply voltage is directly applied thereto. However, a capacitor having a MOS structure used as a memory cell capacitor does not have such a high withstand voltage, and therefore cannot be said to be inappropriate as a power supply bypass capacitor.

Here, by increasing the thickness of the dielectric film interposed between the electrodes, the withstand voltage of the MOS structure capacitor can be increased. However, when a MOS structure capacitor is used as a power supply bypass capacitor, it is necessary to remove steep switching noise, and it is necessary to increase the capacitance. For this purpose, the area of the capacitor electrode must be increased. However, as mentioned above, MOS
Since the insulating film in the structured capacitor has a high defect rate, a large capacity M that can be used as a power supply bypass capacitor is used.
It is difficult to form an OS structure capacitor, and it is not yet practical.

The present invention has been made in view of the above circumstances, and provides a semiconductor integrated circuit having a large capacity, high withstand voltage power supply bypass capacitor and a memory cell capacitor without significantly increasing the number of steps. It is intended to be.

[0010]

The invention according to claim 1 is
An upper electrode for memory and a lower electrode for memory to which a voltage corresponding to information to be stored is applied; an insulating film for memory including a high dielectric film laminated between the upper electrode for memory and the lower electrode for memory; , A bypass capacitor upper electrode and a bypass capacitor lower electrode each connected to one of a power supply and a ground, and a bypass capacitor laminated between the upper electrode and the lower electrode. A power supply bypass capacitor composed of an insulating film and a dielectric film for a bypass capacitor added thereto is formed on the same semiconductor substrate, and the upper electrode for the bypass capacitor and the lower electrode for the bypass capacitor are A conductor containing at least polysilicon, wherein the memory upper electrode and the memory The semiconductor integrated circuit is formed by the same process as that of the lower electrode, and the insulating film for the bypass capacitor and the insulating film for the memory are formed in the same process. . The gist of the invention according to claim 2 is that the memory insulating film and the bypass capacitor insulating film are composite insulating films. The invention according to claim 3 is an electrode comprising a conductor film containing at least polysilicon on a semiconductor substrate on which a memory cell transistor is formed, wherein the memory lower electrode is connected to the memory cell transistor. Forming a lower electrode for a bypass capacitor connected to one of a power supply or a ground, and forming an insulating film including a high dielectric film on the lower electrode for a memory and the lower electrode for a bypass capacitor; Forming a bypass capacitor dielectric film in a region of the insulating film corresponding to the bypass capacitor lower electrode;
An electrode made of a conductor film containing at least polysilicon, wherein the memory upper electrode facing the memory lower electrode with the insulating film interposed therebetween, and the memory upper electrode with the insulating film and the dielectric film for the bypass capacitor interposed therebetween. Forming a bypass capacitor upper electrode that faces the bypass capacitor lower electrode and is connected to the other of the power supply and the ground.

[0011]

The semiconductor integrated circuit according to claim 1 or 2 can be manufactured without adding a large number of steps to the steps required for forming a memory cell capacitor. A capacitor having a high capacity and a high withstand voltage can be obtained with high reliability. Claim 1
Each of the semiconductor integrated circuits according to the first and second aspects can be manufactured by the manufacturing method according to the third aspect.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a stacked memory cell of a DRAM to which the present invention is applied. In the figure, a MOS transistor for controlling writing / reading of information to be stored is shown in a portion on the left side from the center, and a memory cell on which charging / discharging is performed via this MOS transistor is shown on the right side. A capacitor is shown.
First, the configuration of the MOS transistor will be described. In FIG. 1, reference numeral 1 denotes S doped with a low concentration P-type impurity.
i-substrate. 2 is the source of each MOS transistor,
A high-concentration N-type impurity diffusion region formed as a drain,
Reference numeral 3 denotes an element isolation SiO ₂ film, and reference numeral 4 denotes an interlayer insulating film. 5
Is a polysilicon layer. Of these polysilicon layers, a polysilicon layer interposed between the source and the drain of the MOS transistor constitutes a gate electrode of the MOS transistor and serves as a word line of a memory cell. Used. Reference numeral 9 denotes a data line of a memory cell made of a conductive film such as Al (aluminum), a part of which is connected to one of the high-concentration N-type impurity diffusion layers 2.

Next, the configuration of the memory cell capacitor will be described. In FIG. 1, reference numeral 6 denotes a lower electrode, which is formed of a conductor layer in which polysilicon is doped with phosphorus or arsenic. A part of the lower electrode 6 is connected to the high concentration N-type impurity diffusion region 2. Reference numeral 7 denotes an insulating film of the memory cell capacitor, which is laminated so as to cover the lower electrode 6. This insulating film 7 has a multilayer structure in which at least a high dielectric film is interposed, and details thereof are shown in FIG. Reference numeral 8 denotes an upper electrode of the memory cell capacitor laminated on the insulating film 7, and is made of polysilicon doped with phosphorus or arsenic.

In such a configuration, when a positive voltage is applied to the word line 5, the Si substrate 1 immediately below the word line 5 is applied.
When the inversion layer is formed on the surface of the semiconductor device, the voltage applied to one high-concentration N-type impurity diffusion region 2 via the data line 9 is applied to the other high-concentration N-type impurity diffusion region 2 via the inversion layer. As a result, the memory cell capacitor including the lower electrode 6, the insulating film 7, and the upper electrode 8 is charged to a voltage level corresponding to information to be stored. Information is written in this manner. Reading of information is also performed by applying a positive voltage to the word line 5 in the same manner as described above. In this case, the voltage charged in the memory cell capacitor passes through the data line 9 via the reverse path. Is read out.

Next, a detailed configuration of the memory cell capacitor will be described with reference to FIG. As shown in the figure, the memory cell capacitor includes a lower SiO ₂ film 71, a high dielectric film 72 and an upper S
It has a structure in which a composite insulating film 7 formed by laminating iO ₂ films 73 is interposed. Here, the lower SiO ₂ film 71 is formed by exposing the lower electrode 6 to an atmosphere containing oxygen and being naturally oxidized, and has a thickness of about 20 °. The high dielectric film 72 is a film made of Si ₃ N ₄ having a thickness of about 80 ° deposited on the lower SiO ₂ film 71 by a CVD (chemical vapor deposition) method or the like. The upper SiO ₂ film 73 is obtained by oxidizing the high dielectric film 72 and has a thickness of about 20 °.

The memory cell capacitor having this structure can withstand a voltage of about 7 V. On the other hand, since a voltage of 通常 of the power supply voltage Vcc is normally applied to the upper electrode 8, when the power supply voltage Vcc is 5V, the maximum applied voltage to the memory cell capacitor is 2.5V. Therefore, it can be said that the memory cell capacitor having this structure has a sufficiently high withstand voltage as compared with the maximum applied voltage, and a highly reliable DRAM can be configured.

FIG. 3 is a sectional view showing a configuration of a power supply bypass capacitor of a DRAM to which the present invention is applied. Fig. 1
In FIG. 3, each element corresponding to each element shown in FIG. 1 is assigned the same reference numeral as that used in FIG. Have been.

As shown in FIG. 3, the present power supply bypass capacitor has a lower electrode 6 formed on the element isolating SiO ₂ film 3 in the same step as that of the memory cell capacitor, and is formed in the same step. Formed lower SiO
_A composite insulating film 7 composed of _two films 71, a high dielectric film 72 and an upper SiO ₂ film 73, and an upper SiO ₂ film 74 for improving withstand voltage formed by a process added especially for the power supply bypass capacitor; The structure is such that the upper electrode 8 formed in the same step as that of the memory cell capacitor is laminated. An insulating film made of SiO ₂ or the like is formed on the upper electrode 8, and the lower electrode 6 and the wiring electrode 10 of the upper electrode 8 are formed of Al (aluminum) or the like. The lower electrode 6 and the upper electrode 8 are each connected to either the power supply Vcc or the ground.

Here, the lower SiO 2 in the composite insulating film 7 is
_{The 2} film 71 is a SiO ₂ film having a thickness of about 10 to 20 ° formed by natural oxidation of the surface of the lower electrode 6, and the lower SiO ₂ film 71 of the memory cell capacitor.
Are formed at the same time in the step where is formed. The high dielectric film 72 in the composite insulating film 7 has a thickness of 40 to 120 °.
A the Si ₃ N ₄ film thickness ranging from, at the same time be deposited in high dielectric film 72 in the memory cell capacitor is deposited by a CVD method. Similarly, the upper SiO ₂ film 73 is the upper SiO ₂ film 7 in the memory cell capacitor.
3 and formed at the same time.

The SiO ₂ film 74 on the composite insulating film 7 has a CV
By the D method or the like, the deposition is performed so that the film thickness combined with the upper SiO ₂ film 73 becomes 50 to 600 °. This SiO ₂
The film 74 is particularly laminated to obtain a withstand voltage required as a power supply bypass capacitor. Where Si
When the combined film thickness of the O ₂ films 73 and 74 is 50 °, the breakdown voltage is 3 V or more. On the other hand, if the thickness is set to 600 ° or more, the capacity of the power supply bypass capacitor itself is reduced. Therefore, as described above, the SiO ₂ film 74 is
Lamination is performed so that the film thickness combined with the iO ₂ film 73 is in the range of 50 to 600 °.

<Manufacturing Method> A method of manufacturing a portion corresponding to the memory cell capacitor and the power supply bypass capacitor of the DRAM according to the present embodiment will be described below. (1) After a MOS transistor for a memory cell is formed on a Si substrate 1 as shown in FIG. 1, a conductor film containing polysilicon is laminated, and its patterning is performed.
Lower electrode 6 for a memory cell capacitor connected to high-concentration N-type impurity diffusion region 2 of an S transistor (see FIG. 1)
And a lower electrode 6 for a power supply bypass capacitor (see FIG. 3). (2) Next, a lower SiO ₂ film 71 having a thickness of about 10 to 20 ° is formed on the surface of the lower electrode 6 for the memory cell capacitor and the surface of the lower electrode 6 for the bypass capacitor by natural oxidation. A high dielectric film 72 such as a Si ₃ N ₄ film is deposited by a CVD method or the like. And
An upper SiO ₂ film 73 is formed on the high dielectric film 72.
Thus, the composite insulating film 7 as a part of the inter-electrode insulating film of the memory cell capacitor and the inter-electrode insulating film of the power supply bypass capacitor is formed. (3) Next, after depositing SiO ₂ by the CVD method or the like, patterning is performed, and the SiO ₂ film 74 is formed in a region corresponding to the upper side of the lower electrode 6 for the power supply bypass capacitor.
To form (4) Then, after laminating a conductor film containing polysilicon, patterning is performed to form an upper electrode 8 facing the lower electrode 6 for the memory cell capacitor and an upper electrode facing the lower electrode 6 for the power supply bypass capacitor. An electrode 8 is formed.

<Effects of the present embodiment> As described above, the power supply bypass capacitor of the present embodiment includes the lower electrode 6, the composite insulating film 7 made of a high dielectric film, and the upper electrode 8.
Can be formed by adding only the step of forming the SiO2 film 74 for improving the withstand voltage, which is common to the step of forming each layer in the memory cell capacitor. High capacity and high withstand voltage products can be manufactured with high reliability.

The electrodes of the capacitors such as the memory cell capacitor and the power supply bypass capacitor employed in the above-described embodiment all have polysilicon as a part thereof, and have a sheet resistance of 2 to 60 Ω / □. On the other hand, in the conventional MOS structure capacitor, one electrode is the surface of the Si substrate on which the inversion channel of the MOS transistor is formed, and the sheet resistance is several hundred to several KΩ / □. Therefore, the capacitor adopted in this embodiment has improved frequency response as compared with the conventional MOS structure capacitor, and is particularly useful for noise reduction. In particular, when a composite insulating film is formed as the insulating film, the defect rate can be extremely reduced,
In recent years, it is useful as a power supply bypass capacitor provided in a semiconductor integrated circuit whose speed has been increased.

<Other Embodiments> (1) A capacitor according to the present invention can use various insulating films, for example, Ta ₂ O ₅ , SrTiO ₃ or Si ₃ N ₄ instead of Si ₃ N _4. PZT or the like may be used. (2) Si ₃ N ₄ is not a CVD method, the lower electrode 6 N ₂
It is also possible to form by a thermal nitridation method that exposes to a high temperature in an atmosphere. In the above practical example, the composite insulating film between the electrodes of the capacitor has a three-layer structure of SiO ₂ —Si ₃ N ₄ —SiO ₂ , but in this case, the insulating film is Si ₃ N ₄ —SiO ₂ . (3) In the above embodiment, S is used as the insulating film for improving the breakdown voltage.
Although the iO ₂ film 74 was formed, the material of the insulating film was Si.
The material is not limited to O ₂ , and any material having a high withstand voltage such as Si ₃ N ₄ is applicable.

[0025]

As described above, according to the present invention, it is possible to manufacture a semiconductor integrated circuit having a power supply bypass capacitor without adding a large step to the steps required for forming a memory cell capacitor. There is an effect that can be. Further, the semiconductor integrated circuit according to the present invention has a high capacity and a high withstand voltage as the power supply bypass capacitor, and thus has an advantage of high performance and high reliability.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a memory cell portion in an embodiment in which the present invention is applied to a DRAM.

FIG. 2 is a sectional view showing a detailed configuration of a memory cell capacitor in a memory cell portion of the DRAM.

FIG. 3 is a sectional view showing a configuration of a power supply bypass capacitor portion of the DRAM.

[Explanation of symbols]

1 ... Si substrate, 2 ... high-concentration N-type impurity diffusion region, 3 ... isolation SiO ₂ film, 4 ... interlayer insulation film, 5 ... word lines,
6 lower electrode, 7 composite insulating film including high dielectric film, 71
... lower SiO ₂ film 72 ... high-dielectric film, 73 ... upper SiO ₂ layer, 74 ... Si
O ₂ film, 8: upper electrode.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-190792 (JP, A) JP-A-4-145623 (JP, A) JP-A-5-121654 (JP, A) JP-A-5-190654 102424 (JP, A) JP-A-5-235265 (JP, A) JP-A-5-235275 (JP, A) JP-A-3-22470 (JP, A) JP-A-5-102426 (JP, A) JP-A-61-218155 (JP, A) JP-A-4-237157 (JP, A) JP-A-62-35662 (JP, A) JP-A-60-211969 (JP, A) JP-A-1-239964 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/04 H01L 21/822 H01L 21/8242 H01L 27/108

Claims (3)

(57) [Claims] 1. A memory comprising an upper electrode for memory and a lower electrode for memory to which a voltage corresponding to information to be stored is applied, and a high dielectric film laminated between the upper electrode for memory and the lower electrode for memory. A memory cell capacitor including a memory insulating film; an upper electrode for a bypass capacitor and a lower electrode for a bypass capacitor each connected to one of a power supply and a ground; and a stack between the upper electrode and the lower electrode. A power supply bypass capacitor composed of the formed bypass capacitor insulating film and the bypass capacitor dielectric film added thereto, formed on the same semiconductor substrate, wherein the bypass capacitor upper electrode and the bypass capacitor are formed. The lower electrode is a conductor containing at least polysilicon and is Electrodes and has been formed by the lower electrode and the respective same process memory, the bypass capacitor insulating film and the memory insulating film semiconductor integrated circuit, characterized in that formed in the same step. 2. The semiconductor integrated circuit according to claim 1, wherein said memory insulating film and said bypass capacitor insulating film are composite insulating films. 3. An electrode made of a conductive film containing at least polysilicon on a semiconductor substrate on which a memory cell transistor is formed, wherein: a lower electrode for memory connected to the transistor for memory cell; Forming a lower electrode for a bypass capacitor connected to one of the grounds; forming an insulating film including a high dielectric film on the lower electrode for the memory and the lower electrode for the bypass capacitor; Forming a dielectric film for a bypass capacitor in a region corresponding to the lower electrode for a bypass capacitor, wherein the electrodes are made of a conductive film containing at least polysilicon, and the lower electrode for a memory is sandwiched between the insulating films. And a memory upper electrode opposed to the insulating film and the dielectric film for the bypass capacitor. Forming a bypass capacitor upper electrode opposed to the bypass capacitor lower electrode and connected to the other of the power supply and the ground.