JP2724459B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a method for forming a well (WELL) and a channel stopper (such as an element isolation region and a field dope region) of a semiconductor integrated circuit device. SUMMARY OF THE INVENTION The present invention obtains an impurity concentration profile of a retrograde WELL having a large latch-up resistance as shown in FIG. It is possible to form. [Related Art] Conventionally, formation of a WELL region in a semiconductor integrated circuit device has been performed before forming an oxide film for element isolation. This is because the acceleration voltage for ion implantation is constant, and the upper limit is several hundred kev. Therefore, the impurity profile for obtaining a desired surface concentration and depth as a MOS transistor is as shown in FIG. 2. In particular, in the case of a P-type WELL-CMOS, the relative WELL resistance was high. Also, in the region of the channel stopper, impurities are introduced before the element isolation oxide film forming step, separately from the formation of the WELL due to the restriction of the ion implantation voltage. [Problems to be Solved by the Invention] As described above, the conventional technology has problems such as low latch-up resistance due to a high resistance value of WELL. Also, the number of steps was large, such as separately forming a channel stopper. [Means for Solving the Problems] The present invention for solving the problems includes a step of selectively forming an isolation insulating film for isolating an element formation region on a main surface of a semiconductor substrate; Forming a mask material for ion implantation on the main surface, and exposing and developing the mask material for ion implantation by using a photoresist to cover at least a part of the isolation insulating film and a part of an element formation region. Selectively exposing a region including the ion-exposed region, etching and removing the ion implantation mask material in the selectively exposed region, removing the photoresist, and removing the ion implantation mask material. An impurity is introduced into the main surface of the semiconductor substrate through the formed region, and an impurity is introduced into a part of the lower part of the isolation insulating film and the element formation region, thereby forming a channel stopper region and a well A method for manufacturing a semiconductor integrated circuit device, comprising: a step of forming a region; and a step of removing the mask material for ion implantation. Here, the mask material for ion implantation contains, for example, a metal element. The introduction of the impurity is performed by, for example, an ion implantation method using a plurality of types of energy intensities. That is, in the present invention, variable ion implantation from several keV to several Mev of the acceleration voltage is performed in the impurity introduction for WELL formation. At the same time, impurities are introduced into the channel stopper region. [Operation] By taking the above-described means, a method of manufacturing a semiconductor integrated circuit device with a small number of steps for realizing a retrograde WELL structure having high latch-up resistance and simultaneously forming a channel stopper has become possible. FIG. 1 shows an impurity concentration profile of a P-type well in a semiconductor integrated circuit device manufactured by the manufacturing method of the present invention. Embodiments of the present invention will be described in the order of manufacturing steps with reference to FIGS. 3 (a) to 3 (e). First, a Pad oxide film 2 is formed on an N-type Si substrate 1. Then, the SiN film 3 is deposited, and S
The iN film 3 is removed [FIG. 3 (a)]. Next, an element isolation oxide film 4 is formed [FIG. 3 (b)]. Next, an Al sputtered film or the like is deposited as the ion implantation mask material 5, and the mask material in the P-WELL and the channel stopper region is removed by photolithography. After a while, several kev ~
The voltage variable ion implantation 6 of several Mev is performed [FIG. 3 (c)]. Next, N-WELL and N-
A WELL-side channel stopper region is also formed, and a heat treatment for diffusion is performed [FIG. 3 (d)]. Next, the Pad oxide film 2 is removed, and oxidation for forming a gate oxide film of the MOS transistor is performed. Then, similarly to the conventional method of manufacturing an integrated circuit device, formation of a gate electrode, formation of a source / drain,
It is completed through steps such as formation of an Al wiring [FIG. 3 (e)]. [Effects of the Invention] (1) As can be seen from the WELL concentration profile in FIG. 1, it is possible to manufacture an integrated circuit device having high latch-up resistance. (2) As can be seen from the cross-sectional views in the order of the manufacturing process shown in FIG. 3, two processes for forming the channel stopper can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an impurity concentration profile of a P-type well in a semiconductor integrated circuit device manufactured by a manufacturing method of the present invention. FIG. 2 is a diagram showing a WELL impurity concentration profile made by a conventional manufacturing technique. 3 (a) to 3 (e) are cross-sectional views of a semiconductor integrated circuit device using the present invention in the order of manufacturing steps. 1 N-type Si substrate 2 Pad oxide film 3 SiN film 4 Oxide film for element isolation 5 Patterned ion implantation mask material 6 Boron implanter 7 P-WELL region of as-implant 8. As-implant channel stopper region 9 ... Diffused WELL region 10 ... Diffused channel stopper region 11 ... Diffused N-WELL 12 ... Diffused N-type channel stopper region 13 ... Gate oxidation Film 14 Gate electrode 15 Source or drain region 16 Intermediate insulating layer 17 Al wiring 18 Final protective film

Claims (1)

(57) [Claims] A step of selectively forming an isolation insulating film for separating an element formation region on a main surface of a semiconductor substrate; a step of forming a mask material for ion implantation on a main surface of the semiconductor substrate; and a mask material for ion implantation A step of selectively exposing a region including at least a part of an element formation region while covering at least a part of the isolation insulating film by an exposure and development method using a photoresist; and A step of etching and removing the mask material for ion implantation; a step of removing the photoresist; and introducing an impurity by ion implantation into a main surface of the semiconductor substrate through a region from which the mask material for ion implantation is removed; Forming a channel stopper region and a well region by introducing an impurity into a part of the isolation insulating film and the element formation region; The method of manufacturing a semiconductor integrated circuit device characterized in that it comprises a step of removing the click member, a. 2. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said mask material for ion implantation contains a metal element. 3. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the impurity is introduced by an ion implantation method using a plurality of types of energy intensities. Manufacturing method.