JP2706720B2 - Voltage regulator - Google Patents
Voltage regulatorInfo
- Publication number
- JP2706720B2 JP2706720B2 JP33101190A JP33101190A JP2706720B2 JP 2706720 B2 JP2706720 B2 JP 2706720B2 JP 33101190 A JP33101190 A JP 33101190A JP 33101190 A JP33101190 A JP 33101190A JP 2706720 B2 JP2706720 B2 JP 2706720B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- voltage regulator
- error amplifier
- voltage
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Continuous-Control Power Sources That Use Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、CMOSモノリシックIC化されたボルテージ・
レギュレーターに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a CMOS monolithic IC.
It is about a regulator.
本発明は、ボルテージ・レギュレーター内の誤差増幅
器の電流値を決定するトランジスタ、もしくは抵抗に対
し、ポリシリコン抵抗、もしくはアルミ配線によって形
成されたリンク部材を付加し、そのリンク部材の一部も
しくは全てを切断すことで、低消費電流で負荷応答性能
の高いボルテージ・レギュレーターを提供するものであ
る。According to the present invention, a link member formed by a polysilicon resistor or aluminum wiring is added to a transistor or a resistor that determines a current value of an error amplifier in a voltage regulator, and a part or all of the link member is added. By disconnecting, a voltage regulator with low current consumption and high load response performance is provided.
従来の正の出力電圧を持つボルテージ・レギュレータ
ーの回路図を第２図に示す。基準電圧回路１と抵抗R1と
R2とから取り出された電圧は、トランジスタM1〜M5で構
成される誤差増幅器２で比較され、出力トランジスタ３
を制御する。つまり、抵抗R1、R2から取り出された電圧
が、基準電圧より小さければ、誤差増幅器２の出力は低
くなり、出力トランジスタ３を強くバイアスし、逆に、
抵抗R1、R2から取り出された電圧が基準電圧より高けれ
ば出力トランジスタ３を弱くバイアスして出力端子４に
は一定の電圧が得られる。FIG. 2 is a circuit diagram of a conventional voltage regulator having a positive output voltage. A reference voltage circuit 1 and the resistor R 1
Voltage taken from R 2 Prefecture is compared with composed error amplifier 2 in transistor M 1 ~M 5, the output transistor 3
Control. That is, if the voltages taken out of the resistors R 1 and R 2 are smaller than the reference voltage, the output of the error amplifier 2 becomes low, and the output transistor 3 is strongly biased.
If the voltage extracted from the resistors R 1 and R 2 is higher than the reference voltage, the output transistor 3 is weakly biased and a constant voltage is obtained at the output terminal 4.
第２図のボルテージ・レギュレーターの場合、次のよ
うな問題点が生じる。In the case of the voltage regulator shown in FIG. 2, the following problems occur.
トランジスタM5の電流値をI5、誤差増幅器２の負荷と
なる出力トランジスタ３のゲート容量値をＣとすると、
誤差増幅器２のスルー・レートSRは、式（１）で表わさ
れる。I 5 The current value of the transistor M 5, when the gate capacitance of the output transistor 3 as a load of the error amplifier 2 is C,
The slew rate SR of the error amplifier 2 is expressed by equation (1).
SR＝I5/C ……（１） 式（１）から明らかなように、誤差増幅器２の応答性
能を高めるには、I5を大きくし、Ｃを小さくすれば良
い。SR = I 5 / C (1) As is apparent from the equation (1), the response performance of the error amplifier 2 can be improved by increasing I 5 and decreasing C.
I5はトランジスタのしきい値電圧や移動度のプロセス
・バラツキがあり、通常の値に対し、例えば、最小で
は、1/3程度に減少し、最大では３倍程度に増大する。
最小でも、ある所望のSRを得ようとすれば、I5の電流は
プロセスバラツキを考えて、通常で、最低限必要な電流
の３倍の電流を流し、最大では最低限必要な電流の９倍
の電流を流すことになり、ボルテージ・レギュレーター
の消費電流の増大を招くことになる。I 5 has process variations in threshold voltage and mobility of the transistor, to a normal value, for example, in the minimum, reduced to about 1/3, the maximum increases to approximately 3-fold.
At a minimum, in order to obtain a certain desired SR, current I 5 think the process variation, in general, flushed three times the current of the minimum required current, the minimum required current is up to 9 As a result, twice the current flows, which increases the current consumption of the voltage regulator.
本発明は、従来の技術の課題を解決することを目的と
し、とりわけ、低消費電流で負荷応答性能の高いボルテ
ージ・レギュレーターを提供できた。An object of the present invention is to solve the problems of the related art, and in particular, was able to provide a voltage regulator with low current consumption and high load response performance.
具体的には、誤差増幅器２に流す電流値をトリミング
することによって、プロセスバラツキによる電流値のバ
ラツキを抑え、低消費電流で負荷応答性能を高めるもの
である。Specifically, by trimming the current value flowing through the error amplifier 2, variations in the current value due to process variations are suppressed, and the load response performance is improved with low current consumption.
本発明のボルテージ・レギュレーターは、第４図のよ
うにプロセスバラツキによる電流値のバラツキを抑えら
れるため、低消費電流で、負荷応答性能を高めることが
できる。The voltage regulator of the present invention can suppress the variation in the current value due to the process variation as shown in FIG. 4, so that the load response performance can be improved with low current consumption.
以下、図面に従って本発明の実施例を詳細に説明す
る。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図は、本発明の正の出力電圧を持つボルテージ・
レギュレーターの回路図である。基準電圧回路１、出力
トランジスタ３、及び抵抗R1、R2は第２図と同様であ
る、誤差増幅器２は、従来のトランジスタM5の代わり
に、誤差増幅器２に流れる電流をトリミングすることが
可能な素子６が、挿入されている。FIG. 1 shows a voltage output having a positive output voltage of the present invention.
It is a circuit diagram of a regulator. Reference voltage circuit 1, the output transistor 3, and a resistor R 1, R 2 is the same as FIG. 2, the error amplifier 2, instead of the conventional transistor M 5, is possible to trim the current flowing through the error amplifier 2 A possible element 6 has been inserted.
第３図に、このトリミング素子の回路図の一例を示
す。トランジスタM6のドレインを、トランジスタM3、M4
のソースに結線し、トランジスタM6のソースとトランジ
スタM7のドレインを結線し、トランジスタM7のソースと
トランジスタM8のドレインを結線し、トランジスタM8の
ソースとグランド端子５を結線し、トランジスタM6〜M8
のゲートは全てトランジスタM3のゲートに結線し、か
つ、リンク部材L1の一端をトランジスタM6、M7のソー
ス、ドレインの接続点に結線し、他端をグランド端子５
に結線し、リンク部材L2の一端をトランジスタM7、M8の
ソース、ドレインの接続点に結線し、他端をグランド端
子５に結線している。FIG. 3 shows an example of a circuit diagram of the trimming element. The drain of the transistor M 6, transistor M 3, M 4
The source and connect, and connecting the drain of the source and the transistor M 7 of the transistor M 6, and connect the source and drain of the transistor M 8 of the transistor M 7, and connect the source and the ground terminal 5 of the transistor M 8, transistor M 6 to M 8
The gate is connected all to the gate of the transistor M 3, and to connect the one end of the link member L 1 the source of the transistor M 6, M 7, the connection point of the drain, the ground terminal 5 and the other end
And connect to, and connect one end of the link member L 2 sources of the transistors M 7, M 8, the connection point of the drain, and connecting the other end to the ground terminal 5.
例えば、トランジスタM6〜M8の幅Ｗ長を等しくし、こ
れをW6とし、トランジスタM6〜M8の長さＬ長を等しく
し、これをL6とする。今M6〜M8からなるトランジスタの
W/L比をK6とすれば、K6の値はリンク部材L1、L2の切
断、非切断によって次のようになる。For example, the widths W of the transistors M 6 to M 8 are made equal, and this is set to W 6, and the lengths L of the transistors M 6 to M 8 are made equal, which is set to L 6 . From consisting of transistors now M 6 ~M 8
If the W / L ratio and K 6, the value of K 6 is cut of the link member L 1, L 2, by a non-cutting as follows.
L1、L2共に非切断の時K6＝W6／L6 L1断切の時K6＝W6／（２×L6） L1、L2共に切断の時K6＝W6／（３×L6） すなわち、プロセスバラツキによって誤差増幅器の電
流が所望の値より多ければ、L1、L2を切断し、逆に、所
望の値より少なければ、L1、L2を非切断とすれば、誤差
増幅器の電流を所望の値に近ずけることが可能である。
つまり、プロセスバラツキによる電流値のバラツキを第
４図のように小さく抑えることができる。L 1, L 2 are both K 6 = W 6 / when K 6 = W 6 / L 6 L 1 sever when uncleaved (2 × L 6) L 1 , L 2 together when cutting K 6 = W 6 / (3 × L 6 ) That is, if the current of the error amplifier is larger than a desired value due to process variation, L 1 and L 2 are cut off, and if less than the desired value, L 1 and L 2 are not cut off. Then, the current of the error amplifier can be made closer to a desired value.
That is, the variation in the current value due to the process variation can be suppressed as shown in FIG.
以上述べたように本発明によれば、誤差増幅器の電流
値をトリミングすることによって、プロセスバラツキに
よる電流値のバラツキを抑え、低消費電流で負荷応答性
能の高いボルテージ・レギュレーターを提供できるとい
う効果がある。As described above, according to the present invention, by trimming the current value of the error amplifier, it is possible to suppress the variation in the current value due to the process variation and to provide a voltage regulator with low current consumption and high load response performance. is there.
第１図は本発明のボルテージ・レギュレーターの回路
図、第２図は従来のボルテージ・レギュレーターの回路
図、第３図はトリミング素子の一例の回路図、第４図は
プロセスバラツキと電流値のバラツキとの関係図であ
る。 １……基準電圧回路 ２……誤差増幅器 ３……出力トランジスタ ４……出力端子 ５……グランド端子 ６……トリミング素子 L1、L2、Ln……リンク部材1 is a circuit diagram of a voltage regulator according to the present invention, FIG. 2 is a circuit diagram of a conventional voltage regulator, FIG. 3 is a circuit diagram of an example of a trimming element, and FIG. 4 is a process variation and a variation of a current value. FIG. 1 ...... reference voltage circuit 2 ...... error amplifier 3 ...... Output transistor 4 ...... output terminal 5 ...... ground terminal 6 ...... trimming elements L 1, L 2, L n ...... link member
Claims (1)
れたボルテージ・レギュレーターにおいて、前記誤差増
幅器に流す電流値をトリミングする手段を具備すること
を特徴としたボルテージ・レギュレーター。1. A voltage regulator comprising a CMOS monolithic IC including an error amplifier, comprising: means for trimming a value of a current flowing through the error amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33101190A JP2706720B2 (en) | 1990-11-28 | 1990-11-28 | Voltage regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33101190A JP2706720B2 (en) | 1990-11-28 | 1990-11-28 | Voltage regulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04195613A JPH04195613A (en) | 1992-07-15 |
| JP2706720B2 true JP2706720B2 (en) | 1998-01-28 |
Family
ID=18238829
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33101190A Expired - Lifetime JP2706720B2 (en) | 1990-11-28 | 1990-11-28 | Voltage regulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2706720B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102692943A (en) * | 2011-03-24 | 2012-09-26 | 精工电子有限公司 | Voltage regulator |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5646166B2 (en) * | 2009-12-25 | 2014-12-24 | 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． | Power circuit |
| US8188719B2 (en) | 2010-05-28 | 2012-05-29 | Seiko Instruments Inc. | Voltage regulator |
| JP2012168899A (en) | 2011-02-16 | 2012-09-06 | Seiko Instruments Inc | Voltage regulator |
| JP6250418B2 (en) | 2013-05-23 | 2017-12-20 | エスアイアイ・セミコンダクタ株式会社 | Voltage regulator |
| JP6316647B2 (en) | 2014-04-25 | 2018-04-25 | エイブリック株式会社 | Overcurrent protection circuit, semiconductor device, and voltage regulator |
-
1990
- 1990-11-28 JP JP33101190A patent/JP2706720B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102692943A (en) * | 2011-03-24 | 2012-09-26 | 精工电子有限公司 | Voltage regulator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04195613A (en) | 1992-07-15 |
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