JP2706363B2 - Semiconductor storage device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of performing an operation test at high speed.

<Conventional Technology> In recent years, semiconductor storage devices have made remarkable progress.
The degree of integration of M (random access memory), ROM (read only memory) and other memories has steadily increased four times in three years. The time required for device operation tests has been increasing along with this, and in order to efficiently carry out shipping inspection on the manufacturing side and acceptance inspection on the user side,
There is a need to establish a faster test mode.

Conventionally, in such a situation, in order to perform an operation test at a high speed, for example, a so-called parallel test mode for testing a plurality of bit lines in parallel has been adopted in a DRAM (Dynamic Random Access Memory). In the parallel test mode, the same data is written to a plurality of bits at the same time, and the data is compared at the time of reading, and if there is even one different data, it is determined to be defective.

<Problems to be solved by the invention> However, the conventional parallel test mode is about 1M
The reality is that the test time of × 1 DRAM is not exceeded.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device capable of testing one row (practically, about 1024 bits or 2048 bits) in parallel, and thus performing an operation test at high speed.

<Means for Solving the Problems> In order to achieve the above object, a semiconductor memory device of the present invention writes and reads the same data in a plurality of memory cells in parallel through a pair of bit lines operating in a complementary manner. A possible semiconductor memory device, comprising: a line data storage circuit for outputting an expected value signal representing data written to a specific memory cell via a bit line connected to the memory cell; and writing to the specific memory cell. A signal based on data or the expected value signal from the line data storage circuit is received as an input signal, and a pair of bits of a memory cell other than the memory cell according to the level of the input signal. A bit line selection circuit for selecting one or the other bit line, and a potential supply circuit for applying a predetermined potential to the selected bit line Path, a bit line selection by the bit line selection circuit based on a signal based on data written to the specific memory cell, and supply of a predetermined potential by the potential supply circuit, in parallel with the specific memory cell. An output signal written to another memory cell and representing the same data as the expected value signal is detected via one of the bit lines selected by the bit line selection circuit when the expected value signal is at a high level. On the other hand, when the expected value signal is at a low level, it is detected through the other bit line selected by the bit line selection circuit, and the output signal and the expected value signal are detected in accordance with the level of the detected output signal. And an output determination circuit for outputting a signal indicating a match or a mismatch with.

<Operation> When the data written in a specific memory cell is at the logical level “1”, the expected value signal output from the line data storage circuit is at a high level. At this time, the output determination circuit detects an output signal that should represent the same data as the data written in the other memory cell via one of the bit lines selected by the bit line selection circuit. The one bit line is at a high or low level representing the output signal. The output determination circuit outputs a signal indicating a match or a mismatch between the output signal and the expected value signal according to whether the detected level is higher or lower. For example, when one of the bit lines goes low when the other memory cell is read normally,
When the detected level is low, a signal indicating a match is output, while when the detected level is high, a signal indicating a mismatch is output.

On the other hand, when the data written in the specific memory cell is at the logical level “0”, the expected value signal output from the line data storage circuit becomes low. At this time, the output determination circuit
An output signal representing the same data as the data written in the other memory cells is detected via the other bit line selected by the bit line selection circuit. Explaining with reference to the above example, when reading of the other memory cell is performed normally, the output signal is inverted, so that the other bit line goes low. here,
The output determination circuit outputs a signal indicating a match when the detected level is a low level, and outputs a signal indicating a mismatch when the detected level is a high level. Therefore, the output determination circuit outputs a signal indicating a match when the other memory cell is normally read, and outputs a signal indicating a mismatch when the read is erroneous. As described above, the output determination circuit performs the above-described operation even when the same data simultaneously written in the specific memory cell and the other memory cell is at any of the logical levels “0” and “1”. A signal indicating a match is output when the reading of the memory cell is normally performed, and a signal indicating a mismatch is output when the reading of the other memory cell is erroneous.

Generally, memory cells for one row can be simultaneously selected by one word line. Therefore, by causing the bit line selection circuit to simultaneously select one or the other of the pair of bit lines of the memory cells for one row in parallel and simultaneously operating the output determination circuit for each memory cell, The memory cells for one row can be tested at the same time. Therefore, the operation test is performed at high speed.

Embodiment Hereinafter, a semiconductor memory device according to the present invention will be described in detail with reference to embodiments.

FIG. 1 shows a DRAM according to an embodiment of the present invention. This DRAM includes a line data storage circuit 1, a bit line selection circuit 2, and an output determination circuit 3. Reference numeral 4 denotes a memory cell array, and reference numeral 5 denotes a sense amplifier array including sense amplifiers 51, 52,. The memory cell array 4 is 1
One row of memory cells 41, 42,... Simultaneously selected by the word lines WL. Data is written to and read from the memory cells 41 and 42 via each pair of bit lines B and B #; BL and BL # that operate complementarily. Note that only the bit lines B and BL of the pair of bit lines are actually connected to the memory cells 41 and 42. The sense amplifiers 51 and 52 of the sense amplifier array 5 are connected to the bit lines B and B #, respectively.
Amplify the voltage between BL and BL #. The line data storage circuit 1 includes an NMOS transistor 11 controlled by a signal φ11.
And inverters 12 and 13 connected in anti-parallel, and signal φ
NMOS transistors 14 and 15 controlled simultaneously by 12
It has. Then, data represented by the input signal DIN can be written to the memory cell 41 via the bit lines B and B #, and a signal DIN # obtained by inverting the input signal DIN can be output to the bit line selection circuit 2. . Further, the data written in the memory cell 41 can be read as an expected value signal E, and this signal E can be inverted to be a signal E # and output to the bit line selection circuit 2. Bit line selection circuit 2 includes an AND circuit 21 receiving signal φ21 and
22 and an inverter 23 connected between the input terminals of the AND circuits 21 and 22. Then, upon receiving the signal DIN # or the expected value signal E # from the line data storage circuit 1, the bit line BL or BL # of the memory cell 42 is changed according to the level of each signal DIN #, E #. A pair of selection signals S and S # to be selected are output. The output determination circuit 3
A PMOS transistor 32 is connected between the power supply and the output line DOUT and is turned on and off by a signal φ32, and an NMOS transistor 35 is connected between the output line DOUT and the ground. The gate of the NMOS transistor 35 is an NMOS transistor
They are connected in parallel to the bit lines BL, BL # via 33,34. The NMOS transistors 33 and 34 are controlled by selection signals S and S # from the bit line selection circuit 2, respectively. The output determination circuit 3 includes an NMOS transistor 31 connected between the gate of the NMOS transistor 35 and the ground and controlled by a signal φ31.

This DRAM operates as follows based on the operation timing shown in FIG. In FIG. 2, the broken line indicates the timing of the write operation, and the solid line indicates the timing of the read operation.

 First, the write operation will be described.

In the precharge state (the state at the left end in the operation timing shown in FIG. 2), the signal φ21 is at the low (L) level, and the outputs of the AND circuits 21 and 22 of the bit line selection circuit 2 are both at the L level. Both the NMOS transistors 33 and 34 of the determination circuit 3 are non-conductive.
The signal φ31 is at a high (H) level, and the signal φ32 is at an L level.

When a write operation starts, an H or L level is applied to the input signal DIN in accordance with the input data. And
When the signal φ11 rises, NM of the line data storage circuit 1
The OS transistor 11 becomes conductive and the input signal DIN
Is latched by inverters 12 and 13. Thereafter, when the signal φ21 rises to the H state, when the input signal DIN is at the H level, that is, when DIN # is at the L level, the selection signals S, S
# Indicates L level and H level, respectively. Therefore, NM
The OS transistor 34 becomes conductive, and the bit line BL #
Deducted to GND level. On the other hand, NMOS transistor 3
3 is in a non-conducting state, so that the bit line BL is at the level of the original precharged state (usually 1/2 Vcc level is used)
It is still. On the other hand, when the input signal DIN is L
Level, that is, when the signal DIN # is at the H level, the selection signal
S and S # are H level and L level, respectively. Therefore, the NMOS transistor 33 becomes conductive and the bit line BL
Is dropped to the GND level. On the other hand, since the NMOS transistor 34 is non-conductive, the bit line BL # remains at the level of the original precharged state.

In parallel with such an operation on the memory cell 42 side, a signal φ12 is raised on the memory cell 41 side, and the NMOS transistors 14 and 15 of the line data storage circuit 1 are turned on.
Input data is written to bit lines B and B #. When the input vibration DIN is at H level, the bit lines B and B # are at H level and L level, respectively. When the input signal DIN is at L level, the bit lines B and B # are at L level and H level, respectively. Become. After the rise of the word line WL, the sense amplifiers 51 and 52 of the sense amplifier array 5 are driven, and the bit line pair
B, B #; the level of the bit line pair BL, BL # is the memory cells 41, 42
Is amplified to a level sufficient to be written to Finally, the word line WL is dropped, and the write operation to the memory cells 41 and 42 ends. In this manner, the same data is simultaneously written to the memory cells 41, 42,... Via each pair of bit lines B, B #; BL, BL #.

Next, the read operation and the determination operation will be described.

When the read operation starts, as shown in FIG. 2, the word line WL rises, the sense amplifiers 51 and 52 are driven, and the data written in the memory cells 41 and 42 is transferred to the bit line pair B and B #. Read out to the bit line pair BL, BL #, respectively.
Further, signal φ12 rises, and expected value signal E representing the data written in memory cell 41 is output to bit line selection circuit 2 as inverted signal E #.
When the signal φ31 goes low and the signal φ32 goes high when the determination operation starts, the signal φ21 rises.

Here, when the input data written in the memory cell 41 is logic “1”, the expected value signal E becomes H level, that is, the signal E
# Becomes L level. At this time, the selection signals S and S # are at L level and H level, respectively. Therefore, the NMOS transistor 34 of the output determination circuit 3 becomes conductive, and the level of the bit line BL # is input to the gate of the NMOS transistor 35. If the reading of the memory cell 42 is normally performed, the data line BL # should be at the L level.
When the data line BL # is at L level, the gate of the NMOS transistor 35 is given L level, and the NMOS transistor 35 remains non-conductive. Therefore, the output line DOUT has H
The level is output. On the other hand, when reading of the memory cell 42 is erroneous, the data line BL # is at the H level. Therefore, the NMOS transistor 35 is turned on, and an L level indicating a mismatch is output to the output line DOUT.

On the other hand, the data written in the memory cell 41 is logic “0”.
, The expected value signal E is at the L level, that is, the signal E # is at the H level.
Level. At this time, the selection signals S and S # are H
Level, L level. Therefore, the output determination circuit 3
The NMOS transistor 33 becomes conductive, and the level of the bit line BL becomes NM.
Input to the gate of OS transistor 35. If the reading of the memory cell 42 is normally performed, the data line
BL should be at L level. Data line BL is L
When the level is at the level, the NMOS transistor 35 is supplied with the L level at the gate and remains non-conductive. Therefore, an H level indicating coincidence is output to output line DOUT. On the other hand, when reading of the memory cell 42 is erroneous, the data line BL is at the H level. NM
The OS transistor 35 is turned on, and an L level indicating a mismatch is output to the output line DOUT.

In this way, in this DRAM, the same input data simultaneously written into the memory cells 41 and 42 has the logic level “0”,
In either case of "1", a signal indicating a match is output when reading of the memory cell 42 is normally performed, and a signal indicating mismatch when reading of the memory cell 42 is erroneous. Is output. And the above word line
The NMOS transistors 33, 34 and 3 of the output determination circuit 3 are provided for each of the other memory cells (not shown) selected simultaneously by WL.
By providing 5 and operating simultaneously, one row of memory cells can be tested simultaneously. Therefore, an operation test can be performed at high speed.

The memory cells 41 and 42 are connected to only one of the pair of bit lines B and B #; BL and BL # that operate complementarily. For example, as shown in FIG.
This corresponds to the case where a cell plate voltage is applied to one terminal of the capacitor, which is composed of a transistor and a capacitor. However, the present invention is not limited to this, and as shown in FIG. 4 or FIG.
The present invention can be applied to a case in which both are connected to both bit lines BL and BL # (US Pat. No. 4,792,922).

 Next, a second embodiment of the present invention will be described.

FIG. 6 shows a DRAM test circuit of the second embodiment,
FIG. 7 shows control signals φ ₁ and φ ₂ input to the test circuit.
And φ represents a _third input waveform.

6, reference numeral 101 denotes an expected value generation circuit corresponding to the line data storage circuit 1 shown in FIG. 1, and reference numeral 102 similarly denotes a data signal selection circuit corresponding to the bit line selection circuit 2 shown in FIG. ing. 103-108 are inverters,
109 is a P-type MOS transistor, 110 to 114 are N-type MOS transistors, and 115 and 116 are NAND (Negative OR) gates. Output judging circuit includes a first switch SW ₁ composed of transistors 12-14, and a second switch SW ₂ consisting of transistor 11. In addition, the transistor 109
And 110 constitute a switch SW ₃ for temporarily holding the expected value to the output signal line S.

This test circuit checks whether or not the expected value output from the expected value generation circuit 101 and the level of the data line D are the same as follows. Note that here the expected value is
VCC or GND. In addition, data lines D and D always receive data having phases opposite to each other. The one data is obtained by inputting a signal output from one bit terminal to an inverter (not shown), and the other data is obtained directly from the bit terminal.

First, as shown in FIG. 7, the signal φ ₁ falls (t ₁ ), and the N-type MOS transistors 113 and 114 are turned off through the data line selection circuit 102. Next, the signal φ ₂ falls (t ₂ ), and the transistor 112
Is turned on, and the node connected to the gate of the N-type MOS transistor 111 is discharged. As a result, the N-type MOS transistor 111 is turned off. Further, the signal φ ₃ falls (t ₃ ), and the P-type MOS transistor 109 and the N-type MOS transistor 110 are turned on to give an expected value to the output signal line S.

To compare the expected value with the level of the data line D, first, the signals φ ₂ and φ ₃ are raised (t ₄ ), and the transistor 1
Turn off 09, 110 and 112. Next, φ ₁ rises (t ₅ ), and the data line selection circuit 102 is enabled, that is, put into an operable state in response to an expected value.

When the expected value is VCC, the transistor 113 is turned on through the data line selection circuit 2, and the output of the data line is input to the gate of the N-type transistor 111. Here, if the expected value and the level of the data line D match, the level of the data line is GND, so that the N-type transistor 111 remains off and the expected value is output to the output signal line S. Output as is. Conversely, if the expected value and the level of the data line D do not match, the data line is at VCC, so that the N-type transistor 111 is turned on and the output signal line S
Is rewritten to the level of the fail signal line, and as a result, data having a phase opposite to the expected value is output to the output signal line S.

On the other hand, when the expected value is GND, the transistor 114 is turned on through the data line selection circuit 102, and the level of the data line D is output to the gate of the N-type transistor 111. Here, if the expected value matches the output of the data line D, the output of the data line D is at GND, so that the N-type transistor 111 remains off and the output signal line S has the expected value. Is output as is. Conversely, if the expected value and the level of the data line D do not match, the data line D is VCC, so that the N-type transistor 111 is turned on and the output signal line S
Is rewritten to the level of the fail signal line, and as a result, data having a phase opposite to the expected value is output to the output signal line S.

As described above, if the expected value matches the output of the data line, the transistor 111 is turned off and the expected value is output to the output signal line S. If the expected value and the output of the data line do not match, the transistor 111 is turned on. As a result, the output signal line S outputs the level of the fail signal line, that is, data having a phase opposite to the expected value.

In this circuit, the data selection signal from the data line selection circuit 102, the output signal line S, and the fail signal line can be shared by a plurality of data line pairs. If this is used for, for example, a semiconductor memory device (DRAM, SRAM, ROM, etc.), data output to a plurality of data lines D, can be determined at a time.
Device test time can be reduced. Also,
Even if the data of all the bits is erroneous, it can be detected that the data is erroneous. In addition, it is possible to avoid using a complicated circuit configuration such as EXOR (exclusive OR).

Note that a P-type M transistor is used instead of the N-type MOS transistors 111 to 114.
OS or MOS can be used, and the first switch SW ₁
May be replaced by a logic circuit as shown in FIG. 8, for example.

Next, a circuit configuration for simultaneously performing writing for one row will be described.

FIG. 9 shows a configuration of a one-row parallel write circuit in a DRAM. In FIG. 9, 201 is a write control circuit, 202 is a write circuit, 203 is a sense amplifier, 204
Indicates storage elements, respectively. FIG. 1 shows only one set of a circuit composed of a write circuit 202, a sense amplifier 203, a storage element 204, a bit line pair BL, BL #, etc. Output line O
A plurality of UT1, OUT2 and word lines WL are connected in parallel. Note that 211 is an inverter, 212 and 213 are AND (logical product) gates, and 21 and 22 are NMOS transistors.

In the precharge state, the write control signal φp is at “L” level, and the outputs of the AND gates 212 and 213 are both at “L” level. Therefore, the NMOS transistors 221 and 222 are both in a non-conductive state.

When a write operation is started, an “H” level or an “L” level corresponding to input data is applied to the input signal DIN.
Thereafter, when the control signal φp rises to the “H” level, if the input signal DIN is the “H” level, the NMOS transistor 222 is turned on and the bit line BL # is pulled down to the GND level. On the other hand, if the input signal DIN is “L” level, NMO
The S transistor 221 becomes conductive, and the bit line BL becomes GN
Deducted to D level. In any case, the bit lines that have not been dropped are kept at the original precharged state level (usually 1/2 Vcc level is used).

Next, after starting the word line WL, the sense amplifier 203
To change the level of the bit line pair BL, BL # to the storage element 204.
Is amplified to a level sufficient to write data into the memory. Finally, the word line WL is dropped, and the write operation to the storage element 204 ends.

.. Connected to the word line WL, the writing is performed simultaneously, that is, in parallel, according to the output of the common write control circuit 201.

Note that, as shown in FIG.
Add transistors 223 and 224 and connect one bit line to GND
The other level may be set to the Vcc level. Further, the AND gates 212 and 213 of the write control circuit 201 are changed to OR (logical sum) gates, and the control signal φp is set to “H” or “L”.
May be reversed. Furthermore, the writing circuit
By using PMOS transistors instead of the NMOS transistors 221 and 222 of 202, the level of the bit lines BL and BL # is changed from GND to Vc
The circuit configuration may be changed as appropriate such as c.

<Effects of the Invention> As is clear from the above, the semiconductor memory device of the present invention has a line data storage for outputting an expected value signal representing data written in a specific memory cell via a bit line connected to the memory cell. A circuit and a signal based on write data to the specific memory cell, or the expected value signal from the line data storage circuit as an input signal thereof. A bit line selection circuit for selecting one or the other bit line of a pair of bit lines of a memory cell other than the cell, a potential supply circuit for applying a predetermined potential to the selected bit line, Selection of a bit line by the bit line selection circuit based on a signal based on write data to a specific memory cell, and a predetermined potential by the potential supply circuit Supplies the output signal to be written to the other memory cell in parallel with the specific memory cell and representing the same data as the expected value signal, and the bit line when the expected value signal is at a high level. While the signal is detected through one of the bit lines selected by the selection circuit, when the expected value signal is at a low level, the signal is detected through the other bit line selected by the bit line selection circuit. An output determination circuit that outputs a signal indicating a match or mismatch between the output signal and the expected value signal in accordance with the signal level is provided, so that one row can be tested in parallel,
Therefore, an operation test can be performed at high speed.

[Brief description of the drawings]

FIG. 1 shows a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a DRAM, FIG. 2 is a diagram showing the operation timing of the DRAM, FIGS. 3, 4, and 5 are diagrams each showing a state where a memory cell is connected to a bit line, and FIG. FIG. 7 is a diagram showing a test circuit of a DRAM according to a second embodiment of the invention, FIG. 7 is a diagram showing operation timing of the test circuit, FIG. 8 is a diagram showing an example in which a part of the test circuit is modified, and FIG. Figure, No.
FIG. 10 shows a one-row parallel writing circuit. 1 ... line data storage circuit, 2 ... bit line selection circuit, 3 ... output determination circuit, 4 ... memory cell array, 5
…… Sense amplifier array, 41,42 …… Memory cells, 51,52
… Sense amplifier, 101 expected value generation circuit, 102 data signal selection circuit, 103 to 108 inverter, 109…
P-type MOS transistor, 110 to 114 N-type MOS transistor, 115, 116 NAND gate, B, B #, BL, BL # bit line, S output signal line, fail signal line, WL …
Word line.

Claims (1)

(57) [Claims] 1. A semiconductor memory device capable of writing and reading the same data to and from a plurality of memory cells in parallel via a pair of bit lines operating in a complementary manner, and representing data written to a specific memory cell. A line data storage circuit that outputs an expected value signal via a bit line connected to the memory cell, a signal based on write data to the specific memory cell, or the expected value signal from the line data storage circuit, A bit line selection circuit that receives as an input signal and selects one or the other bit line out of a pair of bit lines of a memory cell other than the memory cell according to the level of the input signal; A potential supply circuit for applying a preset predetermined potential to the line; and a potential supply circuit based on a signal based on data written to the specific memory cell. By selecting a bit line by a bit line selection circuit and supplying a predetermined potential by the potential supply circuit, the same data as the expected value signal written to the other memory cells in parallel with the specific memory cell is written. An output signal to be represented is detected via one of the bit lines selected by the bit line selection circuit when the expected value signal is at a high level, and is detected by the bit line selection circuit when the expected value signal is at a low level. An output determination circuit for detecting via the other selected bit line and outputting a signal indicating a match or mismatch between the output signal and the expected value signal in accordance with the level of the detected output signal; A semiconductor memory device characterized by the above-mentioned.