JP2704935B2 - Processor with test function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor, and more particularly to a processor for general-purpose equipment requiring a test function.

[0002]

2. Description of the Related Art As is well known, a test (test) of a processor such as a logic LSI includes a DC characteristic test (DC parametric test), an AC characteristic test (AC parametric test), and a function test (functional test).
There are three types. Testing of such processors is performed at each stage of design, manufacture, shipping, and acceptance.

In the DC characteristic test, characteristics such as input, output, input / output transmission, total current, and power consumption are measured. In the AC characteristics test, rise and fall times of input / output waveforms, propagation delay time between input / output terminals, setup time, hold time, minimum clock pulse width, operating frequency, and the like are measured. The function test is a test that is performed to confirm whether or not the processor operates without showing an abnormality in a function when a specified operating condition is given to the processor.

[0004] Among them, a particularly important test is a function test. Functional tests include test pattern accumulation, mounting test,
Four types of methods are known, the comparative test method and the self test method. In the test pattern storage method, an input test pattern and an expected output pattern are created in advance and stored in a memory of a test apparatus such as an LSI tester. At the time of the test, the input test pattern is applied to the processor as the device under test, and the quality of the device under test is determined by comparing the output pattern from the device under test with the accumulated expected output pattern. The mounting test method is a test in which a device under test is mounted on a system to which the device is applied, the system is actually operated, and the quality of the device under test is determined based on the quality of the system. In the comparative test method, the same input test pattern is simultaneously applied to the device under test and the non-defective processor for comparison, and the output pattern from the device under test is compared with the expected output pattern from the non-defective processor. Is determined. The self test method is a test method in which the generation of an input test pattern and the determination of a test result or the compression of an output pattern are executed by the processor itself.

[0005] Among the above functional tests, the mounting test method does not require a tester (tester), is relatively easy and economical, and is mainly used for acceptance inspection by a user (user). Can be Next, the mounting test method will be described in some detail.

First, a microcomputer board which is confirmed to be all good is prepared. Here, on the microcomputer board, ROM, RAM, I / O interface and other circuits are mounted as peripheral circuits (external circuits). A processor as a device under test is inserted into this microcomputer board. Next,
An external circuit controls the processor to enter a test mode. The microcomputer board is caused to actually execute a prepared test program. Here, the test program combines various instructions and operands so that a defect in an internal circuit of the processor can be detected. The external circuit converts the data format of the execution result of the program into a data format that can be easily confirmed by the external circuit. The execution result converted into the data format is output to an external output device (display device or printing device) via the general-purpose input / output port. The user determines the quality of the processor under test based on whether the test program is correctly executed by looking at the execution result output to the output device.

As described above, in the mounting test method at the time of the acceptance inspection, the operation of the internal circuit of the processor is checked according to many procedures.

[0008]

As described above, in the conventional processor test method (mounting test method) by executing a test program, the procedure is many, and the operation of all resources of the internal circuit constituting the processor is confirmed. Can not do.
Therefore, even if there is a defect in any of the internal circuits of the processor, it has been extremely difficult to confirm an appropriate part.

Further, in the mounting test method, there is a complicated timing constraint in changing the mode from the test mode to the normal operation mode or in the mode from the normal operation mode to the test mode, and there is also a command limitation in restarting the program.

Therefore, an object of the present invention is to reduce restrictions when changing the operation mode, and to stop and restart the program without restriction.
It is an object of the present invention to provide a processor with a test function that can efficiently and accurately check the operation of all resources of an internal circuit constituting a processor from an external circuit.

Another object of the present invention is to provide a processor with a test function capable of immediately specifying a defective portion even if the internal circuit of the processor has a defective portion.

[0012]

According to the present invention, there is provided a processor having a test function according to the present invention, wherein a processor including a plurality of internal circuits connected to each other by an internal bus responds to a stop signal supplied from an external circuit. An operation mode switching circuit that switches an operation mode to one of a test mode and an actual operation mode; and a test bus that is used in the test mode and is connectable to the external circuit. When the processor is switched to the test mode by the mode switching circuit, the processor has a means for communicatively connecting the own circuit and the test bus.

In the above processor with a test function,
The operation mode switching circuit responds to a resource selection signal supplied from the external circuit, and sends a selection signal for selecting one resource in a specific internal circuit among the plurality of internal circuits to the specific internal circuit. Preferably, the specific internal circuit includes means for selecting, in response to the selection signal, the one resource to be connected to the test bus.

[0014]

In the test mode, all resources are released to the user so that the state of all resources of the plurality of internal circuits of the processor can be confirmed by the external circuit. In addition, since one resource of a specific internal circuit can be selected by the resource selection signal, even if there is a defect in the internal circuit of the processor, the defect can be immediately specified.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, a processor 2 with a test function according to one embodiment of the present invention includes an external circuit 1, a test bus 3, a memory address line 4, a halt (HALT) signal line 5, and a write (WR) signal. It is connected by a line 6, a read (RD) signal line 7, and a resource selection signal line 8.

The processor with test function 2 includes, as its internal circuits, an operation mode switching circuit 9, a test mode control line 10, a memory unit 11, and a register unit 12.
, An operation unit 13, a control unit 14, and an internal bus 15. The operation mode switching circuit 9 outputs a test mode control signal to the memory unit 11, the register unit 12, the arithmetic unit 13, and the control unit 14 via a test mode control line 10 as described later. Memory unit 11, register unit 1
2, the operation unit 13 and the control unit 14 are connected to each other via an internal bus 15. Further, the memory unit 11, the register unit 12, the operation unit 13, and the control unit 14 are connected to the test bus 3.

The memory section 11 is divided into three or four memory blocks, and has a program memory for storing programs and a data memory for storing data. In the present embodiment, the register section 12 includes 16 registers as described later. The operation unit 13 includes an arithmetic logic unit (AL
U), an adder / subtractor, a multiplier and the like. The control unit 14 is a part that fetches and decodes instructions, and includes a program counter (not shown).

As is well known in the art, when a stop signal of logic "0" level is sent from the stop signal line 5, the processor 2 stops its operation. More specifically, the program counter in the control unit 14 is stopped, whereby the processor 2 stops the execution of the program being executed at that time. Accordingly, the processor 2 holds the state of the internal circuit in a state where the currently executed instruction is completed.

In the present invention, this stop signal is used to switch the processor 2 to the "test mode" or the "actual operation mode". More specifically, in response to the stop signal, the operation mode switching circuit 9 switches the operation mode of the processor 2 between the “test mode” and the “actual operation mode”. When the stop signal indicates the logic “0” level, the operation mode switching circuit 9 switches the operation mode of the processor 2 from “actual operation mode” to “test mode”. When the stop signal is at the logic “0” level, the operation mode switching circuit 9 switches the operation mode of the processor 2 from “actual operation mode” to “test mode”. In the "test mode", the processor 2 not only stops its operation as in the case of receiving the normal stop signal, but also releases all resources inside the processor 2 to the user as described later. As a result, the processor 2 enters a state where all the internal resources can be convinced by the external circuit 1.

The processor 2 has 200 or more circuits as internal resources. Therefore, 8 bits are required to specify the internal resources. The operation mode switching circuit 9 receives an 8-bit resource selection signal from the external circuit 1 via the resource selection signal line 8. In response to the 8-bit resource selection signal, the operation mode switching circuit 9 selects one of the internal resources and writes or reads data to or from the internal resources as described later. When writing data to the selected internal resource, the external circuit 1 sends a write signal of logic “0” level to the processor 2 from the write signal line 6. At this time, the test data transmitted from the test bus 3 is written to the selected internal resource. On the other hand, when data is to be read from the selected internal resource, the external circuit 1 sends a read signal of logic “0” level to the processor 2 from the read signal line 7. At this time, data stored on the test bus 3 is read from the selected internal resource.

When a resource selection signal for selecting the memory section 11 is transmitted from the external circuit 1 via the resource selection signal line 8, the operation mode switching circuit 9 causes the memory section 11 to operate.
And makes the memory address line 4 valid. Thus, the external circuit 1 can directly specify the address of the memory unit 11.

In the present embodiment, the external circuit 1 is constituted by a one-chip CPU for control. However, the present invention is not limited to such a constitution, and at least data can be transmitted and received via the test bus 3. An address can be transmitted through the memory address line 4, a stop signal can be transmitted through the stop signal line 5, a write signal and a read signal can be transmitted through the write signal line 6 and the read signal line 7, and a resource selection signal line can be transmitted. 8
Any configuration may be used as long as it has a function of transmitting a resource selection signal via the.

As described above, the operation mode switching circuit 9 includes the stop signal from the stop signal line 5, the write signal from the write signal line 6, the read signal from the read signal line 7, and the read signal from the resource select signal line 8. Based on the resource selection signal,
The test mode control line 1 is used for the resources of the memory unit 11, the register unit 12, the arithmetic unit 13, and the control unit 14.
0 controls the input and output of data to and from the test bus 3.

As described above, when the stop signal indicates the "test mode", the processor 2 releases its internal resources to the user. Explain whether resources are released.

Referring to FIG. 2, the register section 12 includes zero to fifteenth registers 12 ₀ , 12 ₁ ,..., 12 ₁₅ . In the drawing, the 0th to 15th registers 12 ₀ , 1
2 _1, ..., 12 _15, respectively GEG0, REG1, ...,
This is indicated by GEG15. The register unit 12 further includes:
It has an input selection circuit 121, an output selection circuit 122, and an output control circuit 123.

The input selection circuit 121 is connected to the test bus 3, the internal bus 15, and the zeroth to fifteenth registers 12 _{0 to} 12 _15.
Is connected between the inputs. Input selection circuit 1
21 is supplied with an input selection signal from the operation mode switching circuit 9 via the test mode control line 10. When the stop signal sent from the stop signal line 5 is at the logical "0" level, that is, when the "test mode" is instructed, the operation mode switching circuit 9 selects the data on the test bus 3 side as the input selection signal. Is output. In response to the input selection signal, the input selection circuit 121
Selects data on the test bus 3 and supplies the selected data to the zeroth to fifteenth registers 12 _{0 to} 12 ₁₅ . When the stop signal transmitted from the stop signal line 5 is at the logical "1" level, that is, when the "actual operation mode" is designated, the operation mode switching circuit 9 selects data on the internal bus 15 side as an input selection signal. Output a signal instructing this. In response to the input selection signal, the input selection circuit 121 selects data on the internal bus 15 and stores the selected data in the zeroth to fifteenth registers 12 ₀ to 12.
Supply 2 ₁₅

The output selection circuit 122 is connected between the outputs of the _zeroth to _fifteenth registers 12 _{0 to} 12 ₁₅ and the output control circuit 123. The output selection circuit 122 is supplied with a register selection signal from the operation mode switching circuit 9 via the test mode control line 10. The resource selection signal supplied from the external circuit 1 via the resource selection signal line 8 is transmitted to the _0th to 15th registers 12 ₀ to 1 in the register section 12.
When instructing to select one of 2 ₁₅ , the operation mode switching circuit 9 outputs a signal instructing to select the register selected by the resource selection signal as the register selection signal. In response to this register selection signal, the output selection circuit 122 outputs the 0th to 15th registers 12 _{0 to} 12
_{One of the 15} is selected, and the data stored in the selected register is supplied to the output control circuit 123.

The output control circuit 123 is an output selection circuit 122
And the test bus 3 and the internal bus 15. Further, an output selection signal is supplied to the output control circuit 123 from the operation mode switching circuit 9 via the test mode control line 10. This output selection signal is the same as the input selection signal. Therefore, when the output selection signal indicates that the test bus 3 is to be selected, the output control circuit 123 sends the data selected by the output selection circuit 122 to the test bus 3. When the output selection signal indicates that the internal bus 15 is to be selected, the output control circuit 123
Represents the data selected by the output selection circuit 122 on the internal bus 15
Send to

As described above, the stop signal is set to the "test mode".
, The register unit 12 is connected to the test bus 3 under the control of the operation mode switching circuit 9 and can transmit and receive data on the test bus 3. Therefore, the 0th to 15th registers 12 ₀ constituting the register section 12
12 ₁₅ is opened to the user.

Like the register section 12, the memory section 11,
The resources of the operation unit 13 and the control unit 14 are also released to the user under the control of the operation mode switching circuit 9 when the stop signal indicates the “test mode”.

Next, the operation of the operation mode switching circuit 9 will be described with reference to FIG. When the processor 2 is started, the operation mode switching circuit 9 sets the stop signal supplied from the external circuit 1 via the stop signal line 5 to logic “0”.
It is determined whether the level is the level or the logic "1" level (step S1). When the stop signal indicates the logic “1” level (N in step S1), the operation mode switching circuit 9 determines that the operation mode of the processor 2 is the “actual operation mode” and causes the processor 2 to perform a normal operation (step S2). ). That is, the operation mode switching circuit 9 sends the internal bus 1 to the memory unit 11, the register unit 12, the arithmetic unit 13, and the control unit 14 via the test mode control line 10.
5 is connected. The control unit 14 decodes the instruction, controls each resource, and causes the memory unit 11, the register unit 12, the operation unit 13, and the control unit 14 to exchange data via the internal bus 15.

When the stop signal indicates a logic "0" level (Y in step S1), the operation mode switching circuit 9 determines which internal resources are transmitted by the resource selection signal supplied from the external circuit 1 through the resource selection signal line 5. Determine if you have selected.

That is, the resource selection signal is transmitted to the register 12
(Y in step S3), the operation mode switching circuit 9 releases each resource of the register unit 12 to the user as described above, and enables the test of the register unit 12. When the resource selection signal indicates the memory unit 11 (Y in step S4), the operation mode switching circuit 9 releases each resource of the memory unit 11 to the user, and
2 is possible. When the resource selection signal indicates the operation unit 13 (Y in step S5), the operation mode switching circuit 9 releases each resource of the operation unit 13 to the user and enables the operation unit 13 to test. When the resource selection signal indicates the control unit 14 (Y in step S6),
The operation mode switching circuit 9 releases each resource of the control unit 14 to the user, and enables the test of the control unit 14.

Next, a test operation in the register section 12 will be described. The operation mode switching circuit 9 outputs the resource selection signal to the 0th to 15th registers 12
It is determined which of _{0 to} 12 ₁₅ is instructed to select (steps S7, S8, S9). The operation mode switching circuit 9 performs write / read processing of the selected register (steps S10, S11, S12).

The write / read processing of the register will be described below with reference to FIGS. here,
The resource selection signal is sent to the 0th register 12 in the register section 12
And instructs the selection of ₀ (Y in step S7), and the write / read process of the register 12 ₀ of the 0 (step S1
The case where (0) is performed will be described as an example.

[0037] First, the operation when writing test data is described in the register 12 ₀ of the 0. Here, the 0th
Register 12 ₀ is 16-bit registers, and a FFFF (H) test data in hexadecimal.

The external circuit 1 has an FFFF on the test bus 3.
The test data representing (H) is transmitted. Next, the external circuit 1 sends out a write signal of logic “0” level on the write signal line 6. In response to this write signal, the operation mode switching circuit 9 sets the 0th register 12 ₀
To write test data. That is, test bus 3
Test data representing FFFF (H) above is written into the register 12 ₀ of the 0th through the input selection circuit 121.

Next, the operation of reading the test data stored therein from the register 12 ₀ of the 0.

The external circuit 1 sends out a read signal of logic "0" level on the read signal line 7. In response to the read signal, the operation mode switching circuit 9 operates the register unit 1
To read out data stored therein from the 0th register 12 _0-2. That is, data stored in the register 12 ₀ of the zeroth order is sent via the output selection circuit 122 and the output control circuit 123 to test bus 3. The data on the test bus 3 is read into the external circuit 1.

[0041] Thus, if the test data written in the register 12 ₀ of the 0th and data read from the register 12 ₀ of the 0 match, that the external circuits 1 registers 12 ₀ of the 0 is normal You can check. On the other hand, when these data do not match, the external circuit 1 determines that the 0th register ₁₂₀ has failed, and uses an output device such as a display device or a printing device to notify the user of the fact.

The present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the spirit of the present invention.

[0043]

As described above, according to the present invention, there are few restrictions when changing the operation mode, and the program can be stopped and restarted without any restrictions. In addition, since data can be written to and read from each resource of the processor from an external circuit, there is an effect that a defective portion can be easily specified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a processor with a test function according to an embodiment of the present invention in a state where it is connected to an external circuit.

FIG. 2 is a block diagram illustrating a configuration of a register unit used in the processor with a test function illustrated in FIG. 1;

FIG. 3 is a flowchart illustrating an operation of an operation mode switching circuit used in the processor with a test function illustrated in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 External circuit 2 Processor with test function 3 Test bus 4 Memory address line 5 Stop signal line 6 Write signal line 7 Read signal line 8 Resource selection signal line 9 Operation mode switching circuit 10 Control line for test mode 11 Memory section 12 Register section 13 Operation unit 14 Control unit 15 Internal bus

Claims (2)

(57) [Claims] In a processor including a plurality of internal circuits connected to each other by an internal bus, an operation mode of the processor is changed to one of a test mode and an actual operation mode in response to a stop signal supplied from an external circuit. An operation mode switching circuit for switching to the test mode, and a test bus used in the test mode and connectable to the external circuit. Each of the plurality of internal circuits switches the processor to the test mode by the operation mode switching circuit. A processor having a test function, wherein the processor has a means for communicatively connecting the own circuit and the test bus when the test bus is received. 2. A selection signal for selecting one resource in a specific internal circuit among the plurality of internal circuits in response to a resource selection signal supplied from the external circuit. To the specific internal circuit, wherein the specific internal circuit includes a selection means for selecting the one resource to be connected to the test bus in response to the selection signal. Item 2. A processor with a test function according to item 1.