JP2703884B2 - Data write control method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data write control method for a register in a data processing device that processes a plurality of data having different bit lengths. [Related Art] In a data processing device, the length of data to be handled is not always one type. For example, when handling English character codes and short integers, a length of at most 8 bits is sufficient (hereinafter, data having a length of 8 bits is referred to as byte data), and kanji character codes and short integers are handled. In such a case, data having a length of 16 bits is called half word data.) Further, when dealing with even larger integers and floating point numbers, a length of 32 bits or more is required (hereinafter, data having a length of 32 bits is called word data). The correspondence between the behavior of data and the bit length of data is called a data type. FIG. 3 shows the configuration of a typical data processing device. The data is usually stored in a register 104 in a storage device 101 or a central processing unit (hereinafter referred to as a processor) 102. After the data arranged in the storage device 101 is once taken into the register 104, it is subjected to processing such as calculation and transfer. In general, one register can store data belonging to a plurality of different data types. For example, a register having a 32-bit width is shown in FIG.
As shown in (B) and (C), byte data 201,
The position of the least significant bit (LSB) is aligned so that half word data 202 and word data 203 can be stored. Also, a single register may not be used for the same data type during the execution of a program. At some point it may be used as a byte type and at some point as a word type. For example, the length of the register for word data is long enough to store four bytes of data. For this reason, registers are often used to store data of a plurality of shorter data types. FIGS. 5A and 5B show the storage of four byte data and two half word data of a register having a 32-bit width. As described above, when storing a plurality of data in one register, when rewriting only one of the plurality of data, if only the part corresponding to the data type is not changed, other data parts in the register will also be At the same time, the data is rewritten, and the data in a portion unrelated to the transfer in the register cannot be guaranteed. In order to avoid the above inconvenience, it is common to change only bits in a necessary range according to a designated data type in writing to a register. Such a function of changing only a series of bit strings of data is called a partial write function. FIG. 6 shows a conventional example of a 32-bit register having a partial write function of lower 8, 16 or 32 bits depending on the data type. The 32-bit register 401 is connected to the data bus 403 via the 32-bit data buffer 402,
The contents are output by 414. The write signal 410 writes only the lower 8 bits (bit numbers 0 to 7) of the data bus, and 411 denotes the next lower 8 bits (bit numbers 8 to 1).
5) is written, and 412 is the upper 16 bits (bit numbers 16 to 3).
This is a signal that rewrites 1). The 2-bit signal 415 indicating the type of the data type indicates the bit width to be transferred to the register, and is represented by 00b (b
Indicates a binary number) indicates byte data, 01b
Means half word data and 10b means word data. The write signal 413 is a control signal designating that data is written to this register. The write control circuit 404 controls such that when the write signal 413 becomes active, the data type signal 415 becomes 410b when the data type signal 415 is 00b, 410 and 411 when it is 01b, and 410, 411 and 412 when it is 10b. Is what you do. In the above conventional example, three write signals (410, 411 and 412) are required for one register in order to write data belonging to three types of data, and a unique write control circuit is required. 404 is required. As the number of registers increases and the types of data types increase, the number of control signals and control circuits described above relatively increases. When a register with a partial write function is mounted on a printed circuit board using an IC package, the number of control signals is large and the amount of wiring increases significantly compared to the case where the same amount of registers are configured without the partial write function. However, there is a disadvantage in that a large number of packages are required and the mounting area is increased due to the complexity of the configuration of one register and the limitation of the number of pins of the IC package. In addition, even when a register having a partial write function is implemented in an LSI, a mask pattern (having a function of configuring each bit of the register) constituting a unit register (having a function of configuring each bit of the register) is compared with a register without a partial write function. In addition to the complexity of the geometrical arrangement that determines the transistors and wiring in the LSI, the extra control signals traverse the mask pattern, which increases the mounting area of the register. [Problems to be solved by the invention] In view of the disadvantages of the conventional example, the present invention
In a data processing device having a register for storing data belonging to a type, an object of the present invention is to provide a partial write function by a register capable of writing with one kind of bit width. [Means for Solving the Problems] A data write control method according to the present invention is provided in a data processing apparatus and stores a plurality of types of data having different bit lengths for temporary storage of operand data. When writing data having a bit length shorter than the bit length of the register as an operation result to the register of the register, in a data writing method of writing data without changing the contents other than the specified bit, The data of the register is held in a holding unit, and data from an arithmetic unit, which is to be written to the one register, is transferred, and is generated based on an instruction code indicating a bit length of the data to be written. In response to a control input signal, the data to be written and the held data are synthesized by synthesizing means. Synthesized data in which the least significant bit of data to be rared is always set as a restart bit is generated, and the synthesized data is written to the one register. [Operation and Principle of the Invention] When writing data to a register, the data immediately before the register designated to be written is read and stored, and after combining the stored data with the write data (blocking), By writing the write to the designated register, it is ensured that the portion that must not be rewritten to the designated register does not change as a result. Embodiment Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing one embodiment of the present invention. Register file 501 contains 32 32-bit wide registers 600 to
It is composed of 631. The input of each register is 32-bit 2
Connected to the input multiplexer 502, the contents of the output of the multiplexer 502 are written by write signals 632-663 for each register. On the other hand, the output of each register is connected to a 32-bit data bus 504 via output buffers 700 to 731 of each register, and is read out to the data bus 504 by read signals 732 to 763 for each register. The blocking register 503 is connected to the data bus 504, and the destination operand register 505
Is a 32-bit latch that latches the contents of the data bus with a write signal 512 when transferring the contents of the data bus 504 (destination data) to the ALU. It is connected between the buses 504 and has a function of combining the output of the blocking register 503 and all or part of the 32 bits of the data bus 504. Also multiplexer 50
2 has a 2-bit control input 511, and the content of the blocking register 503 and the data
The contents of the bus 504 are synthesized as follows. When the control input is 00b, the data written from the data bus is 8 bits, indicating that the upper 24 bits of the register must not change. The lower 8 bits of the output have a data bus
The lower 8 bits of the 504 are selected, and the upper 24 bits of the contents of the blocking register 503 are selected as the upper 24 bits of the output. When the control input is 01b, the data written from the data bus is 16 bits, indicating that the upper 16 bits of the register must not change. The lower 16 bits of the output have a data bus
The lower 16 bits of 504 are selected, and the upper 16 bits of the output are selected as the upper 16 bits of the contents of the blocking register 503. When the control input is 10b, the data written from the data bus is 32 bits, and the contents of the register indicate that the entire 32 bits change. The 32 bits of output include 32 on data bus 504.
The bits are output as is. The ALU 507 is a 32-bit arithmetic logic unit that has a source operand register 506 connected to the data bus.
An arithmetic operation represented by addition or a logical operation represented by AND is performed on the contents of the destination operand register 505 and the contents of the destination operand register 505 in accordance with the designation of the operation designation signal 514. The operation result is output to the data bus 504 via the 32-bit output buffer 508 connected to the data bus when the read signal 515 becomes active. The source operand register 506 and the destination operand register 505 are both 32-bit registers, are connected to the data bus 504, and temporarily hold data for two-operand operation in the ALU 507.
Write signals 512 and 513 are the respective write signals to destination operand register 505 and source operand register 506. Generally, a two-operand operation instruction is executed as follows. Register 600 specified as source operand
The contents of .about.631 are transferred to the source operand register 506 via the data bus 504. The contents of the registers 600 to 631 specified as the destination operand are transferred to the destination operand register 505 via the data bus 504 and to the blocking register 503. The ALU 507 performs an operation on the contents of the source operand register 506 and the contents of the destination operand 505. The operation result is transferred from the output buffer 508 of the ALU to the data bus.
Put on 504. According to the contents of the control input signal 511, the data bus 504
And the contents of the blocking register 503 are synthesized,
Write to registers 600 to 631 specified as destination operands. Next, the operation will be described with reference to an example. Now register
It is assumed that the value stored in the register 615 is 66666666h (123 indicates a hexadecimal number). It is assumed that ADDBR0 and R15 are to be executed as instructions. This instruction means that the 8-bit data stored in the register 600 is added to the 8-bit data stored in the register 615, and the obtained result is transferred to the register 15 (615). In both the registers 600 and 615, the data involved in the addition is only the lower 8 bits (78h for 600, 66h for 615), so that the content of the register 600 is finally 123456DEh (78
h + 66h = 0DEh) is obtained (see FIG. 7 (A)). First, the contents 6666666h of the register 615 are transferred to the source operand register 506 via the data bus 505. Next, the contents of register 600 are stored in data bus 50.
4 to the destination operand register 505 and the blocking register 5
Transferred to 03. Since the ALU507 always performs calculations with a 32-bit width, the output of the ALU507 is 789ABCDEh (12345
678h + 66666666h). The operation result (789ABCDEh) reaches the multiplexer 502 via the data bus 504. Byte type is specified as data type (control input 511 is 00h)
Therefore, the lower 8 bits of the output of the multiplexer 502 are the lower 8 bits of the data bus 504, that is, 0DEh, and the upper 24 bits of the output of the multiplexer 502 are the upper 24 bits of the blocking register 503, that is, the destination operand as the destination operand. Upper 24 bits of 12345678h transferred to Nation Operand Register 505 12
3456h is output. Therefore, 32-bit data of 123456DEh is formed as the entire output of the multiplexer 502, and this value is written to the register 600. Similarly, the case where half word data is handled is when the addition instruction ADDHW R0, R15 for half word data is executed instead of the above ADDB instruction. Also in this case, the operation result (789ABCDEf) is output to the data bus 504.
Until output to, it is the same as for the byte data type. Since the half-word type is specified as the data type (control input 511 is 01h), the lower 16 bits of the output of the multiplexer 502 are assigned to the data bus 504.
Of the lower 16 bits of the multiplexer 502
As the output upper 16 bits, the upper 16 bits of the blocking register 503, that is, the upper 16 bits 1234h of 12345678h previously transferred to the destination operand register 505 as the destination operand are output. Therefore, 32-bit data of 1234BCDEh is formed as the entire output of the multiplexer 502, and this value is written to the register 600 (see FIG. 7B). When handling word data, add the above ADDB
Add instruction ADDWR to word data instead of instruction
0, when R15 is executed. Also in this case, the calculation result (789
ABCDEf) is the same as for the byte data type until it is output on the data bus 504. Word type is specified as the data type (control input 51
Since 1 is 10h), the 32-bit output of the multiplexer 502 is 32 bits of the data bus 504, that is, 32 bits of 789ACBDEh.
Bit data is formed, and this value is written to the register 600 (see FIG. 7C). FIG. 2 is a diagram showing another embodiment of the present invention. In the case of this embodiment, the input of the register file 501 is directly connected to the data bus 504 without passing through the multiplexer 502, and the contents of the data bus 504 are always written with the write signals 632 to 66.
3 writes the corresponding register. On the other hand, A
A 32-bit multiplexer 502 is connected between the output data buses 508 of the LU 507. As a substitute for the blocking register 503, a destination operand register 505 is used here. The output of destination operand register 505 is connected not only as an input to ALU 507, but also to multiplexer 502.
Connected as the other input. The multiplexer 502 has a 2-bit control input 511 as in the previous embodiment, and combines the contents of the destination operand register 505 and the output of the ALU 507 with this value as follows. When the control input is 00b, it indicates that the upper 24 bits of the register must not change. The lower 8 bits of the output are the lower 8 bits of the ALU507.
The upper 24 bits of the contents of the destination operand register 505 are selected as the upper 24 bits of the output. When the control input is 01b, this indicates that the upper 16 bits of the register must not change. The lower 16 bits of the output are the lower 16 bits of the ALU507.
The upper 16 bits of the contents of the destination operand register 505 are selected for the upper 16 dots of the output bit. When the control input is 10b, the contents of the register indicate that the entire 32 bits change. In the output 32 bits, the 32 bits of the ALU507 are output as they are. In this embodiment, since the blocking register 503 for the above embodiment is unnecessary, not only the hardware can be simplified, but also data other than the register file 501 can be used.
A partial write function can be provided to the register resources connected to the bus 504. 2 for realizing addition, subtraction, logical product, logical sum instruction, etc.
Operand operations always transfer the source and destination operands to the ALU,
No extra transfer is required to combine the destination data with the operation result. On the other hand, in the one-operand operation for realizing a logical negation or a two's complement instruction, etc., only the destination operand is usually transferred to the ALU. By the way, in an instruction that does not perform an operation in the ALU, for example, in a register-register data transfer instruction, it is not necessary to read the destination operand.
Either transfer the contents of the destination operand to the blocking register for data synthesis or
Alternatively, a partial write function can be realized by designating an ALU operation as a no operation (NOP) and performing a pseudo operation. Further, for instructions that are complex to execute, it is clear that these transfers have only negligible overhead in terms of overall processing. [Effect of the Invention] As described above, the partial write function of the register
Since it can be realized by using a register having only a single word length writing function, a register in a processor which handles data belonging to a plurality of data types can be realized on a printed circuit board with a small amount of hardware and a small amount of wiring. Therefore, high-density mounting is possible. Also, since the LSI can be realized with a small area, the area of the entire chip can be reduced, and the LSI can be manufactured at low cost and other useful functions can be realized within the same area.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a drawing showing a configuration of an embodiment of a processor using the present invention, FIG. 2 is a drawing showing a configuration of another embodiment of a processor using the present invention, FIG. 3 is a diagram showing a configuration of a typical information processing apparatus, and FIG. 4 is a diagram showing a storage format of data belonging to various data types in a register (A).
Is a byte type, (B) is a half word type,
5 (C) shows a word type, and FIG. 5 shows storing a plurality of data in one register. FIG. 5 (A) shows four byte data and FIG. 5 (B) shows two half word data. FIG. 6 shows how data is stored in registers each having a 32-bit width, FIG. 6 shows a configuration of a register having a partial write function corresponding to a plurality of data types, and FIG. 7 explains the operation of the present invention. It is a drawing. 101 storage device, 102 central processing unit, 103 bus 104, register 201 byte data 202
… Half word data, 203 …… Word data, 3
01 to 304: Byte data, 311 to 312: Half word data, 401: 32-bit register, 402: 32
Bit output buffer, 403 32-bit data bus, 404 Write control circuit, 404 Write control circuit
410: Write signal for lower 8 bits, 411: Write signal for middle 8 bits, 412: Write signal for upper 16 bits, 4
13 Write control signal, 414 Read control signal, 415
… Data type designation signal, 501… Register file, 502… 32-bit multiplexer, 503… Blocking register, 504… 32-bit data bus, 5
05 ... destination operand register, 50
6 ... source operand register, 507 ... 32 bits
ALU, 508: ALU output buffer, 511: Data type designation signal, 512: Destination operand register write signal, 513: Source operand
Register write signal, 514 ... ALU operation designation signal, 515 ...
… ALU operation result read signal, 600 to 631… 32 bit register, 632 to 663… Register write signal, 700 to 731
…… Register output buffer, 732 to 763 …… Register read signal

Claims (1)

(57) [Claims] For a plurality of registers provided in the data processing device and storing a plurality of types of data having different bit lengths for temporary storage of operand data, data having a bit length shorter than the bit length of the register is calculated. When writing as a result, in the data writing method of writing data without changing the contents other than the specified bit, the data of one specified register is held in the holding unit, and the data from the arithmetic unit is stored. The data to be written to the one register is transferred, and the data to be written and the held data are transmitted in response to a control input signal generated based on an instruction code indicating a bit length of the data to be written. Combining means for combining the least significant bits of the data to be written, wherein the least significant bits of the data to be written are always restart bits. Generates a data write control method and writes the combined data in said one register.