JP2702121B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly, to a structure of a memory cell of a dynamic semiconductor memory device. [Prior Art] Generally, a memory cell of a dynamic semiconductor memory device has a one-transistor / one-capacitor structure, and a capacitor stores a charge of about 250 fc in order to guarantee the accuracy of a memory operation. Designed to be possible. Typical structures of such a memory cell include a structure in which a lower electrode of a capacitor is formed in a plane on the surface of a substrate, a structure in which a capacitor electrode pair is formed in a two-layer structure to reduce the area occupied by a capacitor, and a semiconductor substrate. There is a type in which a groove is formed almost vertically and the surface of the groove is used as an electrode. [Problems to be Solved by the Invention] However, each of the above-described conventional capacitor structures has the following problems. First, in the structure in which the lower electrode of the capacitor is formed in a plane on the surface of the semiconductor substrate, a substrate area of at least 15 square microns is required to accumulate the electric charge of about 250 fc, so that one memory cell is occupied. There is a problem that the area is increased and the degree of integration of the memory cells is not improved. On the other hand, in a storage cell having a double-structured capacitor, although the area occupied by one storage cell can be reduced as compared with the above conventional example, a substrate area of about 8 square microns still needs to store a charge of about 250 fc. There is a problem in that the memory cells are consumed and the degree of integration of the memory cells cannot be sufficiently improved. On the other hand, when a trench-type capacitor is employed, the substrate area consumed by one storage cell is considerably reduced, but the trench must be formed almost perpendicularly from the surface of the semiconductor substrate, and such a trench must be formed. However, there is a problem that formation of the film involves manufacturing difficulties. Accordingly, it is an object of the present invention to provide a semiconductor memory device having a memory cell structure which can reduce the substrate occupation area per memory cell and is easy to manufacture. [Means for Solving the Problems] In a semiconductor memory device of the present invention, two switching transistors having a common drain are provided in one section of an element region surrounded by an element isolation region, and the switching transistor is in contact with a common drain region. A capacitor line formed by using substantially the entire inside of the element isolation region on an element region defined by the element isolation region on the interlayer insulating film covering the bit line. And a lower electrode of each capacitor is connected to a source of a corresponding transistor directly below via a contact hole, a capacitor insulating film and an upper electrode are formed so as to cover the lower electrode, and The capacitor has a shape in which the lateral capacitance component is larger than the planar capacitance component. [Operation of the Invention] In the storage cell of the semiconductor memory device according to the above configuration, Since sidewall capacity component by the side wall of the dimer is greater than the plane capacitance component, the total capacitance value of the capacitor body than twice than in the case of forming a planar capacitive element on the semiconductor substrate surface. In addition, since it is not necessary to form fine grooves almost vertically in the semiconductor substrate, the manufacturing process is also facilitated. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1 to 3 show the structure of a first embodiment of the present invention, and FIG. 1 shows the structure of a semiconductor memory device according to the first embodiment.
FIG. 2 is a plan view showing a memory cell for bits, and FIG.
FIG. 3 is a sectional view taken along the line BB 'of FIG. In the drawing, 1 is a semiconductor substrate, 2 is an isolation region, 3 is a diffusion layer of a conductivity type opposite to that of the substrate 1, 4 is a word line extending on the surface of the semiconductor substrate 1, and 5 is a word line. A bit line contact penetrating the insulating layer, 6 is a bit line common to the two-bit storage cells shown, and 7 is a bit line 6
An insulating film covering the insulating film; 8, a capacitor electrode contact penetrating the interlayer film 7 and the insulating film covering the word line 4; 9, a first capacitor formed on the interlayer film 7 and in contact with the capacitor electrode contact 8 The electrode 10 is a capacitive insulating film covering the first capacitive electrode 9, and the numeral 11 is a second capacitive electrode covering the capacitive insulating film 10. Therefore, two MOS transistors are formed on the surface of the substrate surrounded by the isolation region 2 while sharing one bit line diffusion layer.
The MOS transistor is connected to the first capacitor electrode 9 via the source / drain electrode capacitor electrode contact 8. In the memory cell having the above structure, if the cell area is 10 square microns and the capacitance insulating film is 10 nm thick silicon dioxide, the planar dimension of the capacitor becomes 2 × 2.5 square microns. One micron is enough. However, for a capacitor of such dimensions, about
30fF, 17fF capacitance in plane, total
47 fF, and information can be stored in the form of electric charges. Moreover, in the above embodiment, after forming the MOS transistor, in other words, after forming the memory cell and the peripheral circuit, the interlayer film 7 can be deposited and a capacitor can be formed thereon, so that the word line 5 and the bit If a heat-resistant material is used for the wire 6, ordinary polycrystalline silicon or silicon dioxide can be used for the capacitor electrode 9 and the capacitor insulating film 10. In this embodiment, the capacitor is made of tantalum oxide that cannot withstand high temperatures. (Ta
₂ O ₅ ) is used. FIG. 4 is a sectional view of a second embodiment of the present invention. In the second embodiment, a groove 12 is formed in the first capacitor electrode 9 of the same capacitor as in the first embodiment to increase the surface area of the capacitor. For example, the capacitance insulating film is made of silicon dioxide having a thickness of 10 nm, the plane size is set to 2 × 2 square microns, the height is set to 3 microns, the opening area of the groove 12 is set to 1 × 1 square microns, and the depth of the groove 12 is set to 2 Assuming a micron, the capacitance value when the groove 12 is not formed is 96 fF, but increases to 124 fF when the groove 12 is formed. [Effects of the Invention] As described above, the present invention forms a wiring connected to the above-mentioned transistor on a semiconductor substrate, an interlayer insulating film covering the wiring, and a capacitor formed on the interlayer insulating film. The capacitor has a shape such that the side surface capacitance component is larger than the plane capacitance component. Therefore, the capacitor is formed in a two-layer structure in addition to the case where the capacitor is planarly formed on the surface of the semiconductor substrate. The capacity value can be increased as compared to
Therefore, if capacitors having the same capacitance value are formed, the occupied area can be reduced, and the density of the memory cells can be improved. In addition, since it is not necessary to form fine grooves at precise positions, manufacturing is facilitated.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing the structure of a first embodiment of the present invention, FIG. 2 is a sectional view taken along line AA 'of FIG. 1, and FIG. FIG. 4 is a sectional view showing the structure of the second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 3 ... Diffusion layer, 4 ... Word line (wiring), 6 ... Bit line (wiring), 7 ... Interlayer film (interlayer insulating film), 9 ... First capacitance electrode, 10 …… Capacitive insulating film, 11 …… Second capacitive electrode.

Claims (1)

(57) [Claims] Two switching transistors having a common drain are provided in one section of an element region surrounded by an element isolation region, and a bit line in contact with a common drain region is wired, and the element on an interlayer insulating film covering the bit line is provided. Two capacitors formed using substantially the entire inside of the device isolation region on the device region defined by the isolation region are provided independently on each transistor, and the lower electrode of each capacitor is provided directly below the corresponding transistor. A capacitor insulating film and an upper electrode are formed so as to be connected to the source of the transistor via a contact hole, cover the lower electrode, and each capacitor has a shape in which a side capacitance component is larger than a plane capacitance component. A semiconductor memory device characterized in that: