JP2794401B2 - Method for manufacturing MOS transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor, and more particularly, to a pocket which can form a double shallow junction using an impurity-containing insulating film to prevent occurrence of crystal defects in a substrate due to ion implantation. The present invention relates to a method for manufacturing a MOS transistor having a structure.

[0002]

2. Description of the Related Art As the degree of integration of devices increases, punch-through and DIBL (Drain Induced Ba) have been developed.
channel effect, such as a lower lowering effect. In order to prevent such a short channel effect, n ⁻ adjacent to a low concentration source / drain region is used.
Alternatively, an LDD MOS transistor having a p ^- type pocket region has been proposed.

FIGS. 1A to 1D show a manufacturing process of an LDD MOS transistor having a conventional pocket region. As shown in FIG. 1A, a gate insulating film 12 and a gate 13 are sequentially formed on a silicon substrate 11 by a normal process.
Next, as shown in FIG. 1B, n
^The n-type impurity and the p ^- type impurity are successively ion-implanted into the substrate, and the ion-implanted impurity is activated by a heat treatment process, so that low-concentration n ^- type source / drain regions 14 and 15 having a double shallow junction are formed. And p ⁻ -type pocket regions 16 are respectively formed. At this time, low-concentration n ⁻ -type source / drain regions 14 and 15 having double shallow junctions are formed on both sides of the gate in the substrate, respectively, and p ⁻ -type pocket region 16 is formed.
Are respectively formed so as to surround the n ⁻ type source / drain regions 14 and 15. As shown in FIG. 1C, a CVD oxide film is deposited over the entire surface of the substrate, and the oxide film is etched by RIE to form sidewall spacers 17 on both sides of the gate 13. As shown in FIG. 1D, an n ⁺ -type impurity is ion-implanted into the substrate by using the side wall spacer 17 and the gate 13 as a mask, and the ion-implanted impurity is activated by a heat treatment step, so that a high-concentration n ⁺ -type source is formed. / Drain regions 18 and 19 are formed. Thus, an LDD MOS transistor having a pocket region is obtained.

[0004]

In the conventional method for manufacturing a MOS transistor, a normal ion implantation step or a gradient ion implantation step is performed to form a source / drain region and a pocket region. However, when such an ion implantation step is performed, a crystal defect occurs in a channel region or a junction portion of the silicon substrate, and this crystal defect acts as a leak source of the junction and degrades the characteristics of the source. there were.

SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem. A double shallow junction is formed by using an insulating film containing impurities having different diffusivities as a diffusion source, and the silicon is formed by ion implantation. It is an object of the present invention to provide a method of manufacturing a MOS transistor that can prevent occurrence of defects in a substrate.

[0006]

In order to achieve the above object, a method of manufacturing a MOS transistor according to the present invention includes a step of sequentially forming a gate and a gate insulating film on a first conductivity type substrate, and including the gate. Forming an insulating film containing two types of impurities having different diffusivities and conductivity types over the entire surface of the substrate, forming a cap insulating film on the insulating film containing the impurities, and a heat treatment step. Forming an impurity region of the second conductivity type and an impurity region of the first conductivity type surrounding the impurity region of the second conductivity type on the substrate on both sides of the gate; an insulating film containing the impurity and a cap insulating film; Forming side wall spacers on both sides of the gate by etching, and ion-implanting a second conductivity type impurity into the substrate to form a second conductivity type impurity region adjacent to the impurity region. Characterized in that it comprises a.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. 2 (A) to 2 (F) are manufacturing process diagrams of a MOS transistor having a pocket structure according to the embodiment of the present invention. A gate insulating film 22 and a gate 23 are sequentially formed on a silicon substrate 21 as shown in FIG. 2A, and have different diffusion degrees over the entire surface of the substrate on which the gate 23 is formed as shown in FIG. An insulating film 24 containing impurities is deposited to a thickness of 100 to 1000 mm, and a cap insulating film 25 is formed thereon as shown in FIG.
A VD oxide film is deposited to a thickness of 1000 °. Here, the insulating film 24 containing impurities having different diffusivities is a BAsSG film, and the BAsSG film 24 is made of AsH.
_4, SiH _4, B ₂ H ₆ or the like hydride gas, or As-
Vapor deposition is performed using an organic metal source such as (OR) ₄ , Si- (OR) ₄ , B- (OR) ₄ . Here, R means an alcohol group, that is, a hydrocarbon group CHx. Then, 900
When a heat treatment process is performed at a temperature of 10 ° C. for 10 to 30 minutes, a shallow junction of n ⁺ / p ⁻ is formed in the substrate on both sides of the gate as shown in FIG. Here, among the double shallow junctions, n ⁺ regions 26 and 27 respectively act as source / drain regions, and p ⁻ region 28 serves as a pocket region surrounding n ⁺ source / drain regions 26 and 27. Works.

As described above, the BAsSG film 24 is an oxide film containing As and B having different degrees of diffusion in the substrate. B has a degree of diffusion in the silicon substrate that is about 10 times larger than that of As and has a low segregation coefficient of B. Therefore, when heat treating the BAsSG film 24, in order compared to the order diffusion of As is larger about diffusion of B, n ⁺ / p as the ^- dual shallow junction consisting of is formed in the substrate .

FIG. 3 shows the doping profile of the BAsSG film. FIG. 3A shows the doping profile before the heat treatment, and FIG. 3B shows the doping profile after the heat treatment. In FIG. 3A, BAsSG
The concentrations of As and B contained in the film are 5 × 10 ²¹ atoms each.
Using the same concentration as s / cm ³ , the concentration of the substrate is 1.8 × 1
0 ¹⁵ atoms / cm ³ . FIG. 3B shows that when a BAsSG film is deposited on a substrate and then heat-treated, a double shallow junction of n ⁺ / p ⁻ is formed in the substrate. That is, the doping profile of B greatly changes as the heat treatment time changes during the heat treatment step, but in the case of As, it hardly changes regardless of the heat treatment time. FIG. 3 (B) is 900 ° C.
Boron doping profile when heat-treated for 30 minutes at 900 ° C., boron doping profile when heat-treated at 900 ° C. for 20 minutes,
Indicates boron doping profiles when heat-treated at 900 ° C. for 10 minutes.

When the concentration of boron contained in the BAsSG film is reduced, not only can the concentration and profile of B in the silicon substrate be kept low, but also the concentration of As and B and the diffusion time can be adjusted to obtain n ⁺ / p ^- it is easy to adjust the dual junction concentration profile of the.

After performing the heat treatment step, the CVD oxide film 25 and the BAsSG film 24 are anisotropically etched as shown in FIG.
A side wall spacer 29 made of the SG film 24 is formed. After forming the side wall spacer, the gate 23 and the side wall spacer 29 are formed.
As a mask, As ions of 5 × 10 ¹⁵ atoms / cm ³ are implanted into the substrate at an energy of 40 keV, and 850
By performing a heat treatment step at a temperature of 30 ° C. for 30 minutes, n + type high concentration source / drain regions 30 and 31 are formed. Thus, a transistor having a pocket structure is obtained.

In the above embodiment, an n ⁺ / p ⁻ double junction is formed using an oxide film containing As and B.
(Or In) and n ⁺ / p ⁻ using an oxide film containing P
Can be formed.

[0013]

According to the present invention, since a double shallow junction is formed by using an oxide film containing impurities as a diffusion source without performing an ion implantation step, the occurrence of defects in the silicon substrate due to the ion implantation step is prevented. There is an advantage that the characteristics can be prevented from being reduced due to being eliminated. In addition, the method of manufacturing the MOS transistor simplifies the process by forming the sidewall spacer without using a separate deposition process by using the insulating film and the cap insulating film used as the diffusion source as the material for the sidewall spacer. Can be planned.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a conventional MOS transistor.

FIG. 2 is a manufacturing process diagram of the MOS transistor according to the embodiment of the present invention;

FIG. 3 is a diagram illustrating a doping profile of a BAsSG film.

[Explanation of symbols]

21 ... silicon substrate, 22 ... gate insulating film, 23 ... gate, 24 ... oxide film containing impurities, 25 ... CVD oxide film, 29 ... sidewall spacer 26 and 27 low-concentration n ^- -type source / drain regions, 28: low-concentration p ^- type pocket region, 30, 31 ... high-concentration n ⁺ -type source / drain region.

Claims (6)

(57) [Claims] A step of sequentially forming a gate insulating film and a gate on a substrate of a first conductivity type; and an insulating step in which two types of impurities having different diffusivities and conductivity types are contained over the entire surface of the substrate including the gate. A step of forming a film, a step of forming a cap insulating film on the insulating film containing impurities, and a heat treatment step of forming a second conductive type impurity region and a second conductive type impurity region.
Forming a first conductivity type impurity region surrounding the conductivity type impurity region on both sides of the gate of the substrate; etching the impurity-containing insulating film and the cap insulating film to form sidewall spacers on both sides of the gate; Forming an impurity region of the second conductivity type by ion-implanting an impurity of the second conductivity type into the substrate to form an impurity region of the second conductivity type adjacent to the impurity region. Method. 2. The method according to claim 1, wherein the insulating film is an oxide film containing impurities. 3. The insulating film is made of BAsS containing As and B.
3. The method according to claim 2, wherein the film is a G film. 4. When the insulating film is BAsSG, BAsS
The G film is made of a hydride gas such as AsH4, SiH4, B2H6, or As- (OR) 4, Si- (OR) 4, B-
4. The method according to claim 3, wherein the deposition is performed using an organic metal source such as (OR) 4 (where R is an alcohol group). 5. The method according to claim 1, wherein the impurity contained in the oxide film is Ga
3. The method for manufacturing a MOS transistor according to claim 2, wherein P and In or P and In are P. 6. The thickness of the insulating film containing impurities is 10
2. The method according to claim 1, wherein the angle is 0 to 1000 degrees.