JP2792486B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a structure of a DRAM (Dynamic Random Access Memory) for suppressing an increase in current consumption with an increase in memory capacity. The present invention also relates to a DRAM suitable as a memory for replacing a hard disk.

[0002]

2. Description of the Related Art In a portable personal computer or the like, since power is supplied from a battery, reduction of power consumption is a major technical problem. Conventionally, power management (power management) of a hard disk drive and a method of securing a virtual disk drive on a main memory have been used as measures for reducing power consumption.

In power management of a hard disk drive, when access to a hard disk does not exist for a certain period of time, the power consumption of a motor of the hard disk drive is controlled to be turned off to reduce current consumption.

In a method of securing a virtual disk drive in the main memory, a power supply of the hard disk is copied by copying a part of the contents of the hard disk to a predetermined area of the main memory after the power of the personal computer or the like is turned on. When the power is turned off and the power is turned off, the current consumption of the personal computer is reduced by writing back the contents of the virtual disk drive secured on the main memory to the hard disk.

[0005] A nonvolatile flash memory is sometimes used as a memory for partially replacing the hard disk as described above. However, the flash memory has a slow access time, so that the flash memory is more personal than the hard disk drive alone. Computer performance does not improve,
There is a problem that an increase in cost due to the use of the semiconductor memory for partially replacing the hard disk cannot be compensated.

As a countermeasure against this problem, a configuration for reducing the cost by specializing a DRAM (dynamic random access memory) having a faster access time for applications such as replacement of a hard disk has been proposed by the present inventor, Sugibayashi et al. Literature (1995 Digest
of International Solid-St
ate Circuit Symposium, No. 50
To 51).

FIG. 6 shows a configuration example of a memory system using a DRAM described in the above-mentioned document. Referring to FIG.
The memory system connected to 61 via a predetermined bus
It consists of a main memory 62, a hard disk drive (hard disk drive) 63, and a virtual disk drive 64,
The virtual disk drive 64 is composed of a DRAM.

The DRA of the virtual disk drive 64
M is driven by a battery, and its contents are backed up to the hard disk drive 63 before the power is turned off.

FIG. 7 shows the DRA of the virtual disk drive 64.
A memory map of the M memory space is shown in a block diagram. The DRAM is accessed in sector units, and 256 sectors constitute one cluster.

Then, a FAT (file allocation table) address (10 bits in FIG. 7) is allocated to the cluster, and a file allocation table (hereinafter, referred to as “FAT”) is secured in the memory, so that the memory is allocated via the FAT. To access. FIG.
In the memory configuration shown in (1), FAT address # 0 is allocated to a system cluster, FAT address # 1 is allocated to a FAT cluster, and FAT addresses # 2 to # 1023 are allocated to a data cluster.

Since a bad cluster can be registered in the FAT, generally, the DR of the virtual disk drive 64 is
It is also possible to use a memory that is defective in AM, and as a result, it is possible to reduce the cost of a system using this conventional DRAM.

FIG. 8 shows a DRAM configuration of the conventional virtual disk drive 64 shown in FIG.

Referring to FIG. 8, the DRAM includes a command input buffer 81 for outputting an address or a command input from a command pin 80 as an internal address signal or an internal command signal, a flag signal from a refresh timer 84 and an internal buffer. An arbiter 86 serving as an arbitration circuit for inputting a command signal, outputting a control signal (busy signal, operation mode signal), and realizing exclusive access to a memory between a CPU (not shown) and a refresh circuit; A refresh address counter 85 for generating a refresh target address (row address) every time; a row decoder, column decoder, memory cell array,
Memory main part 87 including sense amplifiers, etc., and memory main part
It comprises a data input / output buffer 89 for inputting and outputting data to and from a data pin 88 for writing and reading data to and from 87.

The DRAM shown in FIG. 8 has a self-refresh mode. When a flag signal is output from a refresh timer 84, an arbiter 86 outputs a busy signal to a status pin 82 via a status output buffer 83. The external input command is prohibited, and the address (row address) of the main memory portion 87 corresponding to the refresh address indicated by the refresh address counter 85 is refreshed. (For example, RAS
Only, a predetermined method such as CAS before RAS refresh is performed).

[0015]

However, in the above-mentioned conventional example using a DRAM for partially replacing a hard disk, the performance is improved by increasing the memory capacity, but the power consumption is increased, and the current consumption is reduced. Therefore, there is a problem that the effect of stopping the electric motor of the hard disk drive is reduced.

On the other hand, performing power management on a virtual disk drive using a DRAM requires data transfer again (that is, when power is turned off, the DR is not used).
Since the AM data is erased, the data is backed up and transferred to a hard disk or the like), and the performance of the virtual disk drive is greatly reduced.

Before the battery runs out, it is necessary to rewrite the contents of the virtual disk drive. However, there is a problem that the write-back time becomes longer as the memory capacity of the virtual disk drive increases.

SUMMARY OF THE INVENTION Accordingly, the present invention is to solve the above-mentioned problems of the prior art and to provide a semiconductor memory device which reduces current consumption without deteriorating system performance when using a DRAM as a partial replacement of a hard disk. With the goal.

[0019]

In order to achieve the above object, the present invention relates to a semiconductor memory device having a self-refresh mode, comprising a memory for a file allocation table and a register group attached to the file allocation table. A memory that has a value stored in a register associated with a file allocation table of the register group and a self-refresh operation mode signal and rewrites the value of the register, and that the file allocation table indicates according to the value of the register There is provided a semiconductor memory device which controls stop of self refresh of an area.

The present invention has a self-refresh mode, has a memory for a file allocation table, and has a first register group attached to the file allocation table.

The present invention has an operation mode for accessing a semiconductor memory device in units of clusters recorded in a file allocation table.

[0022]

The principle and operation of the present invention will be described below. According to the present invention, the first mode associated with the self-refresh operation mode signal and the file allocation table is provided.
When the value stored in the register is a predetermined value (= 0), the self refresh of the memory area indicated by the file allocation table is stopped. On the other hand, the value of the register corresponding to the self-refreshed memory area is decremented. In this way, the memory area that has not been accessed for a long time (the memory area whose register value has reached “0”) is not refreshed.

In the memory system using the semiconductor memory device of the present invention, when data is read from the memory area where the refresh is stopped, the data in the corresponding area is transferred from the hard disk drive.

In the present invention, the value of the register is set to a value indicating that writing has occurred in the corresponding memory area by the writing operation, and the memory area where the writing has been performed is not accessed for a long time. Refresh is performed so as to continue holding data.

Further, in the memory system using the semiconductor memory device of the present invention, only the written memory area is written back to the hard disk.

According to the present invention, when a mode for accessing the semiconductor memory device is provided in cluster units recorded in the file allocation table, the read operation sets a value indicating that the refresh of the corresponding memory area is completed. Is done.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. Referring to FIG. 1, a DRAM according to the present embodiment includes a command input buffer 11 that outputs an address or a command input from a command pin 10 as an internal address signal or an internal command signal, a flag signal from a refresh timer 14, Inputs internal command signal and outputs control signal (busy signal, operation mode signal)
An arbiter 16, which is an arbiter for realizing exclusive access to the memory between the CPU and the refresh circuit, and a refresh address counter 15, which generates an address to be refreshed (row address) at predetermined time intervals, are not available. A main memory unit 17 including the illustrated row decoder, column decoder, memory cell array, sense amplifier, and the like;
In addition to a data input / output buffer 19 for inputting and outputting data to and from the data pin 18 for writing and reading data to and from the main memory unit 17, an output of the refresh address counter 15 and an internal address signal are input, and an operation mode from the arbiter 16 is input. A FAT address decoder 20 which decodes one of the addresses based on the signal and outputs it as a FAT address, and a FAT address output from the FAT address decoder 20 are input, and a cluster address is output to the main memory unit 17, and the FAT address is output. Outputs the register value of a register group (first register group) corresponding to
SRAM (static random access memory) 21
And the register value from the FAT SRAM 21 and the arbiter 16
Arithmetic unit that receives a control signal (operation mode signal) from the CPU and outputs a refresh inhibit signal based on the result
It has 24. Then, the first computing unit 24 also writes the computation result to the first register 23.

The operation mode is input from the command pin 10 to the command input buffer 11. The address is multiplexed from command pin 10 to the command input buffer.
Entered in 11.

The arbiter 16 invalidates the command input by the flag signal from the refresh timer 14 during the self-refreshing operation, and outputs a busy signal from the status output buffer 13 to the status pin 12. This flag signal is reset by a reset signal from the main memory unit 17 after the self refresh operation ends.

As described above, in this embodiment, the FAT SRAM 21 including the file allocation table (FAT) 22 and the first register group 23 is incorporated, and the address input from the command pin 10 is stored in the command input buffer 11. The FAT address decoder 20 inputs the internal address signal (or refresh address) to the FAT address
Convert to FAT address, FAT address is SRAM for FAT
Entered in 21.

FIG. 2 is a configuration diagram of the FAT SRAM 21. Referring to FIG. 2, one word of SRAM 21 for FAT is
It consists of 10 bits for AT data (data for specifying a cluster address of a DRAM memory cell array) and 8 bits for data for refresh control, for a total of 18 bits, for a total of 1024 words (FAT address is # 0
To # 1023).

The data (refresh control data stored in the first register group 23) registered in the FAT memory is input to the first computing unit 24, and the first computing unit 24
Performs a predetermined operation, thereby outputting a refresh inhibition signal or the like to the memory main unit 17.

Next, an operation sequence of the DRAM according to the present embodiment will be described with reference to a flowchart. FIG.
5 is a flowchart showing an operation sequence of the DRAM according to the present embodiment in a self-refresh mode.

After the start of the self-refresh mode, the refresh address counter 15 increments (adds 1).
(Step 31), the refresh address counter 15
Refresh address from FAT address decoder
20 and the corresponding FAT address is derived (step 32).

The FAT address is input to the FAT SRAM 21. If the register value registered in the first register group 23 of the FAT SRAM 21 is "0" (see "0" in the judgment in step 33), Since the FAT (memory area of the memory main part 17 corresponding to the FAT address) that has expired has expired, the self-refresh mode ends without performing the self-refresh. That is, when the register value is “0” and the operation mode signal indicates the self-refresh operation mode, the first arithmetic unit 24 sets the refresh inhibit signal to active and does not refresh the corresponding memory area.

On the other hand, if the register value is other than "0" (see "other than" 0 "in the judgment of step 33), the self-refresh of the corresponding word line is performed, but the writing to the corresponding memory area has occurred. If the register value is a register value other than “FF” (hexadecimal display) indicating “(FF)” (see “other than“ FF ”in the determination in step 35), the register value corresponding to the FAT address of the first register group 23 is decremented ( 1 is subtracted) (step 36), and the time until the data in the corresponding memory area expires (the time until the register value is subtracted to become "0") is shortened.

FIG. 4 is a flowchart for explaining the operation in the write mode.

The FAT address of the data write area is derived (step 41), and after the write operation to the corresponding word line (step 42) is completed, the register corresponding to the FAT address of the first register group 23 of the FAT SRAM 21 is read. The value is set to "FF" (see step 43).

In the self-refresh mode,
Until the register value "FF" is detected and the data is written back to the hard disk, the refresh of the memory area of the FAT address whose register value is "FF" is continued.

Before the power is turned off, only the memory area in which the register value of the first register group 23 is "FF" is written back to the hard disk.

FIG. 5 is a flowchart for explaining the operation in the read mode. In FIG. 5, the FAT by the FAT address decoder 20 is obtained from the internal address signal.
The step of deriving the address is omitted.

When the memory area to be read has timed out,
If the value of the register corresponding to the FAT address of the first register group 23 of the FAT SRAM 21 is "0" (see "0" in the determination in step 51), data is read from the hard disk (see FIG. 5). See step 52).

On the other hand, when the register value is other than "0" (see "other than" 0 "in the judgment of step 51), the register value is set to" FE "(hexadecimal display). This is to extend the time-out due to the occurrence of the access (read access).

On the other hand, by inputting the data input from the data pin 18 to the data input / output buffer 19 to the first computing unit 24, the register value of the first register group 23 can be directly changed. This DRAM
Is used as the swap area of the main memory, it is possible to change the control so that a predetermined value is set in the register of the first register group 23 so that refresh is always performed but writing back to the hard disk is not performed. it can.

[0046]

As described above, according to the present invention,
When a DRAM is used to partially replace a hard disk, there is an effect that current consumption does not increase even if the memory capacity increases.

On the other hand, by performing power management on a virtual disk drive using a DRAM in cluster units, it is possible to avoid a significant decrease in the performance of the virtual disk drive even if data is transferred again. There is.

Before the battery runs out, it is necessary to rewrite the contents of the virtual disk drive. According to the present invention, only the necessary area is rewritten, so that the rewriting time is short. There is an advantage.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of an SRAM according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating an operation in a self-refresh mode according to an embodiment of the present invention.

FIG. 4 is a flowchart illustrating an operation in a write mode according to an embodiment of the present invention.

FIG. 5 is a flowchart illustrating an operation in a read mode according to an embodiment of the present invention.

FIG. 6 is a block diagram illustrating a memory system using a conventional virtual disk drive.

FIG. 7 is a diagram showing a memory configuration of a conventional virtual disk drive.

FIG. 8 is a diagram showing a configuration of a conventional virtual disk drive in a DRAM.

[Explanation of symbols]

 10 Command pin 11 Command input buffer 12 Status pin 13 Status output buffer 14 Refresh timer 15 Refresh address counter 16 Arbiter 17 Main memory 18 Data pin 19 Data input / output buffer 20 FAT address decoder 21 FAT SRAM 22 FAT 23 First register Group 24 first computing unit

Claims (9)

(57) [Claims] 1. A semiconductor memory device having a self-refresh mode, comprising: a memory for a file allocation table; and a group of registers attached to the file allocation table. A semiconductor memory, wherein the value of the register is rewritten by a stored value and a self-refresh operation mode signal, and a stop of self-refresh of a memory area indicated by the file allocation table is controlled in accordance with the value of the register. apparatus. 2. A memory system comprising the semiconductor memory device according to claim 1 for replacing at least a part of a hard disk, wherein said memory area is not accessed again for a long time without refreshing said memory area. A memory system for transferring data from the hard disk when an area is accessed. 3. The method according to claim 1, wherein the value of said register is set to a value indicating that writing has occurred in a corresponding memory area by a writing operation, and said memory area to which said writing has been performed has not been accessed for a long time. 2. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is controlled so as to keep retaining data. 4. A value of the register of the semiconductor memory device is set to a value indicating that writing has occurred in a corresponding memory area by a write operation, and the value of the register has been set for a long time with respect to the written memory area. 3. The memory system according to claim 2, wherein even when there is no access, the data is kept stored, and before the power supply is stopped, only the written memory area is written back to the hard disk. 5. An operation mode for accessing a semiconductor memory device in cluster units recorded in the file allocation table, and the contents of the register indicate that refresh of a corresponding area is completed by the read operation. 2. The method according to claim 1, wherein the value is set to a value.
13. The semiconductor memory device according to claim 1. 6. The semiconductor memory device according to claim 1, wherein said register group and said file allocation table are provided in the same static RAM. 7. The semiconductor memory device according to claim 1, wherein the register values of said register group are directly changed from outside, and the refresh of the corresponding memory area is controlled by the register values. 8. A semiconductor memory device having a self-refresh mode, wherein: a register group provided corresponding to an address for accessing a memory area unit of a predetermined size; and a register selected by the address from the register group. Circuit means for inputting a value of the operation mode signal and an operation mode signal, and outputting a signal for controlling inhibition of refresh operation of a memory area corresponding to the address. When the value of the register corresponding to is a predetermined value, a signal for inhibiting the refresh operation of the memory area corresponding to the address is set to the active state, and the value of the register is different from the predetermined value, and When the value is not a value indicating the write state of the corresponding memory area, the memory area is refreshed. The semiconductor memory device characterized by decreasing the value of the register upon shoe. 9. When data is written in a memory area corresponding to the address, the register value corresponding to the address is set to a predetermined value indicating a write state, and in a read operation, the register value corresponding to the address is set. When the value of the register is other than the value indicating the write state, the value of the register is set to a value smaller than the value indicating the write state and larger than a predetermined value prohibiting the refresh. 9. The semiconductor memory device according to claim 8, wherein: