JP2790010B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2790010B2 JP2790010B2 JP5203654A JP20365493A JP2790010B2 JP 2790010 B2 JP2790010 B2 JP 2790010B2 JP 5203654 A JP5203654 A JP 5203654A JP 20365493 A JP20365493 A JP 20365493A JP 2790010 B2 JP2790010 B2 JP 2790010B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating
- formation region
- etching
- element formation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Element Separation (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に絶縁分離溝の形成を含む半導体装置の製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including formation of an insulating isolation groove.
【0002】[0002]
【従来の技術】従来、半導体基板上の素子分離方法の一
つとして絶縁分離溝を形成する方法が用いられている。
図5(a)〜(c)、図6(d)〜(f)は、従来の半
導体装置の製造方法の一例を説明するために製造工程順
に示した半導体チップの断面図である。図5(a)に示
すように、P型半導体基板1上にN型エピタキシャル層
2を形成し、シリコン酸化膜3とシリコン窒化膜4を形
成した上で、半導体素子の絶縁分離のための絶縁分離溝
5を形成する。次に図5(b)に示すように、絶縁分離
溝5の底部にボロンをイオン注入して熱処理を行うこと
により、打ち込んだボロンをP型半導体基板1中に拡散
させ、PN接合による絶縁分離のためのP型拡散領域6
を形成する。その図5(c)に示すように、シリコン窒
化膜4およびシリコン酸化膜3を除去し、絶縁分離溝5
の内壁および素子形成領域上にシリコン酸化膜7および
シリコン窒化膜8を形成する。2. Description of the Related Art Conventionally, a method of forming an insulating isolation groove has been used as one of element isolation methods on a semiconductor substrate.
FIGS. 5A to 5C and 6D to 6F are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps for explaining an example of a conventional method of manufacturing a semiconductor device. As shown in FIG. 5A, an N-type epitaxial layer 2 is formed on a P-type semiconductor substrate 1, and a silicon oxide film 3 and a silicon nitride film 4 are formed. A separation groove 5 is formed. Next, as shown in FIG. 5B, boron is ion-implanted into the bottom of the insulating separation groove 5 and heat treatment is performed, so that the implanted boron is diffused into the P-type semiconductor substrate 1, and the insulating separation by PN junction is performed. Diffusion region 6 for
To form As shown in FIG. 5C, the silicon nitride film 4 and the silicon oxide film 3 are removed, and the insulating isolation trench 5 is formed.
A silicon oxide film 7 and a silicon nitride film 8 are formed on the inner wall and the element formation region.
【0003】次に図6(d)に示すように、絶縁分離溝
5を埋め込むためにボロンリンガラス膜(以下BPSG
膜9と称す)を成長させる。そしてエッチバック法を用
いて、図6(e)に示すように素子形成領域上のシリコ
ン窒化膜8が露出するまで全面エッチングを行い平坦化
を図る。この時、素子形成領域上のBPSG膜9が完全
に除去されるようエッチングを行うと、絶縁分離溝5の
内部のBPSG膜の表面は、素子形成領域のシリコン窒
化膜8の表面より下がり、段差が生じる。この段差を埋
め込むためと、BPSG膜が露出したまま次工程に進ん
だ際のBPSG膜からのボロンの飛び出しいわゆるアウ
トディフュージョン現象による熱処理装置の汚染を防止
するため、その上に液状のシリコン酸化膜(以下PSG
膜10と称す)を塗布し、図6(f)に示すように、同
様のエッチバックを行い素子形成領域表面を露出させ
て、絶縁分離溝を形成していた。Next, as shown in FIG. 6D, a boron-phosphorus glass film (hereinafter referred to as BPSG
(Referred to as film 9). 6E, the entire surface is etched until the silicon nitride film 8 on the element formation region is exposed as shown in FIG. At this time, if etching is performed so that the BPSG film 9 on the element formation region is completely removed, the surface of the BPSG film inside the isolation trench 5 becomes lower than the surface of the silicon nitride film 8 in the element formation region, and a step is formed. Occurs. In order to bury this step and prevent contamination of the heat treatment apparatus due to the so-called out-diffusion phenomenon due to the so-called out-diffusion phenomenon in which boron jumps out of the BPSG film while the BPSG film is exposed, the liquid silicon oxide film ( Below PSG
As shown in FIG. 6 (f), a similar etch-back was performed to expose the surface of the element formation region, thereby forming an insulating isolation groove.
【0004】[0004]
【発明が解決しようとする課題】上述した従来の半導体
装置の製造方法では、BPSG膜9のエッチバックとP
SG膜10のエッチバックにより平坦化を図っているた
め、BPSG膜9の成長時およびPSG膜10の塗布時
の気相条件および基板状態等によって膜質が変化してそ
れぞれの膜のエッチング速度がばらついた場合でも安定
して製造することのできる余裕のある製造条件を設定す
ることが困難であり、例えばPSG膜10のエッチバッ
クの際にエッチング時間が長すぎて、絶縁分離溝5の内
部にBPSG膜の段差を埋めるのに充分なだけのPSG
膜が残らず、絶縁分離溝部と素子形成領域の間で大きな
段差が生じ、後工程において段差被膜性の悪い電極配線
が形成されたり、逆にエッチング時間が短すぎてPSG
膜が素子形成領域上にも残ってしまい、後工程での素子
形成に悪影響を及ぼすといったような不具合が生じ、品
質または製造歩留まりが低下してしまうという欠点があ
った。In the conventional method of manufacturing a semiconductor device described above, the etching back of the BPSG film 9 and the P
Since the SG film 10 is planarized by etching back, the film quality changes depending on the gas phase conditions and the substrate state during the growth of the BPSG film 9 and the application of the PSG film 10, and the etching rate of each film varies. However, it is difficult to set manufacturing conditions that allow for stable manufacturing even when the etching is performed. For example, the etching time is too long when the PSG film 10 is etched back, and the BPSG Just enough PSG to fill the gap in the film
The film does not remain, and a large step is generated between the insulating separation groove and the element formation region. In the subsequent step, the electrode wiring with poor step-coating property is formed, or the etching time is too short, so that the PSG is not formed.
The film remains on the element formation region, causing a problem such as adversely affecting the formation of the element in a later process, and has a disadvantage that the quality or the production yield is reduced.
【0005】[0005]
【課題を解決するための手段】本発明は、半導体基板の
一主表面に絶縁分離溝を形成する工程と、前記絶縁分離
溝を埋め込むに充分な厚さの第一の絶縁膜を半導体基板
全面に成長させる工程と、前記第一の絶縁膜を前記絶縁
分離溝内だけに残して半導体素子形成領域上ではエッチ
ングする工程と、第二の絶縁膜を半導体基板全面に成長
させる工程と、前記第二の絶縁膜の、半導体素子形成領
域の部分に不純物を導入する工程と、前記第二の絶縁膜
を半導体素子形成領域が露出するまでエッチングする工
程とを含むことを特徴とする半導体装置の製造方法であ
る。また本発明は、半導体基板の一主表面に絶縁分離溝
を形成する工程と、前記絶縁分離溝を埋め込むに充分な
厚さの第一の絶縁膜を半導体基板全面に成長させる工程
と、前記第一の絶縁膜を前記絶縁分離溝内だけに残して
半導体素子形成領域上ではエッチングする工程と、第二
の絶縁膜を半導体基板全面に成長させる工程と、第二の
絶縁膜の上にフォトレジストを塗布し、前記フォトレジ
ストを前記絶縁分離溝の上だけに残し、このフォトレジ
ストと第二の絶縁膜を同時に異方性エッチングすること
により素子形成領域を露出させる工程とを含むことを特
徴とする半導体装置の製造方法である。SUMMARY OF THE INVENTION According to the present invention, there is provided a process for forming an insulating separation groove on one main surface of a semiconductor substrate, and forming a first insulating film having a thickness sufficient to fill the insulating separation groove on the entire surface of the semiconductor substrate. Growing on the semiconductor element forming region while leaving the first insulating film only in the insulating isolation groove; growing a second insulating film over the entire surface of the semiconductor substrate; Manufacturing a semiconductor device, comprising: introducing an impurity into a portion of a semiconductor element forming region of a second insulating film; and etching the second insulating film until the semiconductor element forming region is exposed. Is the way. The present invention also provides a step of forming an insulating separation groove on one main surface of the semiconductor substrate, a step of growing a first insulating film having a thickness sufficient to fill the insulating separation groove over the entire surface of the semiconductor substrate, Etching a semiconductor element forming region while leaving one insulating film only in the insulating isolation groove, growing a second insulating film over the entire surface of the semiconductor substrate, and forming a photoresist on the second insulating film Coating, leaving the photoresist only on the insulating isolation groove, and simultaneously exposing the photoresist and the second insulating film to anisotropic etching to expose an element formation region. This is a method for manufacturing a semiconductor device.
【0006】[0006]
【作用】本発明の半導体装置およびその製造方法におい
ては、半導体基板の一主表面に絶縁分離溝を形成する工
程と、前記絶縁分離溝を埋め込むに充分な厚さの第一の
絶縁膜を半導体基板全面に成長させる工程と、前記第一
の絶縁膜を前記絶縁分離溝内だけに残して半導体素子形
成領域上ではエッチングする工程と、第二の絶縁膜を半
導体基板全面に成長させる工程と、前記前記第二の絶縁
膜の、半導体素子形成領域の部分に不純物を導入する工
程と、前記第二の絶縁膜を半導体素子形成領域が露出す
るまでエッチングする工程とを含んで構成されるもので
ある。詳しくは、半導体素子の絶縁分離溝内部に埋め込
まれたボロンリンガラス膜の表面と素子形成領域表面と
の段差を軽減しボロンリンガラス膜からのボロンのアウ
トディフュージョンを防止するためのシリコン酸化膜
を、選択的に絶縁分離溝上部にだけ形成するもので、絶
縁分離溝の上部のリンガラス膜をフォトレジストで保護
しておき、素子形成領域上のリンガラス膜のみに不純物
を導入して濃度を高め、エッチング速度を速くすること
ができるものである。In a semiconductor device and a method of manufacturing the same according to the present invention, a step of forming an insulating separation groove on one main surface of a semiconductor substrate and a step of forming a first insulating film having a thickness sufficient to bury the insulating separation groove in the semiconductor device. A step of growing over the entire surface of the substrate, a step of etching the semiconductor element formation region while leaving the first insulating film only in the insulating isolation groove, and a step of growing the second insulating film over the entire surface of the semiconductor substrate; The second insulating film includes a step of introducing an impurity into a portion of a semiconductor element forming region, and a step of etching the second insulating film until a semiconductor element forming region is exposed. is there. Specifically, a silicon oxide film for reducing the level difference between the surface of the boron phosphorus glass film embedded in the isolation trench of the semiconductor element and the surface of the element formation region and preventing out diffusion of boron from the boron phosphorus glass film. Selectively forming only on the upper part of the isolation trench, the phosphorus glass film on the upper part of the isolation trench is protected by a photoresist, and impurities are introduced only into the phosphorus glass film on the element formation region to reduce the concentration. And the etching rate can be increased.
【0007】[0007]
【実施例】次に本発明の実施例について図面を参照して
説明する。 [実施例1]図1(a)〜(c)、図2(d)〜(f)
および図3(a)〜(c)は、本発明の第1の実施例を
説明するために製造工程順に示した半導体チップの断面
図である。図1(a)に示すように、P型半導体基板1
上にN型エピタキシャル層2を約2μmの厚さで形成
し、900℃程度の熱処理による厚さ300〜400オ
ングストロームのシリコン酸化膜3と化学的気相成長法
による厚さ1000〜1500オングストロームのシリ
コン窒化膜4を形成した上で、半導体素子の絶縁分離の
ための絶縁分離溝5を、P型半導体基板1に達する様、
深さ約4μm、幅約1μmで形成する。次に図1(b)
に示すように、絶縁分離溝5の底部にボロンをイオン注
入し、窒素雰囲気中で900℃程度の熱処理を行うこと
により打ち込んだボロンをP型半導体基板1中に拡散さ
せ、PN接合による絶縁分離のためのP型拡散領域6を
形成する。Next, an embodiment of the present invention will be described with reference to the drawings. [Embodiment 1] FIGS. 1 (a) to 1 (c), 2 (d) to 2 (f)
3 (a) to 3 (c) are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps for explaining the first embodiment of the present invention. As shown in FIG. 1A, a P-type semiconductor substrate 1
An N-type epitaxial layer 2 is formed thereon with a thickness of about 2 μm, and a silicon oxide film 3 having a thickness of 300 to 400 Å by heat treatment at about 900 ° C. and silicon having a thickness of 1000 to 1500 Å by chemical vapor deposition. After the nitride film 4 is formed, an insulating separation groove 5 for insulating and separating the semiconductor element is formed so as to reach the P-type semiconductor substrate 1.
It is formed with a depth of about 4 μm and a width of about 1 μm. Next, FIG.
As shown in FIG. 5, boron is ion-implanted into the bottom of the isolation trench 5 and heat treatment is performed at about 900 ° C. in a nitrogen atmosphere to diffuse the implanted boron into the P-type semiconductor substrate 1 and to perform insulation isolation by PN junction. P-type diffusion region 6 is formed.
【0008】その後図1(c)に示すように、シリコン
窒化膜4およびシリコン酸化膜3を除去し、絶縁分離溝
5の内壁および素子形成領域に1000℃程度の熱処理
による厚さ約2000オングストロームのシリコン酸化
膜7を形成し、図2(d)に示す様に化学的気相成長法
による厚さ約1000オングストロームのシリコン窒化
膜8を形成する。次に図2(e)に示すように、絶縁分
離溝5を埋め込むためのボロンリンガラス膜(以下BP
SG膜9と称す)を半導体装置全面に約1.2μmの厚
さで成長させる。その後、図2(f)に示すように、バ
ッファードフッ酸を用いたエッチバック法を用いて、素
子形成領域上のシリコン窒化膜8が露出するまで全面エ
ッチングして平坦化を行う。この時、素子形成領域上の
BPSG膜9が完全に除去されるようエッチングを行う
と、絶縁分離溝5の内部のBPSG膜9の表面は、素子
形成領域のシリコン窒化膜8の表面より3000から5
000オングストローム程度下がったところになり段差
が生じる。この段差を埋め込むためと、BPSG膜が露
出したまま次工程に進んだ際のBPSG膜からのボロン
の飛び出しいわゆるアウトディフュージョン現象による
熱処理装置の汚染を防止するため、図3(a)に示すよ
うに液状のシリコン酸化膜(以下PSG膜10と称す)
を素子形成領域上で厚さ2000オングストローム程度
になるよう全面に塗布した後、フォトレジスト11を全
面に塗布し、絶縁分離溝5の上部のみフォトレジスト1
1を残すよう、パターニングを行い、リン等のイオンビ
ーム12をPSG膜10中に打ち込む。その後熱処理に
より打ち込んだ不純物イオンをPSG膜10内に拡散さ
せる。Thereafter, as shown in FIG. 1C, the silicon nitride film 4 and the silicon oxide film 3 are removed, and the inner wall of the isolation trench 5 and the element forming region are heat-treated at about 1000 ° C. to a thickness of about 2,000 Å. A silicon oxide film 7 is formed, and a silicon nitride film 8 having a thickness of about 1000 angstroms is formed by a chemical vapor deposition method as shown in FIG. Next, as shown in FIG. 2E, a boron-phosphorus glass film (hereinafter referred to as BP) for embedding the insulating separation groove 5 is formed.
SG film 9) is grown to a thickness of about 1.2 μm over the entire surface of the semiconductor device. Thereafter, as shown in FIG. 2F, the entire surface is etched and flattened by using an etch-back method using buffered hydrofluoric acid until the silicon nitride film 8 on the element formation region is exposed. At this time, if the etching is performed so that the BPSG film 9 on the element formation region is completely removed, the surface of the BPSG film 9 inside the insulating isolation groove 5 becomes 3000 from the surface of the silicon nitride film 8 in the element formation region. 5
A step is generated at a place where the temperature is lowered by about 000 angstroms. As shown in FIG. 3A, in order to fill in this step and prevent contamination of the heat treatment apparatus due to the so-called out-diffusion phenomenon, in which boron jumps out of the BPSG film when proceeding to the next step with the BPSG film exposed. Liquid silicon oxide film (hereinafter referred to as PSG film 10)
Is applied over the entire surface so as to have a thickness of about 2,000 angstroms on the element formation region, and then a photoresist 11 is applied over the entire surface.
Patterning is performed so as to leave 1, and an ion beam 12 of phosphorus or the like is implanted in the PSG film 10. Thereafter, the impurity ions implanted by the heat treatment are diffused into the PSG film 10.
【0009】この結果、図3(b)に示すように素子形
成領域上に高濃度のPSG膜13が形成され、フォトレ
ジスト12を除去した後、バッファードフッ酸を用いた
エッチバック法により、素子形成領域上のシリコン窒化
膜9が露出するまで全面エッチングにより平坦化を行
う。この時、素子形成領域上のPSG膜が完全に除去さ
れるようエッチングを行うが、本発明の特徴である選択
的なイオン注入により素子形成領域上ではPSG膜の濃
度が濃くなっているために絶縁分離溝5上のPSG膜よ
りエッチング速度が早くなり、例えばリン濃度4mol
%のPSG膜の130バッファードフッ酸に対するエッ
チング速度は240オングストローム/分だがリン濃度
を5mol%にするとエッチング速度は300オングス
トローム/分、6mol%では360オングストローム
/分と濃度に比例してエッチング速度は速くなるので、
図3(c)に示すようにBPSG膜10上のPSG膜だ
けを残して素子形成領域上のPSG膜を完全に除去する
ことが容易になる。従って、絶縁分離溝5と素子形成領
域との段差を小さくすることが可能になり、電極配線の
段差被膜性が向上し、また、素子形成領域にPSG膜が
残らないので製品の品質や製造歩留まりを高くできる。As a result, a high-concentration PSG film 13 is formed on the element forming region as shown in FIG. 3B, and after removing the photoresist 12, an etch-back method using buffered hydrofluoric acid is performed. The entire surface is planarized until the silicon nitride film 9 on the element formation region is exposed. At this time, the etching is performed so that the PSG film on the element formation region is completely removed. However, since the concentration of the PSG film is high on the element formation region by selective ion implantation which is a feature of the present invention. The etching rate is higher than that of the PSG film on the insulating separation groove 5, for example, the phosphorus concentration is 4 mol.
% Of the PSG film with respect to 130 buffered hydrofluoric acid has an etching rate of 240 angstroms / min, but when the phosphorus concentration is 5 mol%, the etching rate is 300 angstroms / min, and at 6 mol%, the etching rate is 360 angstroms / min. Because it ’s faster,
As shown in FIG. 3C, it is easy to completely remove the PSG film on the element formation region while leaving only the PSG film on the BPSG film 10. Therefore, it is possible to reduce the level difference between the insulating isolation groove 5 and the element formation region, to improve the step coverage of the electrode wiring, and since the PSG film does not remain in the element formation region, the product quality and the production yield Can be higher.
【0010】[実施例2]図4(a)〜(b)は本発明
の第2の実施例を説明するために製造工程の途中を示し
た半導体チップの断面図である。第1の実施例がフォト
レジストをマスク材にPSG膜に不純物のイオン注入を
行い、フォトレジストを除去した後、ウェットエッチに
よるエッチバックを行うのに対し、本例ではフォトレジ
ストをマスクに、ドライエッチによるPSG膜10のエ
ッチバックを行う。PSG膜10の塗布およびフォトレ
ジストのパターニングまでは第1の実施例と同様である
ため省略するが、図4(a)に示すようにフォトレジス
トのパターニングの後、エッチングガス14により異方
性のドライエッチングを行い、素子形成領域のPSG膜
10を完全に除去する。この時、エッチングガス14の
成分によって、フォトレジストのエッチング速度をPS
G膜のエッチング速度より速くして、図4(b)に示す
様に素子形成領域のPSG膜10が完全に除去される前
に絶縁分離溝上のフォトレジストを除去し、絶縁分離溝
上のPSG膜のエッチングが始まるようにする。[Embodiment 2] FIGS. 4A and 4B are cross-sectional views of a semiconductor chip illustrating a manufacturing process in order to explain a second embodiment of the present invention. In the first embodiment, the PSG film is ion-implanted with impurities using a photoresist as a mask material, the photoresist is removed, and then etch back by wet etching is performed. In the present embodiment, dry etching is performed using the photoresist as a mask. The PSG film 10 is etched back by etching. Since the steps up to the application of the PSG film 10 and the patterning of the photoresist are the same as those in the first embodiment, the description is omitted. However, after the patterning of the photoresist, as shown in FIG. Dry etching is performed to completely remove the PSG film 10 in the element formation region. At this time, the etching rate of the photoresist is set to PS
The photoresist on the isolation trench is removed before the PSG film 10 in the element formation region is completely removed as shown in FIG. Etching is started.
【0011】その結果、本例でも第1の実施例と同様
に、BPSG膜9上のPSG膜10だけを残して、素子
形成領域上のPSG膜を完全に除去することが容易にな
り、絶縁分離溝5と素子形成領域との段差を小さくする
ことができる。また、フォトレジスト11をあらかじめ
薄く塗布しておけば、エッチングガスの成分のコントロ
ールによりフォトレジストのエッチング速度を速めなく
ても、絶縁分離溝上のPSG膜のエッチングが、素子形
成領域上のPSG膜のエッチングより少し遅れて始ま
り、その時間差の分だけ絶縁分離溝上のPSG膜を残す
ことができるので、同様の結果が得られる。As a result, in this embodiment, as in the first embodiment, it is easy to completely remove the PSG film on the element formation region while leaving only the PSG film 10 on the BPSG film 9, and the insulation The step between the separation groove 5 and the element formation region can be reduced. Further, if the photoresist 11 is thinly applied in advance, the etching of the PSG film on the insulating isolation trench can be performed without increasing the etching rate of the photoresist by controlling the components of the etching gas. The same result can be obtained because the PSG film on the insulating isolation trench can be left for a time difference starting with a slight delay from the etching.
【0012】[0012]
【発明の効果】以上説明したように本発明の半導体装置
およびその製造方法によれば、絶縁分離溝内部に埋め込
んだボロンリンガラス膜の表面を覆い素子形成領域との
段差を緩和するために塗布された液状のシリコン酸化膜
を、容易に絶縁分離溝の内部にだけ残して素子形成領域
上では除去することができるため、半導体装置の平坦性
が向上して電極配線の段差被膜性がよくなり、また半導
体素子も安定して製造することができるため製品の品質
が向上し、製造歩留まりも高くなるものであり、また、
半導体素子の絶縁分離溝内部に埋め込まれたボロンリン
ガラス膜の表面と素子形成領域表面との段差を軽減しボ
ロンリンガラス膜からのボロンのアウトディフュージョ
ンを防止するためのシリコン酸化膜を、選択的に絶縁分
離溝上部にだけ形成することができるという効果を有す
る。As described above, according to the semiconductor device and the method of manufacturing the same according to the present invention, the semiconductor device is coated so as to cover the surface of the boron-phosphorus glass film buried in the inside of the insulating isolation groove and to reduce the step with the element forming region. The liquid silicon oxide film that has been removed can be easily removed from the element forming region while remaining only inside the isolation trench, thereby improving the flatness of the semiconductor device and improving the step coverage of the electrode wiring. In addition, since the semiconductor element can be manufactured stably, the quality of the product is improved, and the manufacturing yield is increased.
Select a silicon oxide film to reduce the level difference between the surface of the boron-phosphorus glass film embedded in the isolation trench of the semiconductor device and the surface of the device formation region and to prevent boron out-diffusion from the boron-phosphorus glass film. This has the effect that it can be formed only above the insulating isolation groove.
【図1】本発明の第1の実施例を製造工程順に示すもの
で(a)〜(c)の半導体チップの断面図。FIG. 1 is a sectional view of a semiconductor chip of (a) to (c) showing a first embodiment of the present invention in the order of manufacturing steps.
【図2】本発明の第1の実施例を製造工程順に示すもの
でに続く(d)〜(f)の半導体チップの断面図。FIG. 2 is a cross-sectional view of the semiconductor chip of (d) to (f) following the first embodiment of the present invention in the order of manufacturing steps.
【図3】本発明の第1の実施例を製造工程順に示す半導
体チップの断面図。FIG. 3 is a sectional view of a semiconductor chip showing the first embodiment of the present invention in the order of manufacturing steps.
【図4】本発明の第2の実施例を示す半導体チップの断
面図。FIG. 4 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.
【図5】従来の半導体装置の製造工程(a)〜(c)を
示す断面図。5A to 5C are cross-sectional views illustrating manufacturing steps (a) to (c) of a conventional semiconductor device.
【図6】従来の半導体装置の製造工程(d)〜(f)を
示す断面図。FIG. 6 is a sectional view showing manufacturing steps (d) to (f) of a conventional semiconductor device.
1 P型半導体基板 2 N型エピタキシャル層 3 シリコン酸化膜 4 シリコン窒化膜 5 絶縁分離溝 6 P型拡散領域 7 シリコン酸化膜 8 シリコン窒化膜 9 BPSG膜 10 PSG膜 11 フォトレジスト 12 イオンビーム 13 高濃度のPSG膜 14 エッチングガス DESCRIPTION OF SYMBOLS 1 P-type semiconductor substrate 2 N-type epitaxial layer 3 Silicon oxide film 4 Silicon nitride film 5 Insulating separation groove 6 P-type diffusion region 7 Silicon oxide film 8 Silicon nitride film 9 BPSG film 10 PSG film 11 Photoresist 12 Ion beam 13 High concentration PSG film 14 Etching gas
Claims (2)
成する工程と、前記絶縁分離溝を埋め込むに充分な厚さ
の第一の絶縁膜を半導体基板全面に成長させる工程と、
前記第一の絶縁膜を前記絶縁分離溝内だけに残して半導
体素子形成領域上ではエッチングする工程と、第二の絶
縁膜を半導体基板全面に成長させる工程と、前記第二の
絶縁膜の、半導体素子形成領域の部分に不純物を導入す
る工程と、前記第二の絶縁膜を半導体素子形成領域が露
出するまでエッチングする工程とを含むことを特徴とす
る半導体装置の製造方法。A step of forming an insulating isolation groove on one main surface of a semiconductor substrate; and a step of growing a first insulating film having a thickness sufficient to fill the insulating isolation groove over the entire surface of the semiconductor substrate.
A step of etching the semiconductor element formation region while leaving the first insulating film only in the insulating isolation groove, a step of growing a second insulating film over the entire surface of the semiconductor substrate, and a step of: A method of manufacturing a semiconductor device, comprising: a step of introducing an impurity into a portion of a semiconductor element formation region; and a step of etching the second insulating film until the semiconductor element formation region is exposed.
成する工程と、前記絶縁分離溝を埋め込むに充分な厚さ
の第一の絶縁膜を半導体基板全面に成長させる工程と、
前記第一の絶縁膜を前記絶縁分離溝内だけに残して半導
体素子形成領域上ではエッチングする工程と、第二の絶
縁膜を半導体基板全面に成長させる工程と、第二の絶縁
膜の上にフォトレジストを塗布し、前記フォトレジスト
を前記絶縁分離溝の上だけに残し、このフォトレジスト
と第二の絶縁膜を同時に異方性エッチングすることによ
り素子形成領域を露出させる工程とを含むことを特徴と
する半導体装置の製造方法。A step of forming an insulating isolation groove on one main surface of the semiconductor substrate; and a step of growing a first insulating film having a thickness sufficient to fill the insulating isolation groove over the entire surface of the semiconductor substrate.
A step of etching the semiconductor element formation region while leaving the first insulating film only in the insulating isolation trench, a step of growing a second insulating film over the entire surface of the semiconductor substrate, and a step of: Applying a photoresist, leaving the photoresist only on the insulating isolation groove, and exposing an element formation region by simultaneously anisotropically etching the photoresist and the second insulating film. A method for manufacturing a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5203654A JP2790010B2 (en) | 1993-07-26 | 1993-07-26 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5203654A JP2790010B2 (en) | 1993-07-26 | 1993-07-26 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
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JPH0745694A JPH0745694A (en) | 1995-02-14 |
JP2790010B2 true JP2790010B2 (en) | 1998-08-27 |
Family
ID=16477639
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JP5203654A Expired - Fee Related JP2790010B2 (en) | 1993-07-26 | 1993-07-26 | Method for manufacturing semiconductor device |
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JP (1) | JP2790010B2 (en) |
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KR0179807B1 (en) * | 1995-12-30 | 1999-03-20 | 문정환 | Method of manufacturing semiconductor memory device |
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JPS59182538A (en) * | 1983-04-01 | 1984-10-17 | Hitachi Ltd | Semiconductor device and manufacture thereof |
JPS59182537A (en) * | 1983-04-01 | 1984-10-17 | Hitachi Ltd | Manufacture of semiconductor device |
JPS6240741A (en) * | 1985-08-16 | 1987-02-21 | Nec Corp | Semiconductor device |
JPS63228732A (en) * | 1987-03-18 | 1988-09-22 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
JPS63258039A (en) * | 1987-04-15 | 1988-10-25 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
JPH0574927A (en) * | 1991-09-13 | 1993-03-26 | Nec Corp | Production of semiconductor device |
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