JP2789585B2 - High efficiency coding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a cosine transform (discrete cosine transf
orm) or the like, which relates to a high-efficiency encoding device applied to transform encoding. [Prior Art] In order to suppress the redundancy of an image signal, transform coding in which a screen is divided into blocks each having a predetermined number of pixels and a linear transformation is performed for each block using a transformation axis that matches the characteristics of the original image signal. It has been known. Transform coding includes Hadamard transform,
Cosine transform and the like are known. For example, "IEEE TRANS
ACTIONS ON COMMUNICATIONS "VOL, COM-32, NO.3, MARCH, 1
984, pages 225 to 231 ", a cosine transform coding apparatus having a configuration as shown in FIG. 9 is described. In FIG. 9, a sampled discrete image signal f (j, k) is supplied to an input terminal indicated by 31, and this input signal is supplied to a cosine transform circuit 32. In the cosine conversion circuit 32, two-dimensional cosine conversion is performed. In the two-dimensional cosine transform, a process represented by the following equation is performed. However,
The original data is two-dimensional data f (j, k) (j, k = 0, 1,..., N−1) in which one block is (N × N) samples. The coefficient value F (u, v) from the cosine transform circuit 32 is supplied to the thresholding circuit 33 to reduce the amount of information. The coefficient value F _T (u,
v) is supplied to the quantization circuit 34, the output of the quantization circuit 34 is supplied to the coding circuit 35, and is converted into a code signal having a predetermined number of bits by run-length coding and Huffman coding. The code signal from the coding circuit 35 is supplied to the buffer memory 36. The buffer memory 36 is provided to convert the transmission rate of the code signal from the coding circuit 35 to a rate that does not exceed the rate of the transmission path. The data rate on the input side of the buffer memory 36 is variable, but the data rate on the output side of the buffer memory 36 is substantially constant. Output data from the buffer memory 36 is taken out to a terminal 37. As described above, the amount of information is reduced by thresholding for the coefficient value obtained from the cosine transform circuit 32, and buffering is performed. Thresholding is the execution of the following equation when the threshold value is T,
F (0,0) indicating the DC component of the block is excluded from the thresholding target. [Problems to be Solved by the Invention] The feedback type buffering as described above,
When the buffer memory is about to overflow, the rate of input data to the buffer memory is reduced, and conversely,
When the buffer memory is about to underflow, control is performed so as to increase the rate of input data to the buffer memory. If you raise the sensitivity to the amount of return too much,
Oscillation occurs around the target value, and conversely if the sensitivity is excessively lowered, a problem occurs that it takes time to converge. When it takes time to converge, it is necessary to increase the capacity of the buffer memory 36. As described above, the conventional buffering processing has a drawback that requires considerable know-how in practical use. Further, it is difficult for the conventional feedback type buffering device to make the output data rate completely constant. Considering the application of conversion coding to a digital VTR, data of one frame or one field must be accurately recorded on one track in order to perform variable speed reproduction, for example, still image reproduction. Therefore, it is difficult to apply the conventional transform coding apparatus to a digital VTR as it is. Accordingly, it is an object of the present invention to provide a high-efficiency coding apparatus capable of maintaining a constant data rate in frame units by feed-forward type buffering and efficiently compressing data. is there. [Means for Solving the Problems] The present invention provides a conversion circuit that divides a screen into blocks each including a predetermined number of pixels, performs orthogonal transform on pixel data for each block, and obtains coefficient value data. A block-forming circuit for re-blocking the coefficient value data for each block of the number, and obtaining the amount of information generated during a predetermined period when the quantization width of each block formed by re-blocking is changed. A buffering circuit that determines the quantization width of each block so as not to exceed the target value and minimize the quantization distortion, and coefficient value data other than the DC component of each block formed by reblocking. And a quantization circuit that quantizes the number of bits with a smaller number of bits than the original number of bits and with the quantization width determined by the buffering circuit. The output of the quantization circuit and the buffering circuit Is a high-efficiency encoding apparatus characterized by and information indicating the determined quantization width was set to be transmitted. [Operation] The coefficient value data from the transform encoding is obtained by compressing the original image data. The encoding adapted to the dynamic range can perform feedforward type buffering, and can output data at a constant rate in a frame unit, for example. Therefore, the present invention is suitable for use in a digital VTR. Embodiment A digital VTR to which the present invention is applied will be described in detail with reference to the drawings. This description is made in accordance with the following items. a. Configuration of transmission side and reception side b. Variable length quantization and buffering c. Modification In the case of digital VTR, the transmission side corresponds to the recording side, and the transmission side corresponds to the reproduction side. a. Configuration of the transmitting side and the receiving side In FIG. 1, a sampled discrete image signal is supplied to an input terminal indicated by 1, and an input digital signal is supplied to a cosine transform circuit 2. In the cosine transform circuit 2, two-dimensional cosine transform is performed by the same processing as in the related art. From the cosine transform circuit 2, a (8 × 8) coefficient table corresponding to the block size (for example, 8 × 8) is obtained. In this coefficient table, the DC (average value) component has 9 bits, and the coefficients of the remaining AC components have 8 bits. The coefficient table from the cosine transform circuit 2 is supplied to the blocking circuit 3. Re-blocking is performed by the blocking circuit 3, and the coefficient table is converted into a continuous signal for each block that is a unit of ADRC encoding. In the blocking circuit 3, for example, an (8 × 8) coefficient table is divided into four equal parts as shown in FIG. In this case, the DC component is transmitted as it is without ADRC encoding. Also, as shown in FIG. 3A, when the coefficient table is converted into a data sequence corresponding to the zigzag scanning, the third
Reblocking may be performed on an area as shown in FIG. The output signal of the blocking circuit 3 is supplied to a maximum value detection circuit 4 for detecting the maximum value MAX for each block, a minimum value detection circuit 5 for detecting the minimum value MIN for each block, and a delay circuit 6. The detected maximum value MAX and minimum value MIN are supplied to the subtraction circuit 7, and the dynamic range DR represented by (MAX−MIN = DR) is obtained from the subtraction circuit 7. The delay circuit 6 delays data for a time required to detect the maximum value MAX and the minimum value MIN. The minimum value MIN is subtracted from the video data from the delay circuit 6 in the subtraction circuit 8, and the data PDI from which the minimum value has been removed is obtained from the subtraction circuit 8. The data PDI from which the minimum value has been removed is supplied to the quantization circuit 10 via the delay circuit 9, and the quantization width Δi
Is supplied. The quantization circuit 10 calculates the quantization width Δi
Is used to perform variable-length ADRC encoding for quantizing the data PDI. That is, in the quantization circuit 10, the pixel data PDI from which the minimum value MIN shared by the pixel data in the block has been removed is divided by the quantization width Δi to obtain the dynamic range of the block.
A variable number of bits (0, 1, 2, 3, or 4 bits) are quantized according to the DR. The video signal in the block has a dynamic range DR smaller than that of the original data due to the transform coding, and has a bit number of 0 bits, 1 bit, 2 bits, 3 bits or 4 bits less than 8 bits. Even if quantization is performed, quantization distortion is inconspicuous. The quantization circuit 10 is configured by, for example, a ROM. A 4-bit code signal, which is the maximum number of bits, is generated from the quantization circuit 10, and valid bits are selected from the output signal of the quantization circuit 10 in the framing circuit 15 at the next stage. Therefore, in the ROM 12, together with the quantization width Δi, data Nb indicating the number of bits of the block is formed, and the data Nb is supplied to the framing circuit 15. With a digital VTR, the transmission rate of the recorded data is constant, so if the amount of transmitted data is not limited, some data cannot be recorded or the compression rate will be higher than necessary and the quality of the reproduced image will deteriorate. Or Therefore, a buffering circuit 11 is provided, and the frequency distribution of the dynamic range DR of all the blocks of one screen to be ADRC-coded is examined, and optimal variable-length coding is performed. The buffering circuit 11 has a dynamic range from the arithmetic circuit 7.
DR is supplied. In the buffering circuit 11, threshold values T1, T2, T3, and T4 for obtaining a constant transmission data rate are obtained, and the threshold value and the corresponding parameter code Pi are determined.
Is output. The quantization width Δi determined by the parameter code Pi and the dynamic range DR of the block is read from the ROM 12. The delay circuits 13 and 14 delay the dynamic range DR and the minimum value MIN until the optimum threshold value is obtained by the buffering circuit 11 and variable length quantization is performed. Parameter code Pi from buffering circuit 11 and delay circuit
The dynamic range DR and the minimum value MIN from 13 and 14, the code signal DT from the quantization circuit 10 and the 9-bit data of the DC component passed through the delay circuit 16 are supplied to the framing circuit 15. The framing circuit 15 performs encoding for error correction and adds a synchronization signal. Transmission data is obtained at the output terminal 17 of the framing circuit 15. One parameter code Pi is transmitted on one screen, DR and MIN data are transmitted for each block, and a code signal DT is transmitted for each pixel. Further, as described above, the framing circuit 15 selects valid bits of the code signal DT from the quantization circuit 10 using the data Nb indicating the number of bits. The received data is supplied to an input terminal indicated by 21 in FIG. 4, and is decomposed into a parameter code Pi, a dynamic range DR, a code signal DT, a minimum value MIN, and data of a DC component by a frame decomposition circuit 22. You. The decoding circuit 23 converts the code signal DT into a restoration level, as opposed to the quantization circuit 10 of the ADRC encoder. The restoration level from the decoding circuit 23 is supplied to the addition circuit 25, the minimum value MIN is added to the restoration level, and the restoration data from the addition circuit 25 is supplied to the block decomposition circuit 26. As the output signal of the block decomposition circuit 26, (7 × 8) output data of the coefficient table is obtained. The output signal of the block decomposition circuit 26 and the data corresponding to the DC component passed through the delay circuit 28 are supplied to the inverse cosine transform circuit 27, and the inverse process of the cosine transform as in the conventional case is performed. A decoded output of the digital television signal is obtained at an output terminal 29 of the inverse cosine transform circuit 27. b. Variable-Length Quantization and Buffering FIG. 5 illustrates variable-length quantization performed in the quantization circuit 10. T1, T2, T3, and T4 are threshold values that determine the number of allocated bits. is there. These thresholds are
(T4 <T3 <T2 <T1). When the dynamic range DR (= MAX−MIN) is (DR = T4−
In the case of 1), as shown in FIG. 5A, only the maximum value MAX and the minimum value MIN are transmitted, and the intermediate level L0 between them is set as the restoration level on the receiving side. Therefore, as shown in FIG. 5A, when the dynamic range DR is (T4-1), the quantization width is Δ0. When the dynamic range DR is (0 ≦ DR
In the case of ≤T4-1), the number of allocated bits is 0. FIG. 5B shows a case where the dynamic range DR is (T3-1). Dynamic range DR is (T4 ≦ DR ≦ T3-1)
In the case of, the number of allocated bits is one bit. Therefore, the detected dynamic range DR is divided into two level ranges, and the pixel data PDI after removing the minimum value of the block.
Is determined using the quantization width Δ1,
One of the code signals “0” or “1” corresponding to the level range is assigned, and the restoration level is set to L0 or L1. In the variable length coding shown in FIG. 5, as the dynamic range becomes larger, the quantization width Δi becomes (Δ0 <Δ1 <Δ
Non-linear quantization that is increased to 2 <Δ3 <Δ4) is performed. Non-linear quantization reduces the maximum distortion in a block having a small dynamic range in which quantization distortion is conspicuous, and increases the maximum distortion in a block having a large dynamic range. On the other hand, the compression ratio is increased. When the dynamic range DR is (T2-1), the fifth
As shown in FIG. C, the detected dynamic range DR is divided into four level ranges, and two bits (00) (01) (10) (11) are assigned to each of the level ranges. The level in the middle of the level range is the restoration level L0, L1, L
2, L3. Therefore, the data PD is calculated using the quantization width Δ2.
The level range to which I belongs is required. When the dynamic range DR is (T3 ≦ DR ≦ T2-1), the number of allocated bits is 2 bits. In the case where the dynamic range DR is (T1-1), as shown in FIG. 5D, the detected dynamic range DR is divided into eight level ranges, and each of the level ranges has 3 bits. (000), (001),... (111) are assigned, and the center level of each level range is set as a restoration level L0, L1,. Therefore, the quantization width becomes Δ3. When the dynamic range DR is (T2 ≦ DR ≦ T1-1), the number of allocated bits is 3 bits. Furthermore, if the dynamic range is the maximum of 255,
As shown in FIG. 5E, the detected dynamic range
The DR is divided into 16 level ranges, and 4 bits (0000) (0001)... (1111) are assigned to each of the level ranges, and the center level of each level range is the restoration level.
L0, L1,..., L15. Therefore, the quantization width is Δ4. When the dynamic range DR is (T1 ≦ DR <256), the number of allocated bits is 4 bits. FIG. 6 shows a dynamic range D in the range of (0 to 255).
It is an example of a frequency distribution in which R is the horizontal axis and the frequency of occurrence is the vertical axis. _{x 1, x 2, x 3} , x 4, each of the x _5, as described above, represents the number of blocks included five pieces of the dynamic range DR separated by threshold T1~T4 . (T4−
1) A block having the following dynamic range DR is 0
Since bits are allocated, the number of blocks x ₅ does not contribute to the amount of information generated. Thus, generation amount of information, obtained in _{4x 1 + 3x 2 + 2x 3} + x 4. This amount of generated information is compared with the data threshold, and if it exceeds the data threshold, a larger set of thresholds is applied, and the amount of generated information is calculated in a similar manner. In order to perform the calculation of the above equation, it is necessary to perform a process of obtaining the sum of the frequency distributions in each range for each set of the set thresholds, multiplying the sum by the number of allocated bits, and adding the sum. However, if the above processing is performed every time the set of thresholds is changed, it takes a long time until an optimal set of thresholds is determined. In this embodiment, the frequency distribution shown in FIG. 6 can be converted to the integrated frequency distribution shown in FIG. 7, and the set of different thresholds and the amount of generated information corresponding thereto can be calculated more quickly.
The convergence time until an optimal set of thresholds is obtained can be reduced. As can be understood from FIG. 7, the dynamic range DR
Starts from the maximum occurrence frequency, the occurrence frequencies of the smaller dynamic range DR are sequentially integrated, and an integrated frequency distribution graph is obtained. Therefore, the integration degree is x ₁ next up threshold T1, the accumulated power up threshold T2 (x ₁ + x ₂₎
Next, the accumulated power up threshold T3 is _{(x 1 + x 2 + x} 3) , and the the accumulated power up threshold _{T4 (x 1 + x 2 +} x 3 + x 4). Generated information quantity for threshold T1~T4 is, 4 (x ₁ -0)
+3 _{[(x 1 + x 2) -x} 1 ] + 2 _{[(x 1 + x 2 + x} 3) - (x 1 +
x _2)] + 1 _{[(x 1 + x 2 + x} 3 + x 4) - (x 1 + x 2 + x 3) = 4x
Obtained a _{1 + 3x 2 + 2x 3 +} 1x 4. Once the cumulative frequency distribution graph (cumulative frequency distribution table) shown in FIG. 7 is created, when the set of thresholds is updated, the amount of generated information can be immediately obtained by summing the four numbers. Can be. FIG. 8 is a flowchart showing the operation of the buffering circuit 10. First, the dynamic ranges DR of all the blocks in one screen, for example, one frame are detected (step). Next, the dynamic range DR of one frame
Is created (see FIG. 6) (step). This frequency distribution table is converted into an integration type frequency distribution table (see FIG. 7) (step). The amount of generated information for a set of thresholds (multiple thresholds) in the threshold table,
That is, the total number of bits of the code signal DT when ADRC encoding is performed by applying the selected set of thresholds is calculated (step). In this case, the calculation of the amount of generated information is started from a set of threshold values that minimize the quantization distortion (a set of threshold values specified by the parameter code P0). The obtained amount of generated information is compared with a target value (data threshold) (step). The target value is the maximum value of the transmission rate of transmission data, for example, (2 bits / 1 pixel)
It is. The result of this comparison is determined in steps. When the amount of generated information is equal to or smaller than the target value, the quantization of ADRC is performed using the set of thresholds (step). If the amount of generated information exceeds the target value, the set of thresholds is updated (step). Next, the processes of steps 1 and 2 are repeated for a new set of threshold values that can reduce the amount of generated information. As a table of threshold values T1 to T4, for example, a set of 32 threshold values specified by parameter codes P0 to P31 can be used. Parameter code Pi is P0
The magnitudes of the thresholds T1 to T4 are set so that none of the thresholds T1 to T4 will decrease when changing to P31. The manner and magnitude of the change of the thresholds T1 to T4 are set while observing the image quality. The threshold value of the first parameter code P0 is a very small value for lossless encoding. In the case of the threshold value of the parameter code P31, one bit is allocated to the entire screen. When the thresholds T1 to T4 are set as described above, when calculating the generated information amount in the step, when the parameter code is sequentially changed from P0 to P31, the generated information amount monotonously decreases. become. Therefore, when the parameter code is changed from P0 to P31, a set of thresholds at which the amount of generated information is first equal to or less than the target value is always obtained in the step, and this set of thresholds is applied. ADRC encoding is performed. In addition to the code signal DT, a dynamic range DR, a minimum value MIN, a parameter code Pi, data corresponding to a DC component, and a redundant code of an error correction code are transmitted.
Since these data have a fixed length, they can be ignored by giving an offset to the target value when checking the rate of transmission data. c. Modifications The present invention is not limited to reblocking one coefficient table obtained by transform coding into a plurality of blocks, but may collect a plurality of coefficient tables and perform reblocking. . Also, the transform coding is not limited to cosine transform,
Orthogonal transform such as Hadamard transform may be used. [Effects of the Invention] In the present invention, by applying feedforward type buffering, output data at a constant rate can be generated in frame units, which is suitable for application to a digital VTR. Further, in the present invention, the coefficient value data is re-blocked, and the quantization width is set according to the characteristic of the coefficient value data of each block formed by the re-block, so that the quantization distortion does not increase. , Buffering control can be performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a transmitting side according to an embodiment of the present invention, FIGS. 2 and 3 are schematic diagrams for explaining blocks, and FIG. 5 is a schematic diagram for explaining variable-length quantization, FIGS. 6 and 7 are block diagrams for explaining a frequency distribution table, and FIG. 8 is a diagram for explaining buffering. FIG. 9 is a block diagram for explaining conventional buffering. Explanation of main symbols in the drawings 1: digital video signal input terminal, 2: cosine conversion circuit, 3: blocking circuit, 4: maximum value detection circuit, 5: minimum value detection circuit, 7, 8: subtraction circuit, 10 : Quantization circuit, 11: Buffering circuit.

────────────────────────────────────────────────── ─── Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N ^7/ 24-7/68

Claims (1)

(57) [Claims] A screen is divided into blocks each having a predetermined number of pixels, and a conversion circuit for orthogonally transforming pixel data for each block to obtain coefficient value data, and reblocking the coefficient value data for each arbitrary number of blocks A block generating circuit that calculates the amount of information generated during a predetermined period when the quantization width of each block formed by re-blocking is changed, and calculates the amount of generated information within a range that does not exceed a target value. A buffering circuit that determines the quantization width of each block so that distortion is minimized, and the coefficient value data other than the DC component of each block formed by reblocking is converted into a bit number smaller than the original bit number. And a quantization circuit that quantizes with the quantization width determined by the buffering circuit. The output of the quantization circuit and the quantization determined by the buffering circuit A high-efficiency coding apparatus characterized by transmitting information indicating an encoding width.