JP2786925B2 - A / D converter - Google Patents

Description

The present invention relates to a charge redistribution A / D converter having a binary weighted capacitance array.

(B) Conventional technology FIG. 4 is a circuit diagram of a conventional charge redistribution A / D converter, which shows a 4-bit configuration.

In the case of a 4-bit configuration, the binary weighted capacitance array (1) is composed of five capacitors (1a) to (1e) having capacitances of 8C, 4C, 2C, C and C, respectively. The first electrodes (1a) to (1e) are commonly connected, grounded via a switch (2), and the second electrodes are connected to the changeover switches (3a) to (3e), respectively. One of the changeover switches (3a) to (3e) is grounded, and the other is connected to the changeover switch (4). This changeover switch (4)
A reference potential V _R is inputted into one analog signal to the other
V _IN is input. These switches (3a) to (3e),
Switching of (4) and (2) is controlled in accordance with a switching control signal SC from a control logic (5) described later.

The first electrode side of the capacitance array (1) is connected to the switch (2) and to the inverting input side of the differential amplifier (6). The non-inverting input of the differential amplifier (6) is grounded, so that the output of the differential amplifier (6) If the negative potential V _X of the first electrode side of the capacitor array (1) is "1", If it is positive, it is "0". Then, the output of the differential amplifier (6) is input to the control logic (5), and digital data D _OUT is created. It is further switching control signal SC ₀ to SC ₆ based on the output state create a control logic (5) in the differential amplifier (6), each switch (3a) ~ (3e), (4) and (2)
Supplied to

 Next, the operation of the circuit will be described.

FIG. 5 is a timing chart of the switch operation of FIG. Here, switching of the switches (3a) ~ (3e) and (4), H side shown in FIG. 4 when the switch control signal SC ₁ to SC ₆ is "1", L side when "0" now, switch (2) switching control signal SC ₀ is assumed to be turned on when the "1".

First the switch control signal SC ₀ to SC ₆ the sampling period becomes "1" switch (3a) ~ (3e) (4) is switched to the H side, the switch (2) is turned on, the capacitors The analog signal V _{IN is} applied to the second electrode side of (1a) to (1e).
Is applied to each of the capacitors (1a) to (1e), and 8CV _IN ,
The charge amounts of 4CV _IN , 2CI _IN , CI _IN , and CI _IN are accumulated. Each switch in the hold period switching control signal SC ₀ to SC ₅ is "0" (3a) ~ (3e) is switched to the L side, the switch (2) is turned off, the capacitors (1a) ~ (1
e) The second electrode side is lowered to the ground potential, and the potential of the first electrode in the floating state becomes -V _IN . At this time, the capacitor (1a) ~ total charge amount accumulated in (1e) is 16CV _IN, and this amount of charge is held.

Next, when the switch (3a) is switched again to the H side by MSB determination period, the capacitor V _R to the second electrode of (1a) is applied, the amount of charge is held during the hold period the capacitors (1a) ~ (1e). The distribution of the electric charges is such that the potentials between the two electrodes of the capacitors (1a) to (1e) become equal to each other, and the potential of the second electrode of the capacitor (1a) becomes the potential of the second electrodes of the capacitors (1b) to (1e). performed as higher by V _R with respect. Therefore, since the total capacitance of the capacitance of the capacitor (1a) and a capacitor (1b) ~ (1e) are equal to each other, the potential V _X of the first electrode side is -V _IN + V _R / 2, and this V _X differences It is compared with the ground potential in the dynamic amplifier (6). Therefore, if the analog signal V _IN is higher than V _R / 2, V _X becomes negative, the output of the differential amplifier (6) becomes “1”, and the control logic (5) determines that the MSB is “1”. I do. Conversely, if the analog signal V _IN is lower than V _R / 2, V _X becomes positive and the MSB is determined to be “0”. Control logic (5)
With determination of the MSB is for generating a switching control signal SC _1, MSB is the switching control signal SC ₁ when "1" is maintained at "1", the next period (B2 judgment period when a "0" )
Is set to “0”.

When the MSB is determined to be “1”, the switch (3b) is switched to the H side while the switch (3a) remains at the H side in the subsequent B2 determination period. Then, V _X becomes -V _IN + V _R / 2 + V _R / 4,
Determination as well as the second bit of the MSB depends on the sign of the V _X (B
2) is determined. That is, if V _X is higher than 3V _R / 4 V _X is the result B2 is negative is determined to be "1", if V _X is lower than 3V _R / 4 V
_X becomes positive and B2 becomes “0”.

On the other hand, when the MSB is determined to be "0", the switch (3a) is switched to the L side and the switch (3b) is switched to the H side in the subsequent B2 determination period. Therefore, V _X is −V _IN + V _R /
4 next, B2 is determined depending of the sign of the V _X.

Hereinafter, in the B3 determination period and the LSB determination period, the third bit (B
3) and LSB are determined in the same manner as B2. Therefore, by switching the switches (3a) ~ (3e) successively, V _X is closer to the ground potential, the state of the final switch (3a) ~ (3e) is to represent the digital data D _OUT. Where the control logic (5) are collectively a MSB~LSB obtained serially to each determination period, and outputs a 4-bit digital data D _OUT.

Such a charge redistribution A / D converter is, for example, IEEE J.
Solid State Circuits, Vol.SC-10, No.6, “All-MOS Ch
arge Redistribution Analog-to-Digital Conversion
Techniques-Part 1 ".

(C) In the invention Problem to be Solved above-mentioned A / D converter, that a comparison of the potential in the range of -V _R / 2~V _R / 2 In the differential amplifier (6) is carried out Therefore, to operate the differential amplifier (6), two power supplies, that is, a positive side and a negative side are required. Such an A / D converter is usually formed into an IC, and the need for a plurality of power supplies is a hindrance in forming an IC.

The differential amplifier (6) itself can operate any one of the two power supplies on the + side and the − side as the ground potential. In this case, the determination of the input potential is made on the + side. Alternatively, only one of the-sides can be performed. That is, the normal differential amplifier (6) is configured to compare the input potential within the range of the potential applied to the power supply, and when a potential outside the range of the power supply is input, the normal differential amplifier (6) operates normally. No output can be obtained. As a method for solving such a problem, an intermediate potential (V between the ground potential reference value for determination of the differential amplifier with a single power supply (6) of the power supply potential (V _{R) R} /
2) can be considered. However, V _R / 2 to operate the differential amplifier (6) with respect to the changes to the range of variation of the electrical potential V _X appearing on the first electrode side of the capacitor array (1) from the ground potential to the power supply potential It is necessary to further set V _R / 2, which is a criterion value, so as not to vary.

Accordingly, it is an object of the present invention to enable a differential amplifier to operate with a single power supply and to accurately set a determination reference value.

(D) Means for Solving the Problems The present invention has been made to solve the above-mentioned problems, and is characterized by a capacitor in which a plurality of binary-weighted capacitors are arranged in parallel. An array, means for applying a first reference potential to one electrode side of the capacitance array and for providing an analog signal of a converted value to the other electrode;
Means for applying the first reference potential to the other electrode side of the capacitance array; and a second reference potential or a higher potential than the first reference potential for each capacitor on the other electrode side of the capacitance array. Means for providing a low third reference potential; a correction circuit for correcting the potential so that the first reference potential is an intermediate potential between the third reference potential and the second reference potential; The potential on one electrode side of the capacitor array is set to the first
A control circuit that creates digital data in order from the upper bit based on the comparison result of the comparison circuit, and controls switching of the supply of each potential from the means to the capacitor array; After applying the first reference potential and the analog signal to both electrodes of the capacitor array, respectively, one of the electrodes of the capacitor array is brought into a floating state, and the other is connected to the first reference potential. When the one electrode side of the capacitance array is lower in potential than the first reference potential, the second reference potential,
When the potential becomes high, the third reference potential is sequentially supplied to each capacitor of the capacitor array.

(E) Operation According to the present invention, the second reference potential is shifted from the third reference potential centering on the first reference potential which is an intermediate potential between the second reference potential and the third reference potential. The comparison of the analog signal values is performed, and the comparison circuit can be operated with a single power supply by setting the second reference potential to the power supply potential and the third reference potential to the ground potential. The comparison range is from the ground potential to the power supply potential.

(F) Embodiment One embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of the A / D converter of the present invention, showing a case of a 4-bit configuration.

The capacitance array (10) is composed of four capacitors (10a) to (10d) having capacitances of 4C, 2C, C and C, a first electrode is commonly connected, and a switch (11) is connected to the first electrode. , A voltage (V _R / 2) that is half of the reference voltage V _R is applied. The second electrodes of the capacitors (10a) to (10c) are connected to switches (13a) to (13c), respectively, and one of the switches (13a) to (13c) is connected to the switch (14). The other is connected to the changeover switch (15). Also,
The second electrode of the capacitor (10d) is directly connected to the changeover switch (14). Analog signal for the changeover switch (14)
V _IN and V _R / 2 are applied, and either one is set to the changeover switch (1
3a) to (13c) are supplied to the capacitor. Then, V _R is applied to one of the change-over switch (15), the other is grounded. These switches (13a) to (13c)
(14) (15) and (11) are switched in accordance with the switching control signal SC from the control logic (16) having the same configuration as that of FIG.

First electrode side of the capacitor array (10) is connected to the inverting input of the differential amplifier (17), it is compared to V _R / 2 to the voltage V _X is applied to the non-inverting input. Therefore, lower the potential V _X of the first electrode side of the capacitor array (10) than the V _R / 2 differential amplifier (1
The output of 7) is “1”, and if it is high, it is “0”. The control logic (16) is the same as the control logic (5) in FIG. 4, and the description is omitted.

Supplied to capacitance array (10) and differential amplifier (17)
V _R / 2 is created by dividing the reference potential V _R by resistance.
Potential errors due to variations in resistance are corrected by a potential correction circuit (1
It is minimized by the correction in 8). That is, in the operation of the differential amplifier (17) and the accompanying operation of the changeover switch (15), V _R / 2 is extremely important, and the resistance when dividing the reference potential V _R by resistance is used. Errors due to variations in values cannot be ignored. Therefore, the output of the potential correction circuit (18) is actually monitored, an accurate error is detected, and correction data indicating the detection result is stored in an EPROM (19) in advance.
By storing the configured retrieve the correct reference potential during the actual conversion operation (V _R / 2).

FIG. 2 is a circuit diagram showing an example of the potential correction circuit (18).

The reference potential V _R is divided by a voltage dividing circuit (21) in which a plurality of resistors (R) are connected in series, and an intermediate potential V _R (V _R / 2) between the ground potential and the reference potential V _R is divided. The sandwiched two potentials are further finely divided by a voltage dividing circuit (22) in which a plurality of resistors (r) are connected in series. The voltage of each stage of the voltage dividing circuit (22) is supplied to the selecting circuit (2) operating according to the decoder (23).
One potential is selected according to 4) and is output via the output amplifier (25). The decoder (23) is configured to operate based on the correction data stored in the EPROM (19), and selects the potential closest to V _R / 2 from the potential of each stage of the voltage dividing circuit (22). Let it. That is, the correction data is stored in the voltage divider circuit (2
2) Designates the address of the potential closest to V _R / 2 among the potentials at each stage. Measures the output of the selection circuit (24) and corrects the address of the potential closest to V _R / 2 As data
It is stored in the EPROM (19). For example, the output of the counter (27) that counts the clock CK is converted into correction data and supplied to the decoder (23), the output of the selection circuit (24) is monitored, and the output of the selection circuit (24) is V _R / 2 The output of the counter (27) when it is closest to
Store in (19). Also, here we store the correction data
Although the EPROM (19) is used, any read-only memory to which data can be written can be used.

According to the potential correction circuit (18) as described above, the correction data is stored in the EPROM (19) after manufacturing, whereby errors due to variations in resistance during manufacturing are corrected, and an accurate potential is obtained. Can be.

 Next, the operation of the circuit will be described.

FIG. 3 is a timing chart of the switch operation of FIG. Switches (13a) to (13c) (14) (15) and (1
1) The operation of FIG. 3 the same manner as in the case the switch control signal SC ₁ to SC
₅ is H side when it is "1", is switched to the L side when it is "0", the switch control signal SC ₀ shall be turned on when the "1".

The sampling period, the switch control signal SC ₀ to SC ₄ is "1" switch (11) is turned on the switches (13
a) to (13c) are switched to the H side and each capacitor (10
a) to (10d) are applied with V _R / 2 and V _IN, and each of the capacitors (10a) to (10d) is supplied with 4C (V _IN −V _R / 2) and 2C (V _IN −V _R /
2) The charge of C (V _IN −V _R / 2) and C (V _IN −V _R / 2) is accumulated.

Subsequently, in the MSB determination period, the switch (11) is turned off, the switch (14) is switched to the L side, and the capacitance array (10)
V _R / 2 is applied to the second electrode. In this period, since the switch (11) is turned off and the first electrode side of the capacitance array (10) is in a floating state, the amount of electric charge accumulated in the capacitance array (10) during the sampling period is held and this amount of electric charge is reduced. to be distributed to the capacitors (10a) ~ (10d), V X becomes _{V R / 2 + (V R} 2-V iN). So this V _X
The MSB is determined by comparing with V _R / 2. That is, if V _IN is higher than V _R / 2, V _X becomes lower than V _R / 2, the output of the differential amplifier (17) becomes “1”, and the control logic (15) sets the MSB to “1”. If V _IN is lower than V _R / 2, V _X is V _R / 2
It becomes higher, the output of the differential amplifier (17) becomes “0”, and the MSB is determined to be “0”.

Switch control signal SC _5, when the MSB is determined as "1", "1" MSB is "0" becomes "0". This M
Switching control signal until the SB is determined SC ₅ may be either. (The period shown by the broken line in FIG. 2) Next, in the B2 determination period, the switch (13a) is switched to the L side, and if the MSB is “1”, the second voltage of the capacitor (10a) is changed.
V _R is applied to the electrodes, MSB is the second electrode of the capacitor (10a) if "0" is grounded. V _X when MSB is “1”
_{V R / 2 + (V R} / 2 + V R / 4-V IN) becomes a differential amplifier (1
From the output of 7), the second bit (B2) is determined. That is, if V _IN is higher than 3V _R / 4, V _X becomes lower than V _R / 2, the output of the differential amplifier (17) becomes “1”, B2 is determined to be “1”, and V _IN becomes 3V if lower than _R / 4 V _X is B2 becomes the output of the differential amplifier (17) is a "0" is higher than V _R / 2 is determined as "0". On the other hand, when the MSB is "0" V _X is _{V R / 2 + (V R} /
4−V _IN ), and when V _IN is higher than V _R / 4, V _X is lower than V _R / 2 and B2 is “1”. Conversely, when V _IN is lower than V _R / 4, V _X
There B2 is higher than V _R / 2 is determined to be "0".

Switching control signal SC _1, in accordance with the determination of B2, B2 is maintained as long as "1" following B3 determination period after "1" is maintained at "0" if B2 is "0".

During the B3 judgment period and the LSB judgment period, the switch (1
3a) (13c) operates in the same manner as the switch (12a) in the B2 determination period, and the third bit (B3) and the LSB are determined. That is, M
When SB is "1", the second capacitor (10b) (10c)
V _R / 2 and V _R are alternately applied to the electrodes to determine the magnitude of V _X and V _R / 2, and when the MSB is “0”, the capacitor (10b)
(10c) V _R / 2 and ground potential are alternately applied to V _X and V _R / 2
Is determined. Therefore, each switch (10a) ~
Closer to V _X to V _R / 2 by switching (10c) in the order, the state of the final each switch (10a) ~ (10c) and (15) would represent the bits of the digital data D _OUT.

In such an A / D converter, five steps (in the case of 4 bits) are required to obtain one digital data, so that it is compared with a serial type or a serial / parallel type A / D converter. Although the conversion speed is slower, the circuit configuration is much simpler than that of a serial type or the like, so that the circuit scale can be significantly reduced and the number of bits can be increased by adding capacitors and changeover switches. Bit conversion is easy.

(G) Effects of the Invention According to the present invention, the comparison operation of the differential amplifier can be performed in the range from the ground potential to the reference potential, so that operation with a single power supply is possible and the differential amplifier can be operated. Can be sufficiently secured, and the dynamic range of the circuit can be prevented from being reduced.

Further, by providing an error correction circuit for an intermediate potential obtained by dividing the reference potential by resistance, an error due to manufacturing variations is eliminated, and a highly accurate A / D conversion operation can be realized.

[Brief description of the drawings]

1 is a circuit diagram of an A / D converter of the present invention, FIG. 2 is a circuit diagram of a potential correction circuit, FIG. 3 is an operation timing diagram of FIG. 1, and FIG. 4 is a diagram of a conventional A / D converter. FIG. 5 is a circuit diagram, and FIG. 5 is an operation timing chart of FIG. (1), (10) ... Capacitance array, (1a) to (1e), (10
a) to (10d) ... capacitors, (2), (11) ... switches, (3a) to (3e), (4), (13a) to (13c),
(14), (15) ... changeover switch, (5), (16) ...
Control logic, (6) (17) ... differential amplifier, (18) ...
... potential correction circuit.

Continuation of the front page (56) References JP-A-63-300627 (JP, A) JP-A-1-133423 (JP, A) JP-A-61-69217 (JP, A) JP-A-60-105322 (JP) , A) JP-A-60-93531 (JP, A)

Claims (2)

(57) [Claims] 1. A capacitor array in which a plurality of binary-weighted capacitors are arranged in parallel, a first reference potential is applied to one electrode of the capacitor array, and a converted value of a converted value is applied to the other electrode. A means for applying an analog signal; a means for applying the first reference potential to the other electrode side of the capacitance array; and a high potential with respect to the first reference potential for each capacitor on the other electrode side of the capacitance array. Means for applying a second reference potential or a third reference potential of a low potential, and a plurality of potentials taken out from the third reference potential to the second reference potential, and one of the taken out potentials A correction circuit that outputs one of the potentials as the first reference potential, and a selection circuit that specifies an optimum potential among a plurality of potentials extracted from the third reference potential to the second reference potential. Data is stored in advance and the above correction A read-only storage circuit for giving a selection instruction to a path, a comparison circuit for comparing the potential on one electrode side of the capacitor array with the first reference potential, and a digital data higher rank based on a comparison result of the comparison circuit. And a control circuit that sequentially controls the supply of each potential from each of the means to the capacitor array from the bit, and
After applying the first reference potential and the analog signal to both electrode sides of the capacitor array, respectively, one electrode side of the capacitor array was floated, and the first reference potential was applied to the other electrode side. At this time, if one electrode side of the capacitor array has a potential lower than the first reference potential, the second
Wherein the third reference potential is sequentially supplied to each capacitor of the capacitor array when the reference potential becomes a high potential.
D converter. 2. The correction circuit according to claim 1, further comprising: a first voltage dividing circuit for dividing the second and third reference potentials by resistance; and a further two potentials sandwiching an intermediate potential of the first voltage dividing circuit. 2. The semiconductor device according to claim 1, further comprising: a second voltage dividing circuit for dividing, and a selecting circuit for selectively extracting one potential from the second voltage dividing circuit based on the selection data stored in the storage circuit. 2. The A / D converter according to claim 1.