JP2786028B2 - Erroneous write protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an erroneous write protection circuit, and more particularly to a nonvolatile semiconductor memory device such as an ultraviolet erasing type E.
The present invention relates to a P-ROM erroneous write prevention circuit.

[0002]

2. Description of the Related Art A conventional ultraviolet erasing EP-ROM is shown in FIG. FIG. 4 shows the conventional ultraviolet erasing EP-RO of FIG.
FIG. 9 is an operation waveform diagram at the time of programming in M.

As shown in FIG. 3, the ultraviolet erasing type EP-ROM has a semiconductor memory (hereinafter, referred to as a memory cell).
1, 2, 3, 4 and memory cells 1 and 2 or memory cell 3
And 4, and a circuit (hereinafter referred to as a charge pump) 1 for generating and applying a high voltage to the gate of the memory cell selected at the time of programming.
P-channel transistors or switches 7 and 8 for electrically connecting the _Vpp terminals 1 and 12 used as the power supplies of the charge pumps 11 and 12, and the gates of the memory cells selected during programming (hereinafter referred to as word lines). N-channel depletion transistors 5 and 6 that cut off the high voltage so that the high voltage is not applied to the decoders 9 and 10.

Further, at the time of programming, a circuit (hereinafter referred to as write circuits 13 and 14) for controlling whether a high voltage is applied to a drain (hereinafter referred to as a data line) of a memory cell in accordance with write data according to write data. ). The write circuits 13 and 14 are controlled by an external signal PGM.

After the programming of the memory cell 2 is completed, the erroneous write prevention circuit 41 operates until the programming of the memory cell 1 is started. This erroneous write prevention circuit 4
Reference numeral 1 denotes an inverter 16 that receives an external signal PGM, a resistor 20 and a capacitor 21 that delay the output signal of the inverter 16, and a signal delayed by the resistor 20 and the capacitor 21 is input to the inverter 17. The output signal of the inverter 17 is input to one of the NAND gates 18, and the other of the NAND gate 18 is input with the external signal PGM.

[0006] The output signal of the inverter 18 is the inverter 1
9 and the output signal of the inverter 19 is input to the gates of the high-voltage cutting transistors 5 and 6, and at the same time, to the level shifter 15 that converts the voltage level. The output signal of the level shifter 15 is input to the gates of the switching transistors 7 and 8.

The conventional ultraviolet erasing EP-ROM shown in FIG. 3 will be described with reference to an operation waveform diagram at the time of programming shown in FIG.

The decoder 10 is selected (at t0), and the power supply voltage level (hereinafter referred to as _Vcc level) is applied to the source of the N-channel depletion transistor 6.
At this time, the gate level of the N-channel depletion transistor 6 is at the _Vcc level, and the word line C is at the _Vcc level.

Next, at time t1, the external signal PGM becomes the ground level (referred to as GND level), and the connection point E also becomes the GND level.

When the connection point E goes to the GND level, the gate of the N-channel depletion transistor 6 and the output of the level shifter 15 go to the GND level.
When the output of the level shifter 15 goes to the GND level, the P-channel transistor 8 turns on, the charge pump 12 starts operating, and the word line C goes to a high voltage.
At this time, when the write circuit 13 starts operating and data for applying a high voltage (approximately 8 V) to the data line A is externally input, external data information is written to the memory cell 2 (memory). Cell 2 has a threshold level of 8 to 9
V).

When the external signal PGM goes to the _Vcc level and the program ends (at time t2), the write circuit 13 stops operating and the high voltage is not applied to the data line A. At this time, the connection point E due to the delay circuit of the resistor 20 and the capacitor 21 is used.
Is at the GND level, and the word line C is at t1 to t.
2, the high potential is held in the same state as the memory cell 2, and the memory cell 2 is turned on.
In this state, the data line A is discharged by the memory cell 2.

After the external signal PGM becomes the _Vcc level,
The connection point D is delayed to the _Vcc level by the delay value of the delay circuit formed by the resistor 20 and the capacitor 21 (at time t3).

When the connection point D reaches the _Vcc level, the connection point E
Also at the _Vcc level. When the connection point E is at the _Vcc level, the output of the level shifter 15 becomes high potential (the same level as the _Vpp terminal), and the P-channel transistor 8 is turned off.
At F, the charge pump 12 stops operating and at the same time, the gate of the N-channel depletion transistor 6 goes to the _Vcc level, so that the charge of the word line C flows to the decoder 10 side, and the word line C goes to the _Vcc level. . When the word line C goes to the _Vcc level, the memory cell 2 is turned off, and the discharge of the data line A is stopped.

At this time, if the delay value of the delay circuit including the resistor 20 and the capacitor 21 is small, the charge of the data line A cannot be sufficiently discharged by the memory cell 2. Therefore, the data line A is in a high potential state (about 7 to 8 V) (t
When the next address is input and the decoder 9 is selected, the memory cell 1 is selected at the same timing as the operation described above (at time t4).

At this time, since the power supply voltage is applied to the word line B, the memory cell 1 is turned on, and the charge of the data line A is discharged by the memory cell 1. However, since the gate level of the memory cell 1 is at the _Vcc level, the ability to allow current to flow is small, and the electric charge of the data line A is not sufficiently discharged (the data line A is kept at a high potential state). In this state, the external signal PGM is set to GND.
Level (at time t5), and the word line B becomes high potential at the same timing as the operation described above.

At this time, since the level of the gate (word line B) and drain (data line A) of the memory cell 1 is in a high potential state, writing to the memory cell 1 is performed irrespective of data input to the writing circuit 13. Is performed.

[0017]

After the program is completed (when the external signal PGM is at the _Vcc level), the word line of the conventional ultraviolet erasing type EP-ROM shown in FIG. To maintain the state, the resistance 2
Although the delay circuit of 0 and the capacitor 21 is used, when the resistance value and the capacitance value of the resistor 20 and the capacitor 21 are reduced during diffusion or when the power supply voltage is increased, the resistor 20 and the capacitor 21 are used.
And the delay value of the delay circuit becomes smaller.

When the delay value becomes small, the time for holding the word line in a high voltage state after the program is completed becomes short, and the data line cannot be sufficiently discharged after the write is completed. When a memory cell to which data information is not written is connected to a data line to which discharge has not been sufficiently performed and is selected at the next address, and the word line becomes high potential, the data line of the memory cell to which data information is not written becomes high. There is a problem in that the potential and the word line are set to a high potential and the conditions for writing are set, and data to be written is not written even though it is input from the outside, resulting in erroneous writing.

An object of the present invention is to provide an erroneous write prevention circuit which solves such a problem and prevents erroneous write.

[0020]

For Means for Solving the Problems] As the present invention is flop
Address in synchronization with an external signal indicating programming
Word line to which the gate of the selected memory cell is connected
Control to apply and discharge high voltage to the next address
Prevent erroneous writing of selected memory cells during programming
Erroneous write protection circuit
And input connection of all data lines to be selected.
Of these data lines, select the data line whose address is selected.
High voltage applied corresponding to write data during programming
Is detected below the reference voltage
A differential amplifier for outputting, programming the erroneous write
Prevent the discharge level of the data line from the reference voltage
A reference voltage generating circuit for generating a pair to the external signal
In response, a high voltage is applied to the word line, and the high voltage is applied to the word line.
Control is performed in response to the sensing signal
And a logic circuit for outputting a control signal.

[0021]

FIG. 1 is a circuit diagram of a memory including an erroneous write protection circuit according to one embodiment of the present invention, and FIG. 2 is a waveform diagram showing the operation of each section in FIG.

In FIG. 1 and FIG. 2, this embodiment is different from the prior art erroneous write prevention circuit 41 of FIG. 28 are connected in series, and a resistor 27 and a resistor 28 are connected.
Is input to the gate of the N-channel transistor 26.

[0023] Further, a source connected to the Vcc level, the P-channel transistor 25 and P-channel transistors 2 4 connecting the gate and drain to the drain of the N-channel transistor 26, a current mirror configuration, the P-channel transistor 25 and P-channel 2 of the transistor 2 4
The size of the two transistors is the same.

Further, the source is connected to the GND level, the gate is connected to the data line, and the drain is connected to the P-channel 2.
N-channel transistor 22 connected to the drain of
23 and the N-channel transistor 26 have the same transistor size.

The connection point F is input to the NAND circuit 29 to which the external signal PGM is input, and the output signal of the NAND circuit 29 is input to the inverter 30. This inverter 3
The output of 0 has the same function as the conventional connection point E of FIG.

Other circuits and operations other than the erroneous write circuit 40 of the present embodiment (FIG. 1) are the same as those of the conventional example of FIG.

The voltage at the connection point I of the erroneous write circuit of this embodiment is _Vcc level × {resistance value of resistor 28 / (resistance value of resistor 28 + resistance value of resistor 27)}.
The resistances 28 and 27 are set to 1.5V.

Next, the operation of the erroneous write protection circuit of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to the waveform diagram of FIG.

When the decoder 10 is selected (at time t0), V
_cc level is N channel depletion transistor 6
To the source. At this time, the gate level of the N-channel depletion transistor 6 is at the _Vcc level, and the word line C is at the _Vcc level.

Next, at time t1, the external signal PGM becomes the GND bevel, and the connection point H also becomes the GND level. Connection point H
To the GND level, the gate of the N-channel depletion transistor 6 and the level shifter 15
Becomes the GND level. When the output of the level shifter 15 goes to the GND level, the P-channel transistor 8 turns on, the charge pump 12 starts operating, and the word line C goes to a high voltage.

At this time, the write circuit 13 starts operating,
When data for applying a high voltage (approximately 8 V) to the data line A is externally input, external data information is written to the memory cell 2 (the threshold level of the memory cell 2 becomes 8 to 9 V). ).

The N-channel transistors 22 and 2
3 and 26 and the P-channel transistors 24 and 25 constitute a differential amplifier.
Since the data line A is at a higher level at a higher potential (about 8 V), the connection point F is at the GND level.

When the external signal PGM becomes the _Vcc level and the program ends (at time t2), the writing circuit 13 stops operating and the high voltage is not applied to the data line A. At this time, since the data line A is at a high potential, the connection point F
D level is output, and the connection point H is also at GND level,
The word line C is kept at the high potential in the same state as t1 to t2, and the data line A is discharged by the memory cell 2 because the memory cell 2 is in the ON state.

When the data line A is discharged by the memory cell 2 and the level of the data line A becomes lower than the level of the data line A <the level of 1.5 V at the connection point I (at t3), the connection point F Becomes the _Vcc level, and the connection point H
Also at the _Vcc level. When the connection point H goes to the _Vcc level, the output of the level shifter 15 becomes a high potential (the same level as the _Vpp terminal), and the P-channel transistor 8 is turned off.
At F, the charge pump 12 stops operating and at the same time, the gate of the N-channel depletion transistor 6 goes to the _Vcc level, so that the charge of the word line C flows to the decoder 10 side, and the word line C goes to the _Vcc level. .

When the word line C goes to the _Vcc level, the memory cell 2 is turned off, and the discharge of the data line A is stopped. At this time, the level of the data line A is lower than the level 1.5 V of the connection point I.

When the next address is input and the decoder 9 is selected, the memory cell 1 is selected and turned on at the same timing as the operation described above (t4).

When the memory cell 1 is selected, the level of the data line A becomes close to the GND level, and the word line B becomes high potential at the same timing as the operation described above (t5).

At this time, the write circuit 13 starts operating,
When data for not applying a high voltage to the data line A is input from outside, the word line B of the memory cell 1 has a high potential and the data line A is near the GND level, so that the condition for writing to the memory cell 1 is satisfied. Therefore, there is no erroneous write to the memory cell 1.

[0039]

As described above, according to the present invention, instead of providing a delay circuit and discharging the data line by the delay value of the delay circuit as in the conventional erroneous write protection circuit, a reference voltage is generated by a resistor. By providing a circuit for discharging the data line to the reference voltage or lower, there is an effect that erroneous writing to the memory cell at the time of programming is eliminated.

Although the present invention has been described with respect to the memory cell of the ultraviolet erasing type EP-ROM, the electric erasing type EP-ROM is described.
The same effect can be obtained for a memory cell of a ROM.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a memory including an erroneous write protection circuit according to one embodiment of the present invention.

FIG. 2 is a waveform chart showing the operation of each unit in FIG.

FIG. 3 is a circuit diagram of a memory including a conventional erroneous write protection circuit.

FIG. 4 is a waveform chart showing an operation of each unit in FIG. 3;

[Explanation of symbols]

1,2,3,4 ultraviolet erasable EP-ROM memory cell 5, 6 N-channel depletion transistor 7,8,24,25 P-channel field effect transistors 9 and 10 write decoder circuits 11 and 12 charge pump 13 Circuit 15 Level shifter 16, 17, 19, 30 Inverter 20, 27, 28 Resistor 21 Capacitor 18, 29 NAND circuit 22, 23, 26 N-channel field-effect transistor Vcc Power supply potential Vpp High-level potential for writing PGM External signal for writing 40 , 41 Erroneous write protection circuit Data Information signal input from outside

Claims (1)

(57) [Claims] 1. An external signal indicating write at the time of programming is provided.
Synchronously, the gate of the addressed memory cell is
Control to apply and discharge high voltage to the connected word line
Erroneous programming of the memory cell of the next address selection.
In an erroneous write prevention circuit that prevents data at the time of programming, the drain of the memory cell is connected to
Input lines, and select an address among these data lines.
Supports write data during programming on selected data line
The applied high voltage was discharged below the reference voltage
And a differential amplifier for sensing the error and outputting the sensing signal, and the data line for preventing the erroneous writing during programming.
A reference voltage generating circuit for generating a discharge level of the reference voltage as the reference voltage, and applying a high voltage to the word line in response to the external signal.
After programming, release this high voltage in response to the sensing signal.
And a logic circuit for outputting a control signal for controlling powering.