JP2772008B2 - Processing unit for processing digital input data - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to bar code data received from a scanning device.
Various types of bar codes and
And other digital data scanning formats
The present invention relates to a technique for processing input data from a computer. BACKGROUND ART As is known, various devices for reading barcodes
Scanning devices are currently available. These include
Slots widely used by other retailers
Scanners of canna, hand type and optical pen type scanner
There is na. The data from these scanners is
Decoding information with Sessa and other types of devices
Must be processed to be able to Barcodes consist of bar and space symbols, each symbol
Is either a bar or a space, and each bar and
And the width of the space (ie, bar to space or space
From bar to bar and the interval between transitions)
The content of the code information, for example, the
Provides lufabet / numbers. The printed barcode is initially a light emitting device, ie,
Scanned by laser, light emitting diode, etc.
It is. The light beam is a slot scanner or a hand held model
Automatically traverses code as in the case of some scanners
Draw or as with a light pen or wand
Alternatively, the code can be manually swept across.
In each case, the scanning device is photosensitive, like a phototube
(Light responsive) components from the code
Detect reflected light. This photosensitive means is a code
An electrical signal corresponding to the detected symbol is generated.
These signals are then processed and decoded. The first way to process barcodes is
Transition to space or space to bar
Measure the phase and then the interval between that transition and the next transition
And stages. A series of high-frequency sources
Generate pulses, count these pulses, and
The interval between transitions (ie, depending on the scanner)
(The width of the detected bar or space). transition
Digital count indicating the interval between and the "sign" of the interval
Is sent to a decoder (decoding device), and the decoder
Information of the bar code read and / or
Or change to alphabetic expression. Process data from slot scanners or desktop scanners
Requires an internal frequency of 40 MHz or 20 MHz
Is done. In some cases, a frequency of about 10 MHz is most effective.
It is efficient. The data of the type of scanner you hold is usually
5 or 2.5 MHz frequency, sometimes around 1.25 MHz
Processed using frequency. Lower for light pen
The frequency is used, and the average frequency is about 78KHz to 9.76KHz.
used. Today, various types of barcodes are used. most
Commonly used barcodes are UPCs.
It is a universal product code. UPC uses only numbers
A generic code for the model used, generally for retail
Has been used. Other codes include (1) UPC
European version of "EAN"; (2) Read by machine
Federal government standard for warehouse and inventory management
"Code" which is an alphabet-number barcode
(3) is an interleaved numeric code
"I2 of 5"code; (4) dollar sign, dash, etc.
In early number codes with a few other symbols like
Yes, mainly for photo processing and library code
There is "Codabar" used. Others that are highly specialized and are not widely used
The code includes the complete ASCII set "Code
128 "and" Plessey "codes," Code 93 "and" Code
There is 11 ". As will be appreciated by those skilled in the art, the bar code spacing
Depending on the type of material that the barcode is attached to
I can do it. For example, for rough materials such as paperboard.
In this case, the printing of the code is of low density. That is, bars and spaces
The source is relatively wide. For such low density codes,
The detection frequency of code transitions tends to be shorter. High answer
For materials that allow high resolution or high density printing, i.e.
For very thin bars and spaces, the detection frequency is higher
You can do it. Thus, for certain barcodes
Even, the spacing between bars and spaces varies significantly,
As a result, the circuits needed to detect and process the code
There is a difference in wave numbers. Two types of decoders are widely used.
One such decoder is for decoding UPC / EAN barcodes.
Of accumulation of national cash register used for
Fixed, such as tractor chip No. 6-1005415 / NCR-8415
There is a program decoder. Another type of decoder is the so-called
Programmable processor decoder
ssor decoder). This type of decoder is a processor
Yes, UPC and EAN codes, and various other
Can be used to decode model codes. As will be apparent to those skilled in the art, fixed program decryption
Is significantly faster than programmable processor decoder
Operates at On the other hand, this fixed program
Specially designed to decipher certain codes,
Lack of flexibility but programmable processor
Decoder decodes various codes and selects frequency
And other desirable functions such as error detection.
You can incorporate the program to get it. Conventional equipment is compatible with all types of scanners (desktop scanners).
A hand-held scanner and a light pen or wand.
Scanners). In addition, such a device, because of the large number of frequencies available,
More efficient for the specific information you are trying to read
By automatically selecting the digitizer frequency,
-Has the flexibility to process code data
did not exist. In addition, conventional devices have multiple type decoders and
Not suitable for working together (ie fixed programs
(Herd-wired) decoder and programmable professional
It cannot work with both Sessa decoders). DISCLOSURE OF THE INVENTION According to one preferred embodiment, the present invention provides a
Is a hand held scanner and light pen and stick (one
And bar code scanners of various types
Provide a device to process the provided barcode data.
Offer. According to another type of the invention, the device is capable of various types of bars.
Perform code data processing. According to yet another embodiment of the present invention, various digital
Digitizing such data using frequency
Equipment for processing barcode data
Provided. According to another alternative embodiment of the present invention, multiple frequency
To generate numbers and process specific data.
Allows automatic selection and use of efficient frequencies
Provided by a device for processing barcode data
Is done. According to yet another embodiment of the invention, such data is
By decrypting the data using different means, the data
Cross-check that the digitization is accurate
Enables devices for processing barcode data
Provided. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows the basic components of the device and
FIG. 2 is a general block diagram of a connected state, FIG.
FIG. 3 is a block diagram showing a transition detector and a sequencer of the apparatus shown in FIG.
FIG. 4A is a block diagram of the frequency divider and frequency components of the device shown in FIG.
FIG. 4B is a schematic diagram of a several-bank switching circuit and an array reset circuit. FIG.
FIG. 5A is a schematic diagram of a control circuit of a multiplexer, FIG. 5A is an input selector of the device shown in FIG.
Schematic diagram of detector and main sequencer, Fig. 5B shows FIFO sequencer and FIFO reset circuit, load
Circuit, symbol circuit and 8-bit digital circuit shown in FIG.
Counter schematic line contributing to lower 4 bits of count
Figure and Figure 5C shows the upper four bits of an 8-bit digital count.
Counters, latches and switches shown in FIG.
FIG. 3 is a schematic diagram of an overflow reset circuit and an overflow reset circuit.
You. Description of the Invention Like parts are referenced with reference to the accompanying drawings, designated by like numerals.
FIG. 1 shows a digitizer / sequencer device.
Ten general block diagrams are shown. Same as before
The bar or line above a symbol or term in this description
Indicates a level or reverse signal. The digitizer / sequencer device 10
In the power circuit 22, all conventional types of scanner devices
Receive the barcode above from 11. This device 10 is input
Process information and barcode bar and space symbol width
Digital count signal indicating the digital
A "sign" signal indicating whether the
And transitions within the barcode (ie, bar to space
Or transition from space to bar)
Signal. These signals are sent from device 10 as described above.
Fixed program like integrated circuit chip for UPC decoding
Decryptor 20 or, if desired, a processor containing a UPC code
Decode any type of code programmed in the processor
Programmable processor (programmable processor)
(Rosesser) 26. This programmable processor
The input 26 may include a first-in first-out (FIFO) storage device or
Processor having a buffer (buffer) (not shown)
The information received from device 10 until 26 is decipherable
Retain information. Processor 26 is desynchronized with device 10
To work, a FIFO storage device is required. Device 10 processes input from any type of scanner
Device 10 generates multiple operating frequencies
Means to be described below are provided. On the other hand,
The ram-capable processor 26 provides control signals to the device 10 for input.
Select the best frequency for processing and decoding force (scanner) information
Select. Thus, device 10 performs several important functions. The equipment
10 is to divide the frequency from the digital clock source
Provides multiple frequencies and multiplexes these frequencies
The best frequency to time and control the device itself
To provide a clock input to the fixed program decoder 20.
To decode the first code, for example, the UPC code
Can be done. Programmable processor 26 for optimal frequency
Automatically generate a control signal for selecting. Further, the device 10 processes the input from the barcode scanner.
Process to detect transitions in the barcode and
Used to digitize the interval between the transitions. Fixed program
Ram decoder 20 is similar to programmable processor 26 in implementation.
Receives transition information and digital count value from device 10.
You. The device 10 activates a predetermined sequence each time a transition occurs in the barcode.
Step-by-step operation of the device
An attaching means 28 is provided. Hereinafter, the digitizer / sequence will be described with reference to FIG.
The overall operation of the device 10 will be described. Any form
Bar code scanner 11 or magnetic card reader
Other readers that provide digital signals such as
It is arranged to be connectable to ten scanner input circuits 22.
The operation timing of the device 10 is a timing pulse.
Can be timed by row. Clock input 12 is
Provide a pulse train. The pulse train also has a fixed program
In addition to timing the operation timing of the decoder 20,
Activate the counter and scan the bar or space
Get digital count value to measure width of source symbol
Used to Clock input 12 is an external fixed frequency source 13, such as
From a 40 MHz crystal or another external clock 15
To generate a pulse train. Output of clock input circuit 12
Are provided to the clock division circuit 14. This circuit has a coefficient
2, the frequency of the clock pulse is continuously divided,
As described in more detail below, multiple clock frequencies
It has a divider for generating numbers. This multiple clocks
The clock signal is a multiplexer, clock max (MUX) 1
6 provided. As shown in Fig. 1, a 40 MHz clock
The clock input signal is also provided directly to clock max 16. Clock Max 16 is a programmable processor 26
And clocks in related circuits (as described below).
Device 10 based on the control signal received from the
Select the desired output frequency for Crocma
The output of Box 16 is two clock signals, the S clock.
Clock signal and M clock signal. This S clock signal
The signal is used for basic timing of the operation timing of the device 10.
Provide input to a digital counter (described below)
On the other hand, the M clock signal is sent to the fixed program decoder 20.
It basically provides a timing signal. The input (barcode) provided from any scanner device 11
C) Data processing will be described below. With scanner
The power circuit 22 generates an output signal which is to be processed.
The bar code signal detected by the
The delivery means 24 is provided. This circuit provides the input signal
Transition from bar to space or space to bar based on
Is detected, or the symbol that occurs before the transition is a bar or space
Is determined. Thus, transitions and signs
Detecting means 24 provides signal TRANS to indicate that a transition has occurred.
Both supply the signal VIDEO and the symbol "sign" (ie,
Or whether a space or space is detected). these
The signal is provided to a fixed program decoder 20. further,
The transition and sign detector 24 is a separate
Provide a signal. This signal is called the "SIGN" signal
And acts as an input to the programmable processor 26.
Provided on a first-in-first-out (FIFO) storage device (not shown)
It is. The transition and sign detection means 24 also includes an ordering means 28.
Provide a signal (described below) and operate the ordering means 28.
Start moving. This ordering means 28 is started at the occurrence of each code transition.
Through a predetermined number of steps (detailed below)
The device 10 is operated stepwise. The ordering means 28 is suitable
Sometimes on the FIFO input side of processor 26 And the processor receives data from the device 10.
To be able to get. The ordering means 28 also comprises a transition and
Providing a signal to the sign detection means 24, whereby the means 24
Generate a TRANS signal and also digitize
Can be recorded at a new interval.
The ordering means 28 also enters the digitizing counting means 30.
Provide a force signal, thereby detecting each transition
The start and stop of the counters occurring in
You. The digitizing counting means 30 is also a clock max.
Input signal is received from 16 (S clocks). This signal
The counter is allowed (enabled) by the ordering means 28
), The counter operates at the selected speed
Let it. Clock max 16, ordering means 28 and digitization
All counting means 30 supply signals to the interconnection circuit 33
This allows the digitized count data to be
Properly sent to the FIFO in the programmable processor 26
I can do it. As explained below, the clock max 16
Two banks available for: upper bank and lower
It is arranged to provide the frequency of the bank. Up
The selection of the frequency from the lower bank
It is determined by the link switching means 62. This frequency van
Switch 62 also provides an input to array reset 38.
The array reset 38 is controlled by the clock divider 14 according to an instruction.
Provide a signal for resetting. Details of this instruction
Will be described below. The clock divider circuit 14
Also, by inverting the array reset signal, Generate. this Resets the rest of the device 10. This reset state
The instruction to start is usually connected to the device 10 and
Generated by the test equipment (not shown) used for testing.
You. 2 and 3 show a digitizer / sequencer device.
Device 10 is shown in more detail. Illustrated in FIG.
Clock max 16 is S clock
Kusa Max (MUX) 32, M clock multiplexer
・ Max (MUX) 34, CC3 multiplexer ・ Max
(MUX) 36 and CC3 circuit 40 are provided. These multiplexes
The lexer and the circuit select one of a plurality of operating frequencies,
Optimized handling of scanner device input data
Work. The operation of these circuits is described in detail below.
This will be described in detail. 40 MHz output from clock input circuit 12
The clock signal is applied to the flip-flop in clock divider circuit 14.
FF1 and S clock max 32. H
Rip-flop FF1 divides 40MHz in half, so
For the second flip-flop FF2 and S clock max 32
Transmits a 20 MHz signal. On the other hand, flip-flop FF2
Splits the 20MHz input signal in half, and therefore
Divider FD1, S clock max 32 and M clock
The box 34 is transmitted with a 10 MHz signal. Frequency divider FD1 converts 10MHz input frequency signal to coefficient 2.
Therefore, by dividing continuously eight times, eight additional
Frequency. Lowest frequency generated by FD1
The number is sent to FD2, which continues the signal by a factor of 2.
Is further divided four times. Output of frequency divider FD1, FD2
Is the S clock max 32 and M clock max 34
Connected to these as their respective inputs. Frequency divider
And Clock Max and Clock Max
Will be described in detail below.
Here, the maximum input frequency for the S clock max 32
The number is 40 MHz while the M clock max 34
Since the maximum input frequency is 10MHz, M clock
Source 34 has two highest frequencies (eg, 40 MHz and 20 MHz)
Except for the same frequency as S Clock Max 32
And two additional low frequencies (eg 4.48KHz)
And 2.44KHz). As described above, the output of S-clock max 34 is
And an internal clock for the digitizing counting means 30.
And M clock max 34
The output provides a clock signal to the fixed program decoder 20
You. Operation of S clock max 32 and M clock max 34
Operation control will be described below. For this purpose,
Boxes 32 and 34 are three digital clock control signals CC0 and CC1
And CC2. These signals are programmed
Transmitted from the possible processor 26 to the upper bank
Select a set of frequencies from the 7 sets of frequencies supplied to the kusa
I do. Controls frequency selection by this multiplexer.
Programmable fourth or highest order bit for
It can also be provided by the processor 26. Thus,
Processor 26 is connected to CC3 control circuit 40. On the other hand,
This circuit controls the CC3 multiplexer 36, and
Kusa 36 is an additional supply provided to the lower bank multiplexer.
Are multiplexed. Therefore, four control signals,
CC0, CC1, CC2 and CC3 decode device 10 and fixed program
One set of frequencies selected from 13 sets for operating the heater 20
Provide the ability to As described in more detail below,
If the fourth control signal CC3 cannot be obtained, clock control
Signals from processor 26 in addition to signals CC0, CC1 and CC2 Can be used to internally generate a CC3 signal.
You. From processor 26 Is connected to the array reset circuit 38 (FIGS. 1 and 2).
It is. The array reset circuit 38 includes frequency dividers FD1, F
Clear D2, It works to generate this Clears other circuits in device 10 and allows for post-production testing
To The array reset circuit 38 also provides an array for operation.
-Frequency bank switching means 62 for preparing for reset
(Described below). This frequency bank switching
The operation of the receiving means 62 will be described below. Where is
No such signal available from programmable processor 26
In that case, the means 62 may internally generate the CC3 signal.
Just explain that you can. Next, referring to FIG.
4 and the operation of the ordering means 28 will be described. this
The transition and sign detection means 24 basically includes a transition detector 45 and
A coding circuit 46 is provided. The output of the scanner input circuit 22 is
It is connected to the transition detector 45. This transition detector 45
Generates a TRANS signal and a VIDEO (video) signal, respectively.
The transition has occurred, and the symbol before the transition is a bar
Or a space. These signals are fixed
Provided to the ram decoder 20. The decoder 20 converts these signals
Show the content of the scanned code as before using
Provide an output signal. The ordering means 28 is basically composed of the main sequencer 42 and the FIFO sequence.
It includes a sequencer 44 and a FIFO reset circuit 54. Transition detection
The output unit 45 sends a signal to the main sequencer 42 when a transition occurs.
Output to initiate a controlled actuation sequence. Then
The main sequencer 42 continuously outputs the next eight S clock pulses.
When the selected count is reached, the device 10 is turned off.
Provides a signal to actuate. The transition detector 45 also
An input is provided to a "sign" circuit 46. From main sequencer 42
The signal is provided to circuit 46 and the SIGN output signal (scanned
The symbol "sign" indicates the programmable processor 26.
To ensure that it is provided to the FIFOs in the right time.
The details of the operation of the main sequencer 42 will be described below.
You. The main sequencer 42 also has a
Generates a signal to activate a load circuit 48
You. This load circuit 48 is a part of the digitizing counting means 30.
Preload on the other counter, that is,
Load in advance and reset the other counter.
Work. For this purpose, as shown in FIG.
The digitizing counting means 30 includes counters 50 and 52 and
A load circuit 48 is provided. Counters 50 and 52 are S clock
It is activated by a signal (not shown in FIG. 3). Especially,
Before the main sequencer 42 counts 8, the load circuit 48
Considering the generated eight clock pulses, the count value
The counter 50 is set to 8 in advance. Count 8
Thereafter, the counter 50 starts counting by a signal from the main sequencer 42.
You can start the event. The ordering means 28 includes the main sequencer 42 and the FIFO
It includes a sequencer 44 and a FIFO reset circuit 54. FIFO
The sequencer will be described below. Here, the FIFO
The sequencer is suitable for the FIFO in the programmable processor 26.
Be able to receive data from the device 10 at the right time
I will just explain. Thus FIFO sequencer 44
Is By providing the FIFO to the FIFO in processor 26.
The count information from the ports 50 and 52 to the processor 26
To control that. The main sequencer 42 is a FIFO sequencer 44
Provides a signal to wake up and start the sequence. FI
The FO reset circuit 54 receives a signal from the processor 26. And FIFO when receiving signal from main sequencer 42
Reset the sequencer 44. FIFO sequencer 44 is also connected to latch 56. This
Latch 56 is a programmable count value processor
Output counts from counters 50, 52 until provided to 26
Hold and stabilize the value. As described in more detail below, the counters 50, 52
Are four-stage counters each connected to each other
You can count 255 times, 255 times. program
The FIFO in the processor 26 has a count value of 255 or less.
I can not receive. Therefore, the counters 50 and 52 overflow.
-In other words, when the total count value is 255 or more
Case), the over connected to the carry output of counter 52
-Flow circuit 58 is activated and the maximum count value of 255 is latched.
Lock in the 56. This overflow circuit 58
It constitutes a part of the connection circuit 33 (FIG. 1). This circuit is based
Essentially, the latch 56, the overflow circuit 58, and the
An overflow reset circuit 60 is provided. Oberg
So that the low circuit 58 can be cleared or reset.
An overflow reset circuit 60 is provided. The circuit
60 is connected to the load circuit 48 of the digitizing counting means 30
ing. Thus, the overflow circuit 58 is
Is activated by the overflow reset circuit 60.
Reset. Cow to determine the duration of the code between transitions
Event information from the counter 50 to the fixed program decoder 20
Provided. In particular, this decoder 20 is the fourth counter 50
Has its own internal counter that operates independently at the eye level
Have. Thus, the counter 50 has 4
Decoder while supplying the count value of the two least significant digits
The counter itself has a larger number of remainders
Character and the duration of the symbol between code transitions.
judge. Hereinafter, FIGS. 4A, 4B, 5A, 5B, and 5C will be referred to.
Referring to the operation of the digitizer / sequencer device 10
explain about. However, before entering this explanation, FIG.
And the reference numerals used in the detailed wiring diagram of FIG.
I do. Arrows with open heads indicate input and output pins of the device.
Represent. The open arrow on the head pointing inward indicates the signal
An arrow pointing to the outside with an open head
Show pin. Large circles indicate internal chip persistence
You. The small circle indicates the internal bonding state. The closed arrow is the signal
Indicates the direction. Apparatus 10 is divided into separate components
Large-scale integrated circuit (VLSI) chip
It is desirable to form it with a tip. The device is a standard 28
Mount in pin package or standard 40 pin package
Rukoto can. Inputs relevant only to 40-pin package
Or the output is shown in parentheses. Uses a 40-pin package instead of a 28-pin package
FIG. 4A illustrates the protocol for
The details of the clock input circuit 12 will be referred to. NOR gate NOR
Note that input B of 2 is grounded by the adhesive terminal
To do. For 40-pin package, connect to NOR2 input B
Connected middle terminal (small circle) and grounded lower terminal (small circle)
High impedance by breaking the bond between circles)
A (Z) TTL clock input can be accepted.
Next, connect the middle terminal (small circle) to the high impedance clock.
Upper terminal (small circle) connected to the pin that receives the input
Connect to Thus, the 28-pin package has an external clock
Input cannot be supported, but the 40-pin package does
I can get it. Contrast with 20-pin package
To connect additional pins of the 40-pin package
One method is employed throughout this specification. Clock input 12, clock divider 14, frequency and band
Details of the switching circuit 62 and the array reset circuit 38
This will be described with reference to FIG. 4A. I will foresee
Thus, the clock input 12 is connected to the NOR gate 2 and a pair of
Equipped with inverters I2 and I4. 40MHz crystal 13 is pin X
Connected across TAL1 and XTAL2, inverter I2
Shunt. 40MHz oscillation of crystal and inverter I2
Form a bowl. The output of the oscillator, which is the clock signal, is I4
It passes through and is connected to input A of NOR2. NOR2 input B
Is grounded in a 28-pin package. As mentioned above
Thus, the connection between input B and ground B is broken and input B
Connected to a high impedance clock input.
External clock to the input of NOR2 for a 40-pin package.
Can be provided. The output of NOR2 is a 40 MHz clock signal, which is output via line L102.
Clock divider 14 and clock max 16
It is. See Figure 4B for the operation of Clock Max 16.
This will be described in detail while referring to the drawings. 40 MHz clock signal
Connected to input of barta I6. Inverter I6 output
Is connected to the clock input pin of flip-flop FF1.
ing. Q output of FF1 is clocked via line L103.
16 connected to The flip-flop FF1 is
Input frequency because the terminal is connected to its D input
Generate an output frequency that is 1/2 of Therefore, 40MHz input
Output frequency, the output of flip-flop FF1 on line L103
The frequency at the input terminal Q is 20 MHz. Flip flow
The preset terminal of the tap is connected to + 5V bias.
You. The terminal of flip-flop FF1 is flip-flop FF2
Clock input pin. This flip flow
The tip is also connected by connecting its terminal to its D terminal.
Connected so as to act as a two-to-one divider.
You. Thus, the output at its Q terminal of FF2 is
The wave number becomes 1/2, that is, 10 MHz.
Provided to Box 16. Conventionally, a clock input signal of 40 MHz is used twice for coefficient 2.
40 MHz each on lines L102, L103, L104
z, 20 MHz, and 10 MHz signals were provided. these
Are provided to the clock max 16. Frequency division
FD1 and FD2 continuously divide the input signal by a factor of 2.
1 is a conventional type circuit having two parts A and B. Scratch
Therefore, these are the signals appearing at the Q output of FF2, for example, 10 MHz.
Subsequent splits provide additional frequencies for device 10.
In particular, the output of flip-flop FF2 is
Connected to input A. The first part A of FD1 is Q
Provides output in A, QB, QC, QD. These pins
Are connected to lines L105, L106, L107 and L108 respectively.
These lines are connected to clock max 16.
You. Thus, the signals appearing on lines L105, L106, L107, L108
Are 5 MHz, 2.5 MHz, 1.25 MHz, and 625 KHz, respectively. Minute
The QD terminal of the divider FD1 is connected to the B input of FD1, so that
Supply 625KHz frequency input to B section of FD1. QA ′, Q
The lower sets of Q outputs at B ', QC', and QD 'are 312, respectively.
KHz, 156KHz, 78KHz and 39KHz. These signals are
Appear on lines L109, L110, L111, L112 respectively. QD 'terminal of frequency divider FD1 is A input of frequency divider FD2
Connected to power. Thus, the 39KHz
The lock frequency is divided in half at FD2,
As a result, 19.5 KHz appears at the terminal QA of FD2 on the connected line L113.
It is. QA terminal of frequency divider FD2 is B of frequency divider FD2
Connected to the input side of the part. Thus, the input that appears on the pin
The signal is continuously split by a factor of two, resulting in line L114
A frequency of 9.75 KHz appears on the terminal QB of the
C has a frequency of 4.875 KHz and terminal QD on line C116.
Shows a clock frequency of 2.44KHz respectively. Above
FD1 and F appearing on lines L105 to L116, respectively.
The output of D2 is connected to clock max16. The details of the operation of the frequency bank switching circuit 62 will be described below.
explain. As can be foreseen, circuit 62 comprises NAND2, NAND4,
Four NAND gates, NAND6 and NAND8, and two
It has barters I8 and I10. As explained below
In addition, S clock max 32 and M of clock max 16
Each clock max 34 has one of the upper bank frequencies
And the other handles the frequency of the lower bank.
Equipped with a Luchiplexer. Frequency bank switching circuit 62
Is the upper or lower bank of each clock max 32, 34
It controls which frequency is selected. Then, referring to FIG.
The generated binary clock control inputs CC0, CC1 and CC2
Appears on the respective lines L120, L121 and L122. These signals are
Provided to control the operation of the frequency bank switching circuit 62
Is done. These are also used for frequency selection (see Figure 4B).
See) Clock Max 16 via lines L120, L121, L122
Connected. In particular, each of the lines L120, L121, L122 has a high level.
Signal ("1") appears, Is generated by the processor 26, the S clock
Lower bank of frequency of multiplex 32 and M clock max 34
Is selected. CC0, CC1 and CC2 are all
When high, inputs A, B,
C is at a high level. A low level signal ("0") is provided to the input of inverter I8.
It is. Therefore, the output of inverter I8 becomes high level and NA
The input D of ND2 goes high. Now NAND2 is activated
The output is low. NAND2 output is NAND
Connected to the input A of the NAND4, which outputs the output of the NAND4
Goes high, generating the internal control clock CC3 signal.
Let The high level output of NAND4 is CC3 controlled via line L123.
Connected to road 40 (FIG. 4B). This output was triggered
Through this circuit (as described below)
S clock max 32 and M
Select the output frequency of the lower bank of Clock Max 34
Work like that. The programmable processor 26 has a lower bus
Command to switch from the link frequency to the upper bank frequency.
The processor is using the clock control input.
2 on CC0, CC1, CC2 (lines L120, L121, L122 respectively)
The binary signals 0, 1, 1 are generated. Is provided by processor 26 and all its inputs are high.
NAND6 generates a low-level output signal
You. Especially at low levels Is provided to the input of inverter I8. This allows
The output of data I8 goes high. This output is the input of NAND6.
Connected to force A, which causes it to go high. line
The low level CC0 signal on L120 is applied to the input of inverter I10.
Provided. The output of inverter I10 goes high and NAN
High level of CC1 on line L121 which drives input D of D6 high
A signal is provided to input C of NAND6, which allows it to
High level. The CC2 high level input on line L122 is provided to input B of NAND6.
It is at a high level. Thus, four inputs of NAND6
The forces are all high, which results in a low level output.
It becomes. The output of NAND6 is connected to the input B of NAND gate NAND8.
Has been continued. As a result of the low level input of NAND8,
Output goes high. NAND8 output is NAND4 input B
, And output to NAN2 of high level is also NAN.
NAND4 is activated because it is connected to input A of D4.
There, a low level signal appears at its output terminal,
To remove the internal CC3 signal on line 123, as described below.
As described above, the device 10 has the S clock max 32 and the M clock
Box 34 is switched to the upper bank frequency. Next, the operation of the array reset circuit 38 will be described.
You. As described above, this array reset circuit 38
Resets dividers FD1 and FD2, generates a signal,
Signal is provided to the clock divider circuit 14. This signal resets the device 10 for testing
I do. The array reset circuit 38 is basically a NAND gate NAND
10, equipped with flip-flop FF4 and NOR gate NOR4
You. The programmable processor 26 has lines L120, L121, L122
When a high level ("1") signal is placed on top
Two consecutive low levels ("0") Is activated, the circuit 38 is activated. Is provided to input B at NOR gate NOR10. Line L120, L1
21, when there are all high level signals on L122,
One As a result, the output of NAND4 becomes high level. The output of NAND4 is
Since it is connected to input A of NAND10, both inputs to NAND10
Power is the second Goes to a high level before appears. Therefore, the output of NAND10 is low.
Level. Second Occurs, the input B of NAND10 goes low,
Set the output of ND10 to high level. This is a flip
Apply a high level input to the clock input of
Operates the flip-flop FF4, where the output terminal
The child goes low. FF4 terminal is the input of NOR gate 4
A is connected to A and input B of NOR4 is connected to the output of NAND2.
Is low at this point because
As a result, the output of NOR4 goes high. The output signal from the array reset 38
Provided as input to road 14. This signal is part of circuit 14.
FD1 and FD2, which compose the above, are reset.
In particular, the output of NOR4 is connected to the reset input terminals RA and RB of FD1.
Connected to the reset input terminals RA and RB of FD2.
I have. This signal resets both frequency dividers. Further
The high level signal at the output of NOR4 is
To generate a low level signal at its output. This
Output of flip-flops FF1 and FF2
-"Is connected to the input terminal and these are cleared. late
In addition, all components of the frequency divider circuit 14
Placed in the state. In addition, the output pin of inverter I12
Is low level And this signal is used in the test as described below.
To reset all components of the device. In summary, To the high-level signals on CC0, CC1, and CC2 (10
(Corresponding to base number 7)
While switching to the lower bank frequency, Low CC0 signal, high CC1 and CC2 signals (decimal
Equation 6) describes the device 10 as a high frequency bus of a clock multiplexer.
Switch to link. Two The clock control signal of decimal "7" with
Signal and Generate. FIG. 4B shows the clock multiplexer circuit 16.
It will be described with reference to FIG. Clock multiplexer circuit
16 is basically the S clock max 32 and M clock described above.
Rockmax 34 and CC3 Multiplexer Max3
6, and an associated CC3 circuit 40. S clockma
Box 32 has two multiplexers with eight inputs and one output.
UB1, on the other hand, defines the upper bank frequency
On the other hand, the other side, LB1, defines the lower bank frequency.
You. Similarly, the M clock max 34
Multiplexers, UB2 and LB2, each with an upper
And the lower bank frequency. S clock
The upper bank UB1 and lower bank LB1 of Max 32
Appear on lines L120, L121, L122 at terminals A, B, C respectively
Controlled by CC0, CC1, and CC2 signals. The strobe inputs S of UB1 and LB1 are grounded. Up
The input frequency signal to the bank multiplexer UB1 is
Appear on lines L102 to L108 (input D0 respectively)
To D6). "1" of CC0, CC1 and CC2 selects the frequency
Not to generate the internal CC3 signal as described above
Or array reset and UB1's input D7
Ground. Signals on control inputs A, B and C of multiplexer UB1
Is any frequency appearing on D0 through D6 (lines L102-108)
Will appear at its Y output terminal. For example, UB1
Select the frequency on line L104 that appears at input D2 (eg, 10MHz)
If an attempt is made, a binary signal equal to decimal number 2
0, L121, L122. This is because input A is low level
Input B is high and input C is low.
You need to be. Multiplexer LB1 is for S clock max 32
Select a frequency from the lower bank frequency. Thus, Maru
The multiplexer inputs D0-D5 are fed from the clock divider circuit 14
They are connected to lines L109 to L114, respectively. As mentioned above
A binary clock control signal equal to decimal number 6 and a decimal number
Up and down using a binary clock control signal equal to 7
Since switching between banks is performed, inputs D6 and D7 of LB1 are not connected.
Ground. M clock max 34 is the same as S clock max 32
Use the clock control input on lines L120, L121, L122
You. The multiplexer UB2 of M Clock Max 34
Select the upper bank frequency provided on inputs D0-D6.
+ 5V is applied to D7. For UB1, use inverted output W
Is done. Similarly, in the case of LB2, the input frequency is
To D0-5 on L116. D6 and D7 are used
Not connected to the + 5V signal level. The inverted output W is fixed
Because of the necessity of adjusting the operation of the fixed program
Used for Kumax 34. Of the upper or lower bank clock frequency with respect to device 10.
S clock mac to select which one to use
32 selected upper and lower bank frequency signals are CC3
A multiplexer 36 is provided. Thus, the clock map
The output signal from the mixer 32 is connected to the inputs 1A and 1B of the CC3
While M Clock Max 34 is selected
The upper and lower bank frequencies are CC3 Max 36, respectively.
Input 2A, 2B. The CC3 Max 36 basically consists of S clock and
Upper bank frequency signal or lower bank for M clocks
Two-to-one multiplexing to select one of the frequency signals
It has a circuit. Thus, from S Clock Max 32
The selected frequency appears on the output terminal 1Y of CC3 Max 36
On the other hand, the frequency selected from the M clock max 34 is
Appears at output terminal 2Y of CC3 Max36. Upper bank or
The selection of one of the lower bank signals is CC3 Max 36
This is done by the signal appearing on the selection input of
If a high level signal appears on the
The lower bank frequency is selected and used as the M clock signal.
The lower bank frequency is selected. Signal on S terminal is low
Level, the S clock has an upper bank frequency signal
Signal is selected, upper bank frequency is selected for M clock
Is done. The input signal selected for CC3 Max 36 is shown in Figure 4B
Provided by the CC3 circuit 40 as shown in FIG. This circuit is based
Three NAND games, NAND12, NAND14, and NAND16
And an inverter I14. The CC3 signal appearing on line L123 is the input of NAND gate NAND12
A is connected. Input B of this gate is connected to + 5V
You. Thus, when the level of line L123 increases, ie, LB
1.If switching to the lower bank frequency of LB2 is desired,
The input A of the NAND 12 is at a high level. As a result, NAND12
The output goes low. Therefore, the NAND gate NAND14
Input A goes low. Input B is directly grounded and input A is
Since it is connected to + 5V via inverter I14, NAND
The inputs A and B of the gate NAND16 go low. This
A high level signal is generated at the output of NAND16. Before line L123 goes high, the inputs to NAND14 are
Both are high level. Therefore, the output of NAND14 is low level
Becomes If the CC3 signal on line L123 goes high, N
The input A of AND14 goes low and the output of NAND14 goes high.
And then select CC3 Max 36 or input terminal
Is high, which selects the lower bank frequency.
Selected. When the CC3 signal goes low, it appears on line L123.
Signal is provided to input A of NAND 12 so that
The output goes high, and the output of NAND14 goes low.
You. This operation switches the output of CC3 Max 36.
And the upper bank frequency is selected. If a 40-pin package is used for device 10, CC
The three signals are provided directly to the circuit 40, and thus the frequency bank
The switching circuit 62 generates the internal CC3 signal to
To eliminate the need to select one of the
Rukoto can. Thus, for a 40-pin package,
Connects to input B of NAND16 when power is applied to the terminal of CC3.
The connection to the ground is broken, and the pin is connected to the CC3 input terminal
Is done. Should use CC3 internal signal or external signal
The mode input terminal is used to select between. Inva
The connection between the input of data I14 and the input B of NAND12 is + 5V
And is connected to the mode input. Mode input
If high, the internal CC3 signal is used. Mo
The external CC3 signal is enabled when the
Bull. This means that the signal at the mode input terminal
When low, the output of inverter I14 is high.
This is because the input A of the NAND 16 becomes high level.
Therefore, when the external CC3 signal goes high, NAN
The output of D16 goes low. This output is the input of NAND14
B. When the input B of NAND14 goes low
Output of NAND14 becomes high level, and CC3
Set the selector input S high, where the lower bank frequency
A number is selected. If the CC3 signal is low, NAND1
The output of 6 goes high, causing the input B of NAND 14 to go high. Mo
The output of NAND12 is high because the signal level at the
Level, so input A of NAND14 is at a high level.
It is. Both inputs to NAND14 are high
The output of NAND14 is low, which causes the CC3
Box 36's selector input goes low,
The bank frequency is selected. Selected by CC3 Max 36
The supplied S clock signal is provided to the circuit of the device 10 on the line L232.
(FIGS. 5A, 5B and 5C). M clock signal
The signal is sent to the fixed program decoder 20 via a line (not shown).
Provided. 4A and 4B are described above with reference to the frequency of the device 10.
Includes the operation of the division and frequency selection circuit. next,
Referring to FIGS. 5A, 5B and 5C, the order of the apparatus 10 will be described.
The ordering and digitizing operation will be described. Figure 5A
For reference, the scanner input 22 is a multiple of the four scanners.
Multiplexer 64 to select one of the inputs
It has. Each scanner input has its own scan
Signal from the control device. There are various types of
Scanner inputs are provided. Input 0, input 1 and input
Select A is for the 28-pin configuration of device 10.
You. Input terminals 2, 3 and input select B (shown in parentheses)
Is used only for the 40-pin configuration. Input terminal
0 and 1 are connected to terminals IC0 and IC1 of input max 64, respectively.
It is connected. Input select A terminal is the end of Max 64
It is connected to child A. When input select A is low
In this case, the IC0 signal appears on the output IY of the Max 64. input
When select A is high, the signal at IC1 is
Appears on output IY. In the case of a 40-pin package, input terminal IC2 is directly connected to input 2.
The terminal IC3 is directly connected to the input 3.
Input select terminal B is connected to terminal 64 of Max 64
I have. Input select B is low and input select
If input A is also low, the input of IC0
Appears at output terminal IY. When input select A is high level,
If force select B is low, signal at IC1
Appears in the Max64 output IY. Input select A is low
Level and input select B is high, IC
The signal at 2 appears at output terminal IY. Finally, enter
If both rects A and B are at high level,
The signal appears at the output of the Max 64 at terminal IY. The output of the multiplexer Max 64 is
Channel information and provide this information to the transition detector 45,
Start processing the input data and change the barcode symbol
Determine the occurrence of a transfer. This transition detector 45 is the main sequencer
42 to provide a signal indicating the occurrence of a detected symbol transition.
Offer. This transition detector 45 is basically a pair of inverters.
Data I16, I18, flip-flop FF6 and NAND18, NAN
It has three NAND gates D20 and NAND22.
Scanner input 22 is connected to terminal D of flip-flop FF6,
The input of the inverter I16 and the input B of the NAND gate NAND18
appear. Flip-flop FF6 is connected to its clock input.
Clocked by the signal received from the main sequencer.
Do not change its state until it is Called "commit" signal
The generation of the signal to be performed will be described below. The operation of the main sequencer circuit 42 is as follows. Normal,
Low level from NAND22 Is given to the sequencer 42. this Sets the four outputs Q1-Q4 of sequencer 42 to low level
You. Flip flip connected to input B of NAND gate NAND20
FF6's Q output is high and on FF6's D input
Assuming that the emerging scanner input signal is low
Output of inverter I16 connected to input A of NAND20
The pin goes high. Therefore, NAND20 is enabled
And its output connected to input A of NAND gate NAND22
Goes low. As a result, the output of NAND22 is at a high level.
To the main sequencer 42 And the sequencer 42 is closed by the line L232.
Be operable with the lock signal. As another form, the output pin of FF6 (input A of NAND18)
Is high) and the scanner input signal
Signal (provided on NAND18 input B) is at a high level
Enabled, NAND18 is enabled and its output is low.
Becomes Thus, when the input B of NAND22 goes low,
A high level signal appears on the output pin and the output pin is
Connected to clear input of KENSA42. Thus, the sike
The sensor 42 is activated (enabled) again. Therefore,
The force signal transitions from high to low (i.e., space or
Transition from bar to bar) or from low to high level
(Ie transition from bar to space)
From the main sequencer 42 Is removed. this Is removed, each clock input to the main sequencer 42
Causes the sequencer to perform the following eight steps one after another
move on. That is, Q1-high, Q2-high, Q3-high, Q4-high, Q1-
Low, Q2-low, Q3-low and Q4-low levels. The operation order is as follows. The first clock pulse after signal removal removes the sequencer
The output Q1 of 42 goes high. This signal is coupled to terminal D2
Is done. This operation activates the main sequencer 42,
The output Q2 becomes high level by the clock pulse.
Output Q2 is connected to input terminal D3. Thus, the output Q2 is high
When the level is reached, the main sequencer 42 is prepared and
Force Q3 goes high on the next clock pulse. Likewise
Thus, the output Q3 is connected to the input terminal D4. Thus, output Q3
Goes high, input D4 goes high,
As a result, the main sequencer is prepared and at the next clock pulse,
Its output Q4 goes high, output Q4 goes high
And its complementary output ▲ ▼ connected to terminal D1 is low.
Become a level. As a result, D1 becomes lower and the main sequencer
42, and the next pulse lowers its output Q1.
So that When Q1 goes low, D2 goes low and the primary
The Ken 42 is prepared and its output is output at the next clock pulse.
Make Q2 low. When Q2 goes low, D3
Low level, thus preparing the main sequencer 42,
Its output Q3 goes low on the next clock pulse
To When Q3 goes low, output D4 also goes low,
Q4 goes low at the clock pulse. The above "commit" signal is the fourth signal to the sequencer
Is generated when the clock is input. This fourth clock
Complementary output ▲ ▼ becomes low level by pulse input.
Low, the input of the inverter I18 of the transition detector 45 is low.
Level is added, and the output of inverter I18 is set to a high level.
I do. This output is the clock input of flip-flop FF6.
Connected to it and make it high level. flip flop
The signal level at the Q output of FF6 is the fourth in the sequence
It doesn't change until the count of is over. So this is raw
The signal at the Q output of flip-flop FF6
The level indicates the state of the input signal before the transition. transition
Detector 45 enters bar code until after 4th clock pulse
Reasons for not responding to force transitions are short signals (eg,
This is to prevent operation with a noise signal.
Input signal before the sequencer reaches its fourth count.
If the signal returns to its previous state, NAND20 or NA
ND18, together with NAND22, will be connected to sequencer 42 Is added again so that resetting is performed. Scratch
Thus, short "noise" signals are ignored. However, sequencer 42 has reached the fourth count.
If the low level Is applied to the input C of the NAND 22 to force the sequencer 42
So that all eight steps are completed. As described below, the Q output of flip-flop FF6
Power is provided on line L225. This signal is the input before the transition
Indicates the state of the signal and is provided to a "sign" circuit 46. this
The circuit is a bar, as described below with respect to FIG. 5B.
Or record which of the spaces was present. Next, referring to FIG. 5B and FIG.
Details and operations of 0 and 52 will be described. Each counter is line L23
Count the input clock pulse provided by 2
Requires four high-level signals
Call These are the "load" and And the two inputs EP and ET for “Start count”.
You. Also, in order to provide stable count data,
The counter operates the main and FIFO sequencers 42 and 44 respectively.
Have to be stopped while doing. After count 1 of the main sequencer, the main sequencer 42
▼ is low level. This signal is signaled by line L227.
Connected to both EP inputs of
Stop counting. Sequencer counts 4
After that, the ▲ ▼ of the main sequencer 42 becomes a low level. This
Signal is coupled to the ET input of counter 50 by line L219,
The counters 50 and 52 are further deactivated. Sequencer is mosquito
At und 5, the line L2 is output from the ▲ ▼ output of the main sequencer 42.
Reset the high level signal on 27, but beforehand on line L219
Since the set low level signal exists, both counters 50,
52 cannot be counted. After the sequencer counts 7, as described below
Then, a low-level signal is set on the line L240. this is
Affects the load and clear input of each of counters 50 and 52
Effect. After the sequencer counts 8, the main sequence
High level signal on line L219 from the output of sensor 42.
Set, but the counter still has a low level signal on line L240.
Does not count because the issue exists. Instead, it
Perform the load and clear functions described below.
Forced. At count 9, high level signal on line L240
Is set, and counters 50 and 52 count at count 10.
To start. The counter is the sequencer count 2 to 9
It turns out that it is stopped during. This suspension is of duration
Equivalent to 8 clock pulses or counts at a point. these
Load circuit 48 is required to reset the eight counts.
Is required. Next, referring to FIG. 5B, referring to FIG.
Kensas 44, FIFO reset circuit 54 and "sign" circuit 46
Will be described. The purpose of the load circuit 48 is to
Preset (load) 8 count values for the counter 50
It is to be. The reason is, as mentioned above, the counter
Means that eight clock counts do not occur after the detected transition
Because it does not start until it starts. Load circuit 48 is a basic NAND
It has a gate NAND24 and a flip-flop FF8.
This flip-flop FF8 generates an instruction signal,
The counter 50 is pre-loaded at the count 8 of the Kensa. Or
Therefore, the input A of the NAND gate NAND24 is connected to the main system via the line L228.
Connected to the ▲ ▼ output of sequencer 42. Count 6
Therefore, the ▲ ▼ output goes to a high level,
Input A also goes high. Main sequencer 42 by line L231
The input B of the NAND24 connected to the Q4 output of the
High level at 6. Therefore, the output of NAND24 is low.
Connected to the D input of the flip-flop FF8. next
When a clock pulse occurs, ie, count 7
The Q output of FF8 goes low. This allows
“Load input” of the counter 50 is activated. Next clock
At the time of pulse, that is, when the count reaches 8, the counter
A load occurs. Therefore, “1” is connected to + 5V.
The following input D is applied to the counter. Input A, B
And C are grounded, so the lowest level 3
At one bit position, "zero" is added to the counter.
Therefore, the counter is provided with a binary signal equivalent to decimal number 8.
Provided that the main sequencer 42 lost eight
Configure the count value. Setting the count value 8 to the counter 50
The low level signal on line L240, which allows
The counter 52 is cleared as described when
It also provides input for rearing. Sequencer Cow
After the point 8, the output of the NAND 24 is output from Q4 of the main sequencer 42.
Is high because the line L231 is low. C
At the count of 9 of the Kensa, the counter 50 is again a decimal number
A binary signal equal to 8 is provided. Then from NAND24
Since the signal applied to the D input is at a high level,
The Q output of the flip-flop FF8 becomes high level. This
The line L240 becomes high level and the counter 50, 52 , Respectively, to complete the process of the load circuit. Next, the operation of the “sign” circuit 46 will be described. this
The encoding circuit 46 has a flip-flop FF10. Cow
Q3 output of main sequencer 42 at high level
This signal is sent to flip-flop FF10 by line L229.
Provided. The “sign” in the previous interval (this
The type of the signal, i.e. indicating a bar or space) is indicated by line L2
25, connected to the D input of flip-flop FF10
You. Thus, when the clock input of FF10 goes high,
The flip-flop is activated to output the D input signal level to Q output.
Transmit to force. Low level at Q output of FF10 on line L241
Signal indicates that the previous interval was a bar and L2
The high level signal on 41 was a space before it
Indicates that Described below when describing FIG. 5C
"Sign" information on line L241 is programmable
The information is transmitted to the FIFO part of the processor 26. FIFO sequencer 44 And this signal is
The FO receives the count and “sign” data from device 10
Allows you to get rid of it. This programmable processor
The processor 26 operates asynchronously with the device 10 so that the
The input A is connected to the FIFO memory or the buffer described above.
(Buffer) device (not shown). FIFO Sea
The Ken 44 controls the writing of data into the FIFO buffer.
Basically, flip-flops FF12, FF14, FF16 and
The NOR gate 6 is provided. The operation of the FIFO sequencer 44
When the Q4 output of Kensa 42 goes high on line L231
Start. This sequencer then has 7 clock cows.
FIFO reset until the value reaches the count value, that is, until the count reaches 11.
Runs continuously unless interrupted by circuit 54. line
L231 is connected to terminal D of flip-flop FF12.
You. Terminal D of flip-flop FF12 goes high
Later, the next clock input causes the flip-flop to
The Q output operates to a high level. This output is NO
Connects to input A of R-gate NOR6 and pulls it low.
You. This low level signal appears on line L243, Is configured. Program for "count" and "sign" information
The transmission to the processor 26 is done with line L243 again high.
It is performed when it becomes. From NOR6 Is also connected to the D input of flip-flop FF16. next
At the time of clock pulse, that is, at the time of count 6, flip
The flop FF16 is activated and its Q output has a low level signal.
appear. This signal is provided to latch 56 by line L258,
Activate the latch as described below. In addition,
At the point 6, the flip-flop FF14 is activated.
And its output terminal Q goes high. During normal operation, this set of states is triggered by a clock pulse.
8 and continues until line L231 goes low. next
At the time of the clock pulse, that is, at the clock 9, this low level
The signal reaches its Q output via FF12 and follows the operation of FF14.
Be prepared. At clock pulse 10, low level signal is FF
14 and appears at its Q output. At this time, NOR gate N
Inputs A and B of OR6 are both low, so that
Output goes high, and therefore on line L243 Ends. At clock pulse 11, high level from NOR6
Signal goes through flip-flop FF16 to its Q output
Transmitted to the latch 56 via the line L258.
You. This high level signal latches, as described below.
Deactivate. This is the sequence of the normal FIFO sequencer 44
Is completed. Next, the FIFO reset circuit 54 will be described. this
The circuit is basically NAND26, NAND28, NAND30, and Inver
It has a I20. The purpose of circuit 54 is Is applied to the circuit via line L233, Is to end. This circuit also Is incorrect or inappropriate after it has been removed Is prevented from occurring. Normally, the output from NAND26 is high.
It is a bell. The line carrying L233 is usually at a high level. This is the output of NAND28
Reduce power to low level. This signal is output by inverter I20.
Inverted to produce a high level output on line L246,
Outputs FF12, FF14, and FF16
It can operate in the usual manner as described above. NAND 30 is connected to main sequencer 42 by lines L230 and L219.
Have been. This main sequencer 42 counts 3 to 7.
At some point, either or both lines L230 and / or L219
The output of NAND30 is high level
It is. To show the operation of FIFO reset 54, the main sequence
Assume that sensor 42 is at count 6. Usually line L2
On 34 Occurs at this point. But, Is received on line L233 at input B of NAND28, this
The operation causes the output of NAND 28 to go high. This signal
And a high level signal from NAND30 forces the output of NAND26.
Level, and this signal is then
Constant high-level output of NAND28 regardless of state
To hold. This behavior occurs on line L233 Is incorrect or improper if the Is prevented from occurring. High level signal from NAND28 output
Is inverted by inverter I20, so line L246 is low.
Level. If this occurs, the flip-flop FF
12, FF14 is reset through its clear input,
Are both low. On the other hand, this
This forces a low level signal on inputs A and B of NOR6
Causes the output to go high. This immediately
Supplied by NOR6 on line L243 To end. The low level signal on line L246 is also the flip-flop FF16
To the preset input and its output Q to a high level
I do. High level signal on line L256 deactivates latch 56
(Fig. 5C). The circuits 44 and 56 are controlled by the main sequencer 42.
This state is maintained until und 8 is reached. At this time, NAND
30 inputs are both high and their outputs are low.
To This low level output is coupled to NAND26,
Turn the 26 output to a high level. At this time, the line L233 is also high
If it is a level, ie If no is present, both outputs to NAND28 are also high.
Which causes the output to go low. This signal is
The output is inverted by the barter I20 to a high level, and the line L
Reset status given to FIFO sequencer 44 through 246
Release your condition. But line L233 is still at low level
In some cases, Is still active, the output of NAND28 goes to a high state.
Maintained by inverter I20 to circuit 44 through line L246
The applied reset state means that line L233 will eventually be high
It is in a low level state until. At this time, on line L24
The reset state ends. The outputs QA, QB, QC, and QD of the counter 50 are line L250, respectively.
Connected to L251, L252, L253. These signals are 8-bit
4 represents the least significant 4 bits of the digital count value. Cow
Counter 50 carry signal is provided on line L254.
You. The counter 52 counts the most significant 4 bits of the 8-bit count.
The latch 56, the overflow circuit 58, and the overflow circuit.
Operates with the low reset circuit 60. See FIG.5C.
The following describes these circuits. The counter 52
The flip-flop FF8 of the load circuit 48 is activated and
When enabling the load input of
Cleared by the low level signal that appears. This low level
Signal appears in the sequence of count 7, and the counter
Rear occurs at count 8. Enable counter 52
The input EP is counted 5 and the main sequencer ▲ ▼
It is activated (enabled) when it goes high.
A high level signal appears on line L227. ET input
On the line 254 appearing at the carry output terminal CY of the
Triggered by the "Lee" signal. Load input terminal
LD is not activated because it is connected to + 5V. Outputs QA, QB, QC and QD to counter 52 are input D of latch 56
4, connected to D5, D6, D7. Normally, the latch is LE
High level signal at input deactivates and data is
Switches from input D0-D7 to output Y0-Y7 respectively
Flows. However, the latch is
When more activated, this flow is interrupted, and
When this is activated, outputs Y0-Y7 are
It is held or "latched" in the current state. Line L250,
The output of counter 50 on L251, L252, L253
Appear at the input terminals D0, D1, D2, D3 of the switch 56. Counter 50
The 4-bit count output is also provided by output terminals IC0 and I0 respectively.
Lines L250, L251, L252, L253 connected to C1, IC2, IC3
Via an external fixed program decoder 20. The transition signals TRANS and VIDEO signals are respectively connected to lines L224 and L223.
Through to an output terminal for the decoder 20. TRAN
The S signal is generated at the count 4 of the main sequencer 42,
Signal. It is clear when you look at Figure 5A
As such, the TRANS signal is provided by the output of inverter I18.
You. The VIDEO signal on line L233 is the output of flip-flop FF6
The signal that appears at the terminal
Complement of the "sign" signal appearing on the Q output (complementary
No.). Programmable Processor 26 FIFO
The “sign” signal is a low level signal when the symbol is a bar.
If the symbol is a space while it is a
Issue. In the VIDEO input of the fixed program decoder 20
Signal and the "sign" input to the processor 26 FIFO
Is a bar or space before the transition just completed
Indicates which of The "carry" signal of counter 52 is provided at its CY output
D of the flip-flop FF18 of the overflow circuit 58
Connected to input. The counts in counters 50 and 52 are
When a bar overflow occurs, that is, at the terminal QD of the counter 52,
When the most significant bit changes from 1 to zero
The 52 "carry" signal terminal goes high. This
Flip-flop FF18 is activated and immediately flip-flops
A low level signal appears at the output of the flop FF18. This message
The signal is provided to the preset input PRE of the latch 56. The low level signal that appears at the PRE input is the output of latch 56.
The counter value of all ones on terminals Y0-Y7 is maintained. So mosquito
Counters 50 and 52 reach the maximum value of 255.
When the circuit 58 indicates, this count value is the output of the latch 56.
Maintained in To the FIFO of the programmable processor 26 when an error occurs
Is done. The reason for such an arrangement is that
Sessa 26 can handle more than 255 count values
Because it has an 8-bit microprocessor
is there. Flip-flop FF8 of load circuit 48 is flip-flop
Provides a low level signal on line L240 to the input D of the FF20
At this time, the overflow reset circuit 60 operates. next
Overflow reset circuit 60 by clock pulse
Flip-flop FF20 operates. As a result,
The flip-flop FF20 operates. This allows flip flip
A low level signal is provided to the output terminal Q of the FF20.
You. This output is the clear input of flip-flop FF18.
Connected to child C. This is the overflow circuit 58
Clear lip flop FF18 and set latch 56
Eliminate cut input. The output signals Y0-Y7 on the latch 56 are line L261 through line L, respectively.
268 to the FIFO in the programmable processor 26
Can be As mentioned above, FIFO is Digital count information and digital data at terminals LC0-LC7
Receive a signal indicating the "sign" of the binned interval. Apparatus 10 can consist of standard, commercially available parts.
You. For example, as described above, the fixed program decoder 20
National cash register integrated circuit chip, model
The number 6-1005415 / NCR-8415 can be used. As well
, NAND gate, NOR gate, inverter, counter,
All other circuits of the device 10, such as flip-flops etc.
Consists of standard off-the-shelf components or custom VLSI
Can be manufactured as chips. As is clear from the above description, the digitizer /
The sequencer device 10 is, for example, a wiring integrated circuit chip.
To provide UPC code to such fixed program decoder
Allows you to enter multiple barcodes, including UPC codes.
Through a programmable processor with a FIFO input.
Can operate on UPC and other codes
You. In addition, the device can scan data from various types of scanners.
Can be applied to a wide range of fields as long as
is there. That is, it is derived from the bar symbol and the space symbol
Perform processing on data (equivalent to or equivalent to data)
I can. Finally, the slot model, hand-held model, light pen or
Bar code scanners, whether or not
A preferred embodiment of an apparatus for processing data obtained from
As described above, those skilled in the art will recognize that this device
Data reader, such as a magnetic card reader.
To process data from other "scanner" devices
It will be appreciated that it can be used. For this purpose
To read data recorded on certain media
A magnetic card that provides a digital output signal indicating
A reading device or other equipment or device
Generally referred to as a “scanner”. The present invention is an apparatus for processing barcode data.
To decode the data by different means.
Therefore, check the accuracy of the digitization of the decoding
Provide a device that can perform (cross-check). Device for processing barcode data and other code data
And converts the data using a variety of digitizing frequencies.
Provide a device that can be digitized. Bars supplied from various barcode scanning devices
-A device that processes code data,
An apparatus for processing is provided. A device that processes bar code data,
Decoding the data by means of a stage
Data accuracy can be checked
Provide equipment. A device that processes bar code data,
Digitizing the data using a digitizing frequency
Provide a device capable of Bars supplied from various barcode scanning devices
-A device that processes code data,
An apparatus for processing code data is provided. Bars supplied from various barcode scanning devices
-A device that processes code data,
An apparatus for processing code data is provided. Bars supplied from various barcode scanning devices
-A device that processes code data,
An apparatus for processing code data is provided. A device that processes bar code data,
Digitizing the data using a digitizing frequency
And the most efficient frequency for processing specific data
Bar code data that is automatically selected for use.
An apparatus for performing data processing is provided. Bars supplied from various barcode scanning devices
-A device that processes code data,
An apparatus for processing code data is provided. According to the configuration of the present invention, different types (various types)
All necessary processing required by the scanner in one device
There is an effect that can be performed with. Without further explanation, from the above explanation, the current or future
By utilizing the knowledge of
Can be modified and applied to be suitable for use below
It will be completely understood.

Continuation of front page (56) References JP-A-57-172478 (JP, A) JP-A-58-12073 (JP, A) JP-A-58-4486 (JP, A) JP-A-52-119023 (JP, A) , A) JP-A-60-7524 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06K 7/10 G06K 7/00

Claims (1)

(57) [Claims] Provide at least one barcode scanning means
At least a first scan provided by the first input means;
A first digitizer containing data representing the scanned barcode.
A processing device for processing input data
The bar code to be provided has a bar symbol and a space symbol.
The processing device comprises at least one additional input means.
Receives the second digital input data provided by
Wherein the second digital input data is a second digital input data.
Data representing the bar symbol and space symbol of the barcode,
Or equivalent to bar and space symbols that represent other information
Processing device for processing digital input data, including data
In one of the symbols in response to the input means,
A first digital signal which detects and represents the transition to the other
Circuit means for providing a symbol, and a second digit representing the width of the bar symbol and the space symbol.
Means for providing a taller symbol, each of said symbols being a bar symbol or a space
Means for providing a third digital symbol indicating whether the input means is a signal.
And any one of the first or second digital input data
Selectable means for selecting the first, second, and third circuit means in the first decoder means.
Providing a third digital signal and before the second decoder means;
Providing second and third digital signals, wherein the first decoder means is configured in a non-programmable manner.
And converting the first, second and third digital signals to the
Decode to an output signal that represents the barcode 1
Wherein said second decoder means comprises said second and third digital signals.
With the second barcode or other digital information.
Can be programmed to decode
Digital input data, characterized in that
A processing unit that processes. 2. The programmable decoder is the processing unit
Receiving the first digital signal and the second digital signal from the
As shown, the first-in first-out buffer memory means
Preparing for the input;
On-board processing equipment. 3. Perform a sequence of processing unit operations
Claim 2 further comprising means.
A processing device according to the item. 4. One of the barcode scanning means is a barcode scanner.
A can device, wherein said additional input means is at least
Provide another barcode scanning device or another scanning device
2. The processing device according to claim 1, wherein
Place. 5. At a minimum, a scanned barcode or other scan
Data containing digital data representing the scanned code symbol.
A processing device for processing digital input data, wherein
Digital data is at least one input means of a specific type
Is provided as an output signal and the digital data is
Including symbols and space symbols or their equivalents
And on a certain medium read by the input means
The frequency of the output signal of the input means is recorded.
Of the type of force means and the resolution of the symbol recorded on the medium
Function with change or its equivalent, or before said input means
Changes in the format or resolution of the symbols recorded on the medium.
Digital input data, which is a function of
Means for generating a plurality of internal frequencies, and optimizing processing of the output signal from the input means.
Of the plurality of frequencies for use by the processor for processing.
1 and the operation of the processor is selected.
Processing the digital input data, comprising: selecting means for performing timing.
Processing equipment. 6. First decoder means for receiving the processed signal
Wherein said selecting means comprises a second frequency of said plurality of frequencies.
To perform the timing of the first decoder means,
The processing apparatus according to claim 5, wherein: 7. The first decoder means converts a first type of bar code
Has a fixed program inside to decode
7. The processing device according to claim 6, wherein
Place. 8. Second decoder means for receiving the processed signal
Wherein said second decoder means comprises a second type of bar code.
Or to decode other digital codes
Claim 5 characterized in that it is possible to
On-board processing equipment. 9. The second decoder means includes a first-in first-out buffer memory.
It has a memory and operates asynchronously with the processing unit.
The processing device according to claim 8, wherein 10. The means for generating a plurality of frequencies includes a reference input frequency.
Means for providing a wave number; and
And a plurality of frequency dividers for dividing.
The processing apparatus according to claim 8, wherein 11. The first and second frequencies of the plurality of frequencies are
Said means for selecting comprises a plurality of multiplexing means.
The programmable decoder means comprises:
Selecting said first and second frequencies of frequencies
Providing a control signal to the multiplexing means.
11. The processing apparatus according to claim 10,
Place. 12. Digit representing at least the scanned barcode
Data and at least one other digital code
Process digital input data, including representing digital data
Wherein the digital data is at least
Also scans the bar code for a particular type of first scan.
Output means by the scanning means and the second scanning means.
Means for processing the output signals from both of the scanning means.
And the processing means outputs the output signals of both the scanning means.
Processing the bar code and the other digital code
At least one decoder hand to decode the code
The stage has a common circuit for providing a processed output signal.
Processing device for processing digital input data, comprising:
Place. 13. The first scanning means is a desktop scanner,
C scanner, light pen scanner or wand scanner
Claims selected from the group consisting of:
13. The processing apparatus according to claim 12, wherein 14． The second scanning means is a desk-top scanner,
C scanner, light pen scanner or wand scanner
Claims selected from the group consisting of:
14. The processing apparatus according to claim 13, wherein 15. The second scanning means is a magnetic card reader
14. The process according to claim 13, comprising:
apparatus. 16. The decoder means comprises a program fixed inside.
A first decoder having a system and a second
And a decoder.
A processing device according to the item. 17． A bar symbol provided by the first input means;
A first code consisting of a binary code having a space symbol
A processing device for processing digital input data representing symbols.
And a second code provided by the second input means
Receive the second digital input data representing the binary symbol of
A processing device adapted to respond to each of the first input means and the second input means.
To select digital input data from any of the input means.
Selectable circuit means for selecting the binary symbol of the code of the selected digital input data
The digital symbol selected from the binary symbol of one of
To other binary symbols among binary symbols of input data code
A first digital signal that detects each transition of
Means for providing a binary code of a code of the selected digital input data
Providing a second digital signal indicating the time between said transitions
Means for performing each of the symbols on the selected digital input data.
One binary symbol of the data code or the other binary symbol
Means for providing a third digital signal indicating whether or not the input means is any of the input means.
The selectable circuit means is used for processing the first, second and third digital signals.
Signal to the first decoder means and the second and second
Three digital signals to a second decoder means, said first decoder means being non-programmable;
Converting the first, second and third digital signals into the first code
Wherein the second decoder means is configured to decode the second and third digital signals.
Signal to an output signal representing the second code.
A processing device characterized by being configured to be programmable. 18. The programmable second decoder comprises a processing device
From the first digital signal and the second digital signal
First-in, first-out buffer memos on that input to receive
Claim 17 characterized by including
On-board processing equipment. 19. Executes a sequence of processing unit operations
Claims further comprising means for:
Item 18. The processing device according to Item 18. 20. The first input means includes a bar code scanning device.
The second input means comprises a scanning device.
18. The processing device according to claim 17, wherein the processing device is characterized in that: 21. Processing device for processing multiple digital input signals
Wherein each of said digital input signals is at a first level and
Having a second level and at least one input means;
Provided to the leverage processing device, wherein each said digital input signal is
A core recorded on a medium read by the input means.
Code, and each digital input from the input means.
The frequency of the force signal is recorded on the type of the input means and the medium.
Processing, which is a function of the resolution of the recorded code symbol
In the apparatus, frequency generating means for generating a plurality of predetermined frequencies, and using one of the plurality of predetermined frequencies
The first and second levels of the digital input signal
Measure each time period of and the code symbol
Measurement for use by decoder means for decoding
Means for generating digital data representing said time period
A processing device, comprising: 22. The decoder means receives the processed signal
And a processing unit, wherein the plurality of predetermined
Using the second frequency of the frequencies
Claims:
A processing device according to item 21. 23. The first decoder decodes a first type barcode.
Includes fixed programs in it for coding
23. The processing device according to claim 22,
Place. 24. A second decoder for receiving the processed signal.
A second type of bar code or other digital code
Second decoder programmable for decoding
The method according to claim 21, wherein
Processing equipment. 25. The second decoder has a first-in first-out buffer memo.
And operate asynchronously with the processing device.
25. The processing apparatus according to claim 24, wherein 26. The frequency generating means provides a reference input frequency
A plurality of means for continuously dividing the reference input frequency.
Frequency division means.
Item 24. The processing device according to item 24. 27. Further comprising a plurality of multiplexing means;
The programmable decoder comprises:
And selecting the first and second frequencies of
Providing a control signal to the multiplexing means.
27. The processing device according to claim 26, wherein
Place. 28. The input means is a desk-top scanner, a hand-held scanner.
Scanner, light pen scanner, wand scanner, and magnetic
Claims selected from the set comprising a reader
22. The processing device according to item 21. 29. The digital code is decoded to decode the code symbol.
Processing means for processing data, including
The method according to claim 21, wherein:
Processing equipment. 30. A digital signal that can decode multiple digital data signals
Signal processing device, wherein each of the digital data signals
Are generated as output from the scanning device and
Barcode scanned by the scanning device
The first of a variable time period following a signal level transition according to the symbol
Digital signal processing device having first and second signal levels
(A) a plurality of data input ports, wherein each of the data
The input port can be connected to one of the scanning devices
Yes, one to one data input port to process
A plurality of data providing one said digital data signal
(B) supplied to any of the plurality of data input ports
Transition of the signal level of the digital data signal
And a signal signal for the supplied digital data signal.
Signal level transition detection means for generating bell transition data
And (c) detecting the signal level transition of the data input port.
Connection means for connecting to the means; (d) detection in the supplied digital data signal
Said first and second signals during a transition of the signal level
Measure the time period of the level and
Of the first and second signal levels in the data signal
Common tags that generate digital data related to time periods
(E) a signal generated from the signal level transition detecting means
In response to the level transition data, the common timing means
Common control means for controlling operation; (f) associated with said common timing means and provided
Processing said digital data from the obtained digital data signal.
Common data processing means programmed to manage
Before generating the supplied digital data signal.
The barco scanned by the scanning device
Generate decoded symbol data representing the code symbol
(G) a data output port associated with the common data processing means;
The decoded symbol data is
To provide to a host device connectable to the data output port
And a data output port. 31. The plurality of digital data signals are at least a first
And a second digital data signal, wherein the plurality of data
Data input ports are at least first and second data input ports.
The first data input port is connected to the first data input port.
The first digital data generated by the canning device;
Receiving the first digital data signal.
The scanning signal is scanned by the first scanning device.
The bar and space of the connected barcode symbol respectively.
31. The digital signal processing device according to claim 30, having a first and a second signal level to represent. 32. The second data input port is connected to a second scan port.
The second digital data signal generated by the signaling device
And the second digital data signal
Is scanned by the second scanning device
First and second signal levels representing bar code symbols
32. The digital signal processing device according to claim 31, wherein 33. A small one of the first and second scanning devices;
At least one is a desktop scanner, a handheld scanner,
Glue including light pen scanner and wand scanner
33. The digital signal processing device according to claim 32, wherein the digital signal processing device is selected from the group consisting of: 34. The common timing means is configured to perform
Means for generating a clock pulse, and generating the digital data.
Counts the generated clock pulses to achieve
31. The digital signal processing device according to claim 30, comprising: 35. The plurality of data input ports, the signal level transition
Shift detecting means, the connecting means, the common timing means,
And the common control means is physically connected to the integrated circuit device.
The digital signal processing device according to claim 30, wherein the digital signal processing device is realized by: 36. The common data processing means and the data output port
Is physically controlled using a programmed microprocessor.
And the programmed microprocessor
The data is integrated with the digital data for processing.
Microprocessor programmed from circuit device
36. The digital signal processing device according to claim 35, wherein the digital signal processing device is connected to the integrated circuit device so as to be transferred to the integrated circuit device. 37. The plurality of data input ports, the signal level transition
Shift detecting means, the connecting means, the common timing means,
And the common control means is physically connected to the integrated circuit device.
33. The digital signal processing device according to claim 32, wherein the digital signal processing device is realized by: 38. The common data processing means and the data output port
Is physically controlled using a programmed microprocessor.
And the programmed microprocessor
The data is integrated with the digital data for processing.
Microprocessor programmed from circuit device
38. The digital signal processing device according to claim 37, wherein the digital signal processing device is connected to the integrated circuit device for transferring the data to the integrated circuit device. 39. A digital signal that can decode multiple digital data signals
Signal processing device, wherein each of the digital data signals
Are generated as output from the scanning device and
Barcode scanned by the scanning device
The first of a variable time period following a signal level transition according to the symbol
Digital signal processing device having first and second signal levels
(A) a plurality of data input ports, wherein each of the data
The input port can be connected to one of the scanning devices
Yes, one before the data input port to process
Multiple data input ports to provide digital data signals.
(B) associated with each of said data input ports, and
The digital data supplied to any of the data input ports.
Transition of the signal level of the data signal is detected, and the supplied data is detected.
Digital signal and associated signal level transition data.
And (c) detection in the supplied digital data signal.
Said first and second signals during a transition of the signal level
Measure the time period of the level and
Of the first and second signal levels in the data signal
Common data that generates digital data related to time periods
Digital count data generating means; and (d) relating to the common digital count data generating means.
The data from the supplied digital data signal.
Program for processing data, including digital data
Common data processing means, wherein the supplied data is
The scanning device for generating a digital data signal.
Decoding representing the bar code symbol scanned by
Common data processing to generate encoded symbol data
(E) a data output port associated with the common data processing means.
The decoded symbol data is
To provide to a host device connectable to the data output port
And a data output port. 40. The plurality of digital data signals are at least a first
And a second digital data signal, wherein the plurality of data
Data input ports are at least first and second data input ports.
The first data input port is connected to the first data input port.
The first digital data generated by the canning device;
Receiving the first digital data signal.
The scanning signal is scanned by the first scanning device.
The bar and space of the connected barcode symbol respectively.
40. The digital signal processing device according to claim 39, wherein the digital signal processing device has first and second signal levels to represent. 41. The second data input port is connected to a second scan port.
The second digital data signal generated by the signaling device
And the second digital data signal
Is scanned by the second scanning device
Bar code symbol bar and space
41. The digital signal processing device according to claim 40, wherein the digital signal processing device has first and second signal levels. 42. A small one of the first and second scanning devices;
At least one is a desktop scanner, a handheld scanner,
Glue including light pen scanner and wand scanner
42. The digital signal processing device according to claim 41, wherein the digital signal processing device is selected from the group consisting of: 43. The common digital count data generating means includes:
Means for generating a clock pulse at a constant frequency;
Said generated clock to generate digital data.
41. The digital signal processing device according to claim 40, further comprising: means for counting clock pulses. 44. The plurality of data input ports, the signal level transition
Shift detection means, and generation of the common digital count data
40. The digital signal processing device according to claim 39, wherein the means is physically realized in an integrated circuit device. 45. The common data processing means and the data output port
Is physically controlled using a programmed microprocessor.
And the programmed microprocessor
The data is integrated with the digital data for processing.
Microprocessor programmed from circuit device
45. The digital signal processing device according to claim 44, wherein the digital signal processing device is connected to the integrated circuit device for transferring the data to the integrated circuit device. 46. The plurality of data input ports, the signal level transition
Shift detection means, and generation of the common digital count data
41. The digital signal processing device according to claim 40, wherein the means is physically realized in an integrated circuit device. 47. The common data processing means and the data output port
Is physically controlled using a programmed microprocessor.
And the programmed microprocessor
The data is integrated with the digital data for processing.
Microprocessor programmed from circuit device
47. The digital signal processing device according to claim 46, wherein the digital signal processing device is connected to the integrated circuit device for transferring the data to the integrated circuit device. 48. A digital signal that can decode multiple digital data signals
Signal processing device, wherein each of the digital data signals
Are generated as output from the scanning device and
Barcode scanned by the scanning device
The first of a variable time period following a signal level transition according to the symbol
Digital signal processing device having first and second signal levels
(A) a plurality of data input ports, wherein each of the data
The input port can be connected to one of the scanning devices
And one digital input to one data input port.
A plurality of data input ports for providing data signals; and (b) a plurality of data input ports associated with each of the data input ports.
The digital data supplied to any of the data input ports.
(I) a signal level of the supplied digital data signal.
Is detected and the supplied digital data signal is
The signal level that generates the relevant signal level transition data
Transition detection means; (ii) detection in the supplied digital data signal
Said first and second signals during a transition of the signal level
Measure the time period of the level and
Of the first and second signal levels in the data signal
Common tags that generate digital data related to time periods
Common signal processing means including: (c) associated with the common signal processing means and provided
The digital data generated from the digital data signal
Common data processing procedures programmed to process data
Stage for generating the supplied digital data signal
The scanning device scans the
Generate decoded symbol data representing barcode symbols
And (d) a data output port associated with the common data processing means.
The decoded symbol data is
To provide to a host device connectable to the data output port
And a data output port. 49. The common timing means is configured to perform
Means for generating a clock pulse, and generating the digital data.
Counts the generated clock pulses to achieve
49. The digital signal processing device according to claim 48, comprising: 50. The plurality of digital data signals are at least a first
And a second digital data signal, wherein the plurality of data
Data input ports are at least first and second data input ports.
The first data input port is connected to the first data input port.
The first digital data generated by the canning device;
Receiving the first digital data signal.
The scanning signal is scanned by the first scanning device.
The bar and space of the connected barcode symbol respectively.
50. The digital signal processing device according to claim 49, wherein the digital signal processing device has first and second signal levels to represent. 51. The second data input port is connected to a second scan port.
The second digital data signal generated by the signaling device
And the second digital data signal
Is scanned by the second scanning device
First and second signal levels representing bar code symbols
The digital signal processing device according to claim 50, wherein 52. A small one of the first and second scanning devices;
At least one is a desktop scanner, a handheld scanner,
Glue including light pen scanner and wand scanner
52. The digital signal processing device according to claim 51, wherein the digital signal processing device is selected from the group consisting of: 53. The plurality of data input ports and the common signal processing
49. The digital signal processing device according to claim 48, wherein the processing means is physically realized in the integrated circuit device. 54. The common data processing means and the data output port
Is physically controlled using a programmed microprocessor.
And the programmed microprocessor
The data is integrated with the digital data for processing.
Microprocessor programmed from circuit device
54. The digital signal processing device according to claim 53, wherein the digital signal processing device is connected to the integrated circuit device for transferring the data to the integrated circuit device. 55. The plurality of data input ports and the common signal processing
51. The digital signal processing device according to claim 50, wherein the processing means is physically realized in the integrated circuit device. 56. The common data processing means and the data output port
Is physically controlled using a programmed microprocessor.
And the programmed microprocessor
The data is integrated with the digital data for processing.
Microprocessor programmed from circuit device
56. The digital signal processing device according to claim 55, wherein the digital signal processing device is connected to the integrated circuit device for transferring the data to the integrated circuit device. 57. A digital signal that can decode multiple digital data signals
Signal processing device, wherein each of the digital data signals
Are generated as output from the scanning device and
Barcode scanned by the scanning device
The first of a variable time period following a signal level transition according to the symbol
Digital signal processing device having first and second signal levels
(A) a plurality of data input ports, each data input port
A port is connected to one of said data input ports for processing.
To supply one said digital data signal to the
A plurality of scanning devices connectable to one of said scanning devices.
(B) a clock signal for generating a plurality of predetermined clock signals;
Signal generating means, wherein each predetermined clock signal is
The first and at least one of the digital data signals
Suitable for measuring time periods of the second and second signal levels
(C) using one of the plurality of predetermined clock signals.
The first and the second of the supplied digital data signals.
Measuring each time period of the second signal level;
Generating digital data representing said time period,
(D) associated with said timing means and provided
Processing said digital data from a digital data signal
Common data processing means programmed for
Generating the supplied digital data signal.
The bar code scanned by a scanning device
To generate decoded symbol data representing
(E) in connection with the common data processing means,
Symbol data can be connected to this data output port
And a data output port for providing the digital signal processing device to a host device. 58. The plurality of digital data signals are at least a first
And a second digital data signal, wherein the plurality of data
Data input ports are at least first and second data input ports.
The first data input port is connected to the first data input port.
The first digital data generated by the canning device;
Receiving the first digital data signal.
The scanning signal is scanned by the first scanning device.
The bar and space of the connected barcode symbol respectively.
58. The digital signal processing device according to claim 57, wherein the digital signal processing device has first and second signal levels to represent. 59. The second data input port is connected to a second scan port.
The second digital data signal generated by the signaling device
And the second digital data signal
Is scanned by the second scanning device
First and second signal levels representing bar code symbols
59. The digital signal processing device according to claim 58. 60. A small one of the first and second scanning devices;
At least one is a desktop scanner, a handheld scanner,
Glue including light pen scanner and wand scanner
60. The digital signal processing device according to claim 59, wherein the digital signal processing device is selected from the group consisting of: 61. The plurality of data input ports, the clock signal
Generating means, the timing means, and the common data processing;
58. The digital signal processing device according to claim 57, wherein the processing means is physically realized in the integrated circuit device. 62. The common data processing means and the data output port
Is physically controlled using a programmed microprocessor.
And the programmed microprocessor
The data is integrated with the digital data for processing.
Microprocessor programmed from circuit device
62. The digital signal processing device according to claim 61, wherein the digital signal processing device is connected to the integrated circuit device for transferring to the integrated circuit device. 63. The plurality of data input ports, the clock signal
Generating means, the timing means, and the common data processing;
60. The digital signal processing device according to claim 59, wherein the processing means is physically realized in the integrated circuit device. 64. The common data processing means and the data output port
Is physically controlled using a programmed microprocessor.
And the programmed microprocessor
The data is integrated with the digital data for processing.
Microprocessor programmed from circuit device
64. The digital signal processing device according to claim 63, wherein the digital signal processing device is connected to the integrated circuit device for transferring the data to the integrated circuit device. 65. Barcode scanning device and magnetic medium scanning
Generated as output from each of the
And digital decoder capable of decoding second digital data signal
A first digital data signal.
The signal is scanned by the barcode scanning device.
According to the signal level transition according to the bar code symbol
The second digital signal having first and second signal levels;
The data signal is transmitted by the magnetic medium scanning device.
Signal level transition according to scanned digital code
Digital signal having first and second signal levels according to
(A) first and second data input ports, wherein
The data input port of this first data
Supplying the first digital data signal to a data input port.
Can be connected to the barcode scanning device to
Yes, the second data input port is
A second data input port for receiving the second digital data signal;
Contact the magnetic media scanning device to supply the
First and second data input ports connectable to the first and second data input ports;
(I) the common digital signal processing means supplied to the common digital signal processing means.
Detecting a transition in the signal level of the digital data signal,
Signal level transitions associated with the supplied digital data signal
Transition detection means for generating transition data; and (ii) detecting the supplied digital data signal.
Detecting the signal level during the transition of the signal level;
The detected signal level of the detected digital data signal.
Signal level detecting means for generating continuous digital data
And (iii) the signal level generated from the signal transition detection means.
In response to the bell transition data, the signal level detecting means
Control means for controlling operation; and common digital signal processing means, comprising: (c) the common digital signal processing means;
Said digital signal generated from the supplied digital data signal
Common data programmed to process file data
Processing means, wherein the barcode scanning device is
When providing the supplied digital data signal,
Decoded symbol data representing the barcode symbol
Generating, and wherein the magnetic media scanning device is
When providing the digital data signal,
Generate decoded symbol data representing the
(D) in connection with the common data processing means,
Symbol data can be connected to this data output port
And a data output port for providing the digital signal processing device to a host device. 66. The barcode scanning device is a desktop scanner.
Scanners, handheld scanners, light pen scanners, and wireless
66. The digital signal processing device according to claim 65, wherein the digital signal processing device is selected from a group including a scanner. 67. The first and second data input ports and the common
The communication digital signal processing means
66. The digital signal processing device according to claim 65, wherein the digital signal processing device is realized in a logical manner. 68. The common data processing means and the data output port
Is physically controlled using a programmed microprocessor.
And the programmed microprocessor
The data is integrated with the digital data for processing.
Microprocessor programmed from circuit device
67. The digital signal processing device according to claim 67, wherein the digital signal processing device is connected to the integrated circuit device for transferring to the integrated circuit device. 69. The plurality of data input ports and the common digital
Signal processing means is physically realized in an integrated circuit device.
70. The digital signal processing device according to claim 66, wherein 70. The common data processing means and the data output port
Is physically controlled using a programmed microprocessor.
And the programmed microprocessor
The data is integrated with the digital data for processing.
Microprocessor programmed from circuit device
70. The digital signal processing device according to claim 69, wherein the digital signal processing device is connected to the integrated circuit device so as to transfer the data to the integrated circuit device.