JP2771313B2 - IC card and IC card system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention has a built-in IC circuit such as a microcomputer or a memory, and can process and store data.
The present invention relates to an IC card system including an IC card and a reader / writer for writing and reading data in and from the IC card.

[Conventional technology]

The IC card has eight external terminals.
Of these, five external terminals are used. That is,
One for power supply, one for reset signal, one for clock, one for grounding, and one for data communication for driving a microcomputer. When such an IC card is mounted on a reader / writer, each external terminal is connected to an external terminal of the reader / writer. In this state, each IC circuit in the IC card is grounded by the reader / writer via the grounding external terminal, and a power supply voltage is applied from the reader / writer to each IC circuit in the IC card via the power supply external terminal. At the same time, a reset signal and a CPU driving clock of the microcomputer are supplied from the reader / writer to the microcomputer in the IC card via the reset external terminal and the CPU driving clock external terminal, respectively.

For data communication between the reader / writer and the IC card, 1
One bidirectional transmission line is used for each data external terminal, and a communication system using a start-stop synchronization system is employed. This is a transfer data format in which a 1-bit start bit is first, followed by 7 or 8 bits of data, a 0 to 1 bit parity bit, and terminated by a stop bit of about 1 to 2 bits. On the receiving side, the level at the input terminal is monitored, and if a start bit is detected due to a change in the level, a clock having a cycle that matches the bit cycle determined in the data format is generated. To determine the received data, parity, and stop bit.

[Problems to be solved by the invention]

However, when data communication is performed by the start-stop synchronization method, data communication can be performed by a simple method by reducing the number of connection terminals with a reader / writer, but the transmission rate cannot be increased. That is, according to this data communication, the receiving side synchronizes the clock of a fixed period with the edge of the detected start bit, and determines each bit of the received data based on this clock. In the case of transmitting data at a relatively low speed such as the following, there is no problem if the clock cycle and the data bit cycle are almost the same.
When the transmission speed is higher than kbps, a shift easily occurs between them, and a phase difference occurs between the clock and the data bit, which accumulates, and an error occurs in the bit determination.
For this reason, when data communication by the start-stop synchronization method is used, the transmission rate is naturally limited.

Conventionally, the transmission rate between a reader / writer and an IC card is generally 9600 bps. In this case, since the transmission time per bit is about 100 μsec, when data communication is performed by the start-stop synchronization method as described above, the time required to transmit 11-bit data from the start bit to the stop bit exceeds 1 msec. I will. On the other hand, the calculation processing time of the transmitted data by the microcomputer in the IC card is much shorter than 1 msec. As described above, in the conventional IC card system, although the CPU in the IC card can process data at high speed, the data transmission rate has to be reduced, so the data processing speed of the entire system is low. Will be.

Recently, attention has been paid to the application of the IC card system to various systems. The conventional IC card system can sufficiently cope with a system with a low data transmission rate, but cannot cope with a communication system with a high data transmission rate.

An object of the present invention is to solve such a problem and improve the data transmission rate of an IC card and an IC card.
To provide an IC card system.

[Means for solving the problem]

In order to achieve the above object, an IC card according to the present invention is provided with an external terminal for transmitting a clock for data, and a switching means for switching between an asynchronous system and a clock synchronous system, and transmitting data by the clock synchronous system. Sending and receiving is also possible.

Further, the IC card system according to the present invention comprising the above-described IC card and reader / writer ensures that the data and the data clock transmission directions coincide with each other in data communication by the clock synchronization method between them.

[Action]

As described above, the IC card has eight external terminals, but only five external terminals are used.
External terminals are reserved. Therefore, in the IC card according to the present invention, the spare external terminal is used as an external terminal for a data clock so that data communication can be performed by a clock synchronous system.

Further, the data communication means connected to the external terminal for transmission / reception includes switching means for switching between the clock synchronization method and the start-stop synchronization method. It is configured to be able to switch to either one. This switching means is usually formed by program software, but it is also possible to use a logic circuit without using the program software.

The clock synchronization system is a data communication system in which a clock (data clock) phase-synchronized with a bit of the data is transmitted together with the data. Since the data bit and the clock are always synchronized, the clock is used regardless of the transmission rate. Data bits can be determined without error. Therefore, the transmission rate can be greatly increased as compared with the data communication by the start-stop synchronization method.

Also, in the IC card system according to the present invention, when data is communicated in the clock synchronous system, when the reader / writer sends data to the IC card, the data clock synchronized with the data bit by the reader / writer is also synchronized with the IC.
When the IC card sends data to the reader / writer, the IC card also sends the data clock synchronized with the data bit to the reader / writer. According to such a method, data can be sent for the convenience of processing on the data sending side.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an IC card according to the present invention, wherein 1 to 8 are external terminals, 9 is a microcomputer, 16 is a memory, 14 is a data bus, and 15 is an address bus. 10,1
1, 12, and 13 are CPUs, mask ROMs, and RAs stored in the microcomputer 9.
M, interface. The memory 16 is provided with three areas 16A, 16B, and 16C, and the area 16B is an area for storing an application program corresponding to a system such as a communication system to which the embodiment is applied. The area 16A is an area for storing management data indicating whether the application program stored in the area 16B is executable. Also the area
16C is an area for storing data to be stored, similar to a conventional IC card.

In the figure, in the IC card body, the microcomputer 9, E ²
A memory 16 such as a PROM (electrically erasable and rewritable read-only memory), a data bus 14 and an address bus 15 between the microcomputer 9 and the memory 16 and other wirings are embedded, and eight external The terminals 1 to 8 are exposed to the outside in a predetermined shape and arrangement.

The external terminal 1 is a power supply terminal, and is connected to a power supply terminal such as the microcomputer 9 or the memory 16 via a power supply line in the IC card body. External terminal 2 is a reset terminal, IC
It is connected to a reset pulse input terminal of the microcomputer 9 and a reset pulse input terminal of the memory 16 (not shown) via a reset line in the card body. The external terminal 3 is a drive clock terminal of the microcomputer 9 and is connected to a drive clock input terminal of the microcomputer 9 via a clock line in the IC card body. The external terminal 5 is a ground terminal, which is connected to a ground wire in the IC card body.
Ground terminals such as the microcomputer 9 and the memory 16 are connected to this ground line. The above is the same as the conventional IC card. Further, in the conventional IC card, the external terminal 7 is a terminal for data transmission, and is connected to the interface 13 of the microcomputer 9 via a data transmission line in the main body of the IC card. Therefore, in the conventional IC card, the external terminals 4, 6, and 8 are not used as spares.

On the other hand, in this embodiment, as shown in the figure, the external terminal 4 or 6 which is conventionally reserved is used as a terminal for data clock, and when a different data clock is used for transmission and reception, the external terminal is used. 4, 6 may be used independently. In this embodiment, the external terminals 4 and 6 are connected to the data clock input / output terminal of the interface 13 of the microcomputer 9. The external terminal 7 is used as a data transmission terminal and connected to the transmission terminal of the interface 13 in the microcomputer 9 via a data transmission line in the IC card main body. As a receiving terminal, it is connected to a receiving terminal of the interface 13 via a data receiving line in the IC card body.

The microcomputer 9 is, for example, a product of Hitachi, Ltd.
As in the case of HD6301YO, a device that can selectively take the start-stop synchronization mode and the clock synchronization mode is used.

As the reader / writer, one having a data communication function by start-stop synchronization, one having a data communication function by clock synchronization, or one having both functions is used. When the IC card shown in FIG. 1 is mounted on the reader / writer, the external terminals 1 to 8 respectively contact the corresponding external terminals of the reader / writer, and the IC card and the reader / writer are electrically connected. Then, the power supply voltage V _CC from the reader / writer to the IC card via the external terminal 1 is
A reset pulse ▼ is supplied through the external terminal 2, and a driving clock CCLK of the microcomputer 9 is supplied through the external terminal 3. The external terminal 4 of the IC card is connected to the input / output terminal of the data clock SCLK of the reader / writer. Hereinafter, the external terminal 7 is connected to the data receiving terminal of the reader / writer, and the external terminal 8 is connected to the data transmitting terminal of the reader / writer. Connected.

FIG. 2 is a diagram showing data communication of the IC card system according to the present invention comprising the IC card shown in FIG. 1 and the reader / writer, and FIG. 2A shows the case of the start-stop synchronization mode. b) shows the case of the clock synchronous mode, wherein 17 is a reader / writer, 18 is an IC card, 19 is a data clock SCLK transmission line, and 20 and 21 are data transmission lines. Parts corresponding to those shown in FIG. 1 are denoted by the same reference numerals, and a power supply path, a transmission path for reset pulse ▼, and a transmission path for a microcomputer driving clock CCLK are omitted.

In the start-stop synchronization mode, in FIG.
Since the data clock SCLK is unnecessary, the transmission line 19 is not used. When data communication is performed from the reader / writer 17 to the IC card 18, the data _RX is transmitted from the reader / writer 17 to the IC card 18 via the transmission path 21, and data communication is performed from the IC card 18 to the reader / writer 17 side. when the data T _X is sent from the IC card 18 to the reader-writer 17 via the transmission path 20.

As described above, since the data transmission path from one side of the reader / writer 17 and the IC card 18 to the other side and the data transmission path in the opposite direction are provided separately, these transmission paths 20 and 2 are provided separately.
The data transmission in 1 can be overlapped. As a result, in the start-stop mode, the data transmission speed can be increased as compared with the conventional bidirectional data communication using a single transmission line.

In the clock synchronous mode, the data clock SCLK is bidirectionally transmitted via the transmission line 19 in FIG. 2 (b). That is, the IC card 18 is read from the reader / writer 17 side.
When data communication side are on the transmission path 21, as shown by the solid line arrow, IC card data R _X from the reader-writer 17
18 is sent to, and at the same time, the upper data clock SCLK transmission line 19 synchronized with each bit of the data R _X, as shown by the solid line arrow, IC card card reader-writer 17 18
Sent to When data communication is performed from the IC card 18 to the reader / writer 17, data T _X is sent from the IC card 18 to the reader / writer 17 as indicated by a broken line arrow on the transmission path 20, and at the same time, this data data clock SCLK synchronized with each bit of T _X is on the transmission path 19, as indicated by broken line arrows, are sent from the IC card 18 to the reader-writer 17. When data R _X and T _X are not sent, data clock SC
No LK is sent.

In this way, two-way data communication by clock synchronization between the reader / writer 17 and the IC card 18 becomes possible, the data transmission rate can be increased, and application to a communication system having a high transmission rate is possible. In this case, in the clock synchronous mode, the IC card 18 is read from the reader / writer 17 side.
The same transmission path 19 is used for data clock SCLK transmission for data communication to the side and data communication in the opposite direction.
In addition, the data transmission direction matches the data clock SCLK transmission direction. For this reason, reader / writer 17
Data communication from the side to the IC card 18 side and data communication in the opposite direction cannot be overlapped,
Data communication is performed according to the convenience of the data sending side, and the data receiving side will receive and process the data, and the data between the reader / writer 17 and the IC card 18 will be smoothly removed. become.

As described above, in order for the IC card system to be able to perform data communication between start-stop synchronization and clock synchronization, as described above, the microcomputer 9 in FIG. 1 must be able to take the start-stop synchronization mode and the clock synchronization mode. No. further,
As shown in FIG. 1, a serial interface 13 for controlling data communication in the microcomputer 9 is controlled by a data communication control program stored in the microphone ROM 11 or the area 16B of the E ² PROM 16 to start and stop from the reader / writer 17. Alternatively, it is necessary to switch to the mode corresponding to the command corresponding to the clock synchronous mode. In the following, taking the HD6301YO manufactured by Hitachi, Ltd. mentioned above as an example of the microcomputer 9, the main part of the serial communication interface (SCI) 13 will be briefly described with reference to FIG. However, in the figure, 22 is a reception shift register, 23 is a reception data register, 24 is a transmission data register, 25 is a transmission shift register, 26 is a bit rate generator, 27 and 28 are transmission / reception control status registers, and 29 is a rate / mode. This is a control register, and portions corresponding to FIG. 1 are denoted by the same reference numerals.

In the figure, the terminal P ₂₂ of the SCI13 is the serial data clock SCLK that is output through the external terminal 4. The serial data R _X next to the terminal P ₂₃ is inputted through the external terminals 8, the terminal P ₂₄ is the serial data T _X which is output via the external terminal 7.

The transmission / reception control status register 27 is for setting the data format (stop bit length, parity, etc.) in the start-stop synchronization mode, and the transmission / reception control status register 28 is for setting the transmission / reception mode and the like. is there. The rate / mode control register 29 is used to set an operation mode of start-stop synchronization and clock synchronization, a transmission rate, and the like. The bit rate generator 26 generates an internal clock in the SCI or a data clock SCLK in the clock synchronous mode.

 Next, the operation of this SCI will be described.

First, when the start / stop synchronization mode is set by the rate / mode control register 29 and the transmission mode is set by the transmission / reception control status register 28, the CP
The parallel data sent from the U10 via the data bus 14 is temporarily stored in the transmission data register 24, then transferred in parallel to the transmission shift register 25, and conforms to the data format specified by the transmission / reception control status register 27. As shown, start bits, parity, stop bits, etc. are added. The bit rate generator 26 has a rate / mode control register.
An internal clock having a cycle corresponding to the transmission rate set in 29 is generated, and data is serially read from the transmission shift register 25 starting from the start bit in synchronization with the internal clock. This serial data is used as transmission data T _X
It is sent to the reader / writer 17 (FIG. 2) via the external terminal 7.

Further, when the reception mode is asynchronous mode has been set, data Fuo mat according to the received data R _X serial sent via the external terminal 8 is set for transmission and reception control status register 27 from the reader-writer 17 , The transmission rate is set in the rate / mode control register 29. When the reception data R _X is sent, it is detected edge of the start bit, with this detection, bit rate generator at a cycle corresponding to a transmission rate set to a rate / mode control register 29 26
Generates an internal clock. Receiving data R _X serial in synchronization with this internal clock is stored in the receive shift register 22. After data Fuo mat of the received data R _X is known Te cowpea the information stored in the transmission and reception control status register 27, connexion by the data Fuo mat is the Pariteichietsuku been performed, the start bit, parity 7 or 8 excluding stop bits
The data of the bit is transferred in parallel to the reception data register 23, after which it is read out from the data bus 14
Is sent to the CPU 10 via the.

Data communication by start-stop synchronization is performed as described above. In this communication mode, the transmission mode and the reception mode are simultaneously set in the transmission / reception control status register 28.
Can be set with.

When the clock synchronous mode is set by the rate / mode control register 29, the transmission / reception control status register 27 is not used, and one of the transmission mode and the reception mode is set in the transmission / reception control status register 28 as described above. . Further, the transmission rate is set in the rate / mode control register 29, whereby the cycle of the clock generated by the bit rate generator 26 in the transmission mode is set. Further, the transmission / reception control status register 28 stores the data clock SC.
Specify the input and output of LK.

In the case of data transmission by clock synchronization, the transmission mode is specified by the transmission / reception control status register 28, and 8-bit parallel data from the CPU 10 is transmitted to the data bus 1.
4, transmission shift register 2 via transmission data register 24
5 is transferred to the transmit / receive control status register 2.
When the output of the data clock SCLK is instructed at 8, the bit rate generator 26 generates eight internal clocks and a data clock SCLK having a cycle matching the transmission rate set in the rate / mode control register 29. In the transmission shift register 25, data of 8 bits in synchronization with this internal clock are read serially one by one bit, are sent to the writer 17 via the external terminal 7 as the transmission data T _X. 8 output from the bit rate generator 26.
The data clocks SCLK are sent to the reader / writer 17 via the external terminal 4.

In the case of data reception by clock synchronization, the reception mode is designated by the transmission / reception control status register 28. When the serial reception data R _X 8 bit via an external terminal 8 from the reader-writer 17 is sent, clock SCLK for synchronization with data to each bit of the received data R _X also
It is sent from the reader / writer 17 via the external terminal 4. At this time, the rate / mode control register 29
Designates the input of an external clock, and the bit rate generator 26 generates an internal clock whose phase is synchronized with the transmitted data clock SCLK in the same cycle. This internal clock, 8 serial reception data R _X of bits is stored in the receive shift register 22, then after being transferred in parallel to the incoming data register 23, is supplied to the CPU10 is read as 8-bit parallel data.

The operation related to the present invention of the SCI13 of the HD6301YO has been described above. In the SCI, the data clock from the reader / writer is also specified by the transmission / reception control status register 27 when transmitting data by clock synchronization.
It is also possible to take in SCLK.

In this way, data transmission is performed in the start-stop synchronization mode and the clock synchronization mode. Switching between the start-stop synchronization mode and the clock synchronization mode is performed by mask ROM in the microcomputer or area in the E ² PROM.
Switching is performed according to a data communication control program stored in 16B and a command transmitted from the reader / writer 17 corresponding to the start-stop synchronization mode or the clock synchronization mode. For such mode switching, a logic circuit can be used in place of the data communication control program as described above.

Next, a description will be given of a receiving system using this IC card so that only the owner of the IC card can receive radio waves broadcast via a broadcasting satellite.

FIG. 4 is a schematic diagram for explaining the broadcast receiving system, in which 30 is a broadcasting station, 31 is a broadcasting satellite, 32 is a receiving device, and 17 is a reader / writer connected to the receiving device.

In this system, information data broadcast from a broadcasting station is encrypted, and when a receiving device 32 receives a radio wave broadcast via a broadcasting satellite 31, an E ² PROM in an IC card 18 is received.
A key for decrypting the encrypted data stored in the area 16B of 16 or a decryption program operates,
The information data from the received radio wave is decoded. at the same time,
The reception fee of this radio wave is recorded in the area 16C of the E ² PROM.

In order to create an IC card corresponding to such a system, a key or decryption program for decrypting the encrypted data in the area 16B of the E ² PROM in the IC card at the broadcasting station is downloaded from a computer such as a personal computer. Is stored. Download of this program
From the viewpoint of simplicity of data communication, data transmission and reception are performed in the start-stop synchronization mode.

On the other hand, in order to load the decryption key or the IC card 18 storing the decryption program into the reader / writer 17 and receive predetermined information data from broadcast waves, the start-stop synchronization mode and the IC card 18 and the reader / writer are used. Initial settings are made between 17 hours. After a lapse of a predetermined time, the communication mode of the IC card 18 is automatically switched from the start-stop synchronization mode to the clock synchronization mode by the mode switching program. Since data communication from broadcast waves is usually performed at a transmission speed of 63 kbps or more, IC
In order to be able to receive data from the card, it is not possible to cope sufficiently unless the clock synchronous mode is used.

As described above, in a broadcast receiving system using an IC card, this request can be sufficiently satisfied by using both the start-stop synchronization mode and the clock synchronization mode.

In the above embodiment, the switching between the start-stop synchronization mode and the clock synchronization mode is automatically performed by the mode switching program after the initial setting. However, the clock is used without using the start-stop synchronization mode from the time of the initial setting. The program may be set to use the synchronous mode, or the mode may be switched from the asynchronous mode to the clock synchronous mode or vice versa by a switching command from the reader / writer. You may.

In addition, the re-switching of the mode is performed automatically by a command of a reader / writer or a program for automatically switching the mode according to a specific procedure, for example, after transmitting a predetermined answer from the reader / writer or an IC card, the mode is automatically switched. It can be done appropriately by using a program.

The IC card according to the present invention can be used for applications other than the above-described broadcast receiving system, and uses a dedicated device for high-speed data communication to which the clock synchronization mode is applied and a start-stop synchronization mode such as a normal banking card. There is an advantage that a single card can be used for both the reader / writer.

The decryption key or decryption program stored in the IC card does not need to be stored in the E ² PROM, but may be stored in the mask ROM.

As mentioned above, although one Example of this invention was described, this invention is not limited only to this Example.

In the above embodiment, the microcomputer including the CPU, the mask ROM, the RAM ', the interface, and the like and the E ² PROM are constituted by independent chips, but these chips are mounted on one chip. May be.

Further, when the IC card system according to the present invention is applied to another communication system, there is a method of storing data transmitted by the communication system in a memory in the IC card. It is also possible to use it in such a way that it is processed by the CPU and then returned to the communication system.

〔The invention's effect〕

As described above, according to the present invention, data communication using the clock synchronization method is also possible, so that the data transmission rate can be greatly increased and its application range can be significantly expanded.

In data communication between the IC card and the reader / writer using the clock synchronization method, the data clock is sent from the data sending side, so the data can be sent according to the convenience of the data sending side. Writer, IC
The removal of data between the cards is performed smoothly.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an IC card according to the present invention, FIG. 2 is a diagram showing an IC card system according to the present invention,
FIG. 3 is a block diagram showing an interface of an example of the microcomputer in FIG. 1, and FIG. 4 is a schematic diagram of a broadcast receiving system using an IC card according to the present invention. 1-8: External terminals, 9: Microcomputer, 16
...... memory, SCLK ...... data clock, T _X ...... transmit data, R _X ...... received data.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takeshi Kimura 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Research Institute (72) Inventor Hiroshi Takamori 1-188 Ushitora 1-chome, Ibaraki-shi, Osaka Hitachi Maxell, Ltd. (72) Inventor Yuji Kodera 1-1-88 Ushitora, Ibaraki-shi, Osaka Hitachi Maxell, Inc. (72) Kenichi Tachibana 1-1-88 Ushitora, Ibaraki-shi, Osaka Hitachi Maxell, Ltd. (58) Investigated field (Int.Cl. ⁶ , DB name) G06K 17/00-19/00

Claims (4)

(57) [Claims] In an IC card which performs data communication with a reader / writer by a start-stop synchronization method, an external terminal for transmitting a clock for data is provided, and either an start-stop synchronization method or a clock synchronization method is provided. Switching means for switching between the start-stop synchronization method and the clock synchronization method to enable data communication.
IC card. 2. A first input / output device for data communication according to a clock synchronous system according to claim 1,
Means for switching between the input / output device of the first embodiment and a second input / output device for data communication using a start-stop synchronization method. 3. The IC card according to claim 1, further comprising a first external terminal for data input and a second external terminal for data output. 4. An IC card system comprising the IC card according to claim 1 and (2) and a reader / writer, wherein the IC card system enables data communication by an asynchronous system and data communication by a clock synchronization system. An IC card system characterized in that, in data communication between the IC card and the reader / writer by a synchronous method, the transmission directions of data and a data clock coincide with each other.