JP2755998B2 - Data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a data transfer device for stopping a component in a computer system, an object of the present invention is to terminate communication with a component without inconsistency when communication is cut off, and to perform communication processing with a lower device. When receiving a command to disconnect communication with the lower-level device, when all communication processes including a pending communication request have been completed, the data transfer device that disconnects communication with the lower-level device receives the command. In this case, a control circuit for unilaterally proceeding with the processing procedure without confirming a response from the lower order device in the communication procedure to the lower order device and terminating the communication process with the lower order device is provided.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device for stopping a component in a computer system, and more particularly to a data transfer device for disconnecting a channel device in a channel processing device from a channel control device.

2. Description of the Related Art In a computer system, when a failure occurs in a component of the system, a recovery process for the component is immediately performed. At this time, the components need to be separated or replaced. When separating a component, it is necessary to separate it without affecting other components.

[Prior Art] FIG. 7 is a block diagram showing a conventional configuration example of a computer system. In the figure, 1 is a CPU, 2 is a main storage device connected to the CPU 1, and 10 is a channel processing device connected to the main storage device 2. The channel processing device 10 includes:
It comprises a channel control device 11 and a plurality of channel devices 12 connected to the channel control device 11. Reference numeral 3 denotes an input / output control device connected to each channel device 12, and reference numeral 4 denotes an input / output device connected to the input / output control device 3.

In the system configured as described above, when accessing the main storage device 2 from the input / output device 4, the access request enters the channel processing device 10 via the input / output control device 3. In the channel processing device 10, the channel device 12 first receives the access request and raises the access request to the channel control device 11. Access requests from a plurality of channel devices 12 to the channel control device 11 may increase.
At this time, these access requests are time-divided and sent to the CPU 1. The CPU 1 reads the contents of the access, and
Is read out and supplied to the input / output device 4. The route at this time follows the reverse route.

In such a series of processing, when a failure occurs in a component of the system, the entire system is conventionally stopped. After stopping the processing in the series including the faulty element, processing such as separation of the faulty element has been performed.

[Problem to be Solved by the Invention] When a failure occurs in a component of the system and the failure element is separated without stopping the system, if an attempt is made to unconditionally disconnect the failure element, an error such as a communication procedure other than the failure device may occur. Detection will cause a secondary failure.

The present invention has been made in view of such a problem, and has as its object to provide a data transfer device capable of terminating communication with a component without inconsistency when disconnecting communication.

[Means for Solving the Problems] FIG. 1 is a principle block diagram of the present invention. In the figure, 20 is a higher-level device, 21 is a plurality of lower-level devices, and 22 is a higher-level device
It is a data transfer device arranged between 20 and the lower device 21. 30 receives a command to disconnect the communication with the lower-level device 21, in a plurality of reception processes from the lower-level device 21, those that are in the process of receiving, continue processing until the end of the reception process, and respond to a new reception request Wait control circuit to stop receiving
31 receives a command to disconnect the communication with the lower-level device 21; in a plurality of transmission processes to the lower-level device 21, when all the transmission processes including the transmission request pending in the data transfer device 22 are completed, A transfer control circuit that disconnects communication with the device 21. Both the wait control circuit 30 and the transfer control circuit 31 are included in the data transfer device 22.

[Operation] When the communication disconnection command is received, the wait control circuit 30 functions to stop the new receiving process, and the transfer control circuit 31 disconnects the communication when all the processing requests in the data transfer device 22 disappear. Work like that. As a result, communication can be stopped without disturbing the reception / transmission procedure when the component (here, the lower device 21) is to be disconnected. As a result, a secondary failure in the data transfer device 22 or the host device 20 due to the communication stop is not induced.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a configuration block diagram showing one embodiment of the present invention. 1 are denoted by the same reference numerals.
In the figure, reference numeral 20 denotes a main storage device as a higher-order device, reference numeral 21 denotes a channel device as a lower-order device, and reference numeral 40 denotes a channel control device arranged between the main storage device 20 and the channel device 21. The relationship between the main storage device 20, the channel device 21, and the channel control device 40 is the same as in the conventional system shown in FIG. In the figure, squares indicate registers.

Reference numeral 22 denotes a channel control unit as a data transfer device.
The channel controller 22 controls two channels at the same time, and is provided with two channels # 0 and # 1.
The # 0 channel control unit 22 controls two channel devices 21 of CH0 and CH1, and the # 1 channel control unit 22 controls two channel devices 21 of CH2 and CH3.

32 and 33 are registers for holding data and the like from the channel device 21, 34 and 35 are selectors (SEL) for selecting the output of the register 32, 36 and 37 are selectors for selecting the output of the register 33, and 38 is the selector 34 and A selector for selecting one of the selectors 36 and 39 is a selector for selecting one of the selectors 35 and 37. The output of the selector 38 enters one input of the selector 41, and the output of the selector 39 enters the channel devices 21 of CH0 and CH1.

Reference numeral 42 denotes a request control circuit that controls writing and reading of data in the memory 20a in the main storage device 20. The output of the selector 41 is temporarily stored in a register 20b in the main storage device 20, and then provided to the memory 20a as address data. The above configuration is the same for the channel control unit 22 side of # 1.

In the system configured as described above, the signal from the channel device 21 is supplied to the selector 34 → selector 38 → selector
41 → given to the memory 20a via the register 20b. On the other hand, data read from the memory 20a enters the channel control device 40 via the register 43. The data output from the register 43 enters the channel control unit 22 of # 0 or # 1.

In the channel control unit 22, data from the register 43 is held in the register 32 or 33. The data held in these registers 32 or 33 is supplied to the selector 35 or
The signal is supplied from the selector 39 to the channel device 21 via 37. Next, operations of the wait control circuit 30 and the transfer control circuit 31 will be described.

FIG. 3 is a diagram showing a detailed configuration example of the wait control circuit 30. The same components as those in FIG. 2 are denoted by the same reference numerals.
The wait control circuit 30 includes a wait control unit 30a for CH0 and a wait control unit 30b for CH1. The waiting control units 30a and 30b include a bus valid signal BUS-VLD and a bus
A fast signal BUS-FIRST, a bus end signal BUS-END, a bus / channel identification signal BUS-CHID, and a communication disconnection command are commonly included.

Each of the waiting control units 30a and 30b outputs a channel sequence flag signal CH-SEQ-FLAG and a channel busy signal CH-BU.
SY is output, of which the CH-SEQ-FLAG signal is fed back to the input.

On the other hand, the bus data BUS-DATA enters the registers 32 and 33, and is held in the register 32 in the order of the command COMMAND, address ADRESS, data word DATA-WORD0, and DATA-WORD1. The same applies to the register 33. And
The wait control unit 30a controls the register 32, and the wait control unit 30b controls the register 33. □ is a register. The operation of the circuit configured as described above will be described below.

The waiting control units 30a, 30b are controlled by the control signals BUS-VLD, BUS-FIRST, B
The bus data is stored in the register 32 or 33 using US-END and BUS-CHID. After the BUS-VLD is turned on as shown in FIG. 4 (b), the wait control unit 30a turns on the BUS-FIRST as shown in (c) and the BUS-CHID shown in (e) CH0
While selecting COMMAND, ADDRESS, DATA-WORD0, D
The four data of ATA-WORD1 are stored in the register 32. 4
When the data transfer is completed, the BUS-END signal is turned on as shown in FIG.

In FIG. 4, in a state where three data of CH0 are held in the register 32, as shown in FIG.
Turns on. As a result, as shown in (e), the BUS-CHID
Is switched to the CH1 side, and one CH1 data is stored in the register 33. Thereafter, returning to the CH0 side again, the last data is stored in the register 32. (F) is SEQ-FLAG of CH0,
(G) is BUSY of CH0. About CH1 (H),
The same applies as shown in FIG.

FIG. 5 is a flowchart showing the operation of the wait control circuit. First, it is checked whether the BUS-VLD has been turned on (S1). When the BUS-FIRST is turned on, it is checked whether the BUS-FIRST is turned on (S2). If the BUS-FIRST is on, it is checked whether the communication disconnection command is on (S3). If the communication disconnection command is off, the CH-SEQ-FLAG is turned on (S4), and a waiting process (a process of putting data into the register 32) is performed (S5).

Next, if BUS-FIRST is off in S2, it is checked whether CH-SEQ-FLAG is on (S6). When the CH-SEQ-FLAG is off, the BUS-VLD is ignored (S7). If the CH-SEQ-FLAG is ON, it is checked whether the BUS-END signal has been turned ON (S8) because the processing is being continued. If the BUS-END signal is off, a wait process starts (S5). BUS-END
If the signal is on, the data transfer has been completed.
Turn off CH-SEQ-FLAG as shown in Figure (f) (S9),
The process enters a waiting process (S5). If the communication disconnection command is ON in S3, the BUS-VLD is ignored (S7).

By repeating such a series of sequences, when a communication disconnection command is received, if the reception processing is not being performed, the reception is immediately stopped because other components are not affected, and the reception processing is terminated when the reception processing is not being performed. After the processing is continued until, the reception can be stopped. Therefore, the channel device 21 (see FIG. 2) can be disconnected without contradiction.

Next, the operation of the transfer control circuit 31 will be described. FIG. 6 is a flowchart showing the operation of the transfer control circuit. First, it is checked whether there is a transmission request (S1). If there is no transmission request, it is checked whether the communication disconnection command is on (S2). When the communication disconnection command is on, the other components are not affected, so that the communication disconnection is immediately performed (S3). When the communication disconnection command is off, the process returns to S1.

If there is a transmission request in S1, it is checked whether the communication disconnection request is on (S4). If the communication disconnection request is on, the transmission request is deleted even if there is a transmission request (S5). If the communication disconnection request is off, it is checked whether a transmission request has been made (S6). If it has been transmitted, the process returns to S1. If not, data transmission is performed (S7).

After data transmission, it is checked whether there is a response from the channel device (S8). If there is a response, the process returns to S6 to check whether or not transmission has been completed. If there is no response, it is checked whether the communication disconnection command is on (S9). If the communication disconnection command is on, S6
Check if it has been sent. If the communication disconnection command is off, the process returns to S8 to check whether there is a response. By repeating the above-described sequence, in response to a transmission request from a lower-level device such as the channel device 21, the communication with the lower-level device is disconnected after all transmission processes including the pending transmission request are completed. Thus, the lower-level device can be disconnected without affecting other components.

The area A surrounded by the broken line in FIG. 6 corresponds to claim 2, and the area B corresponds to claim 3.

In the above embodiment, the channel device is taken as the lower device and the main memory is taken as the higher device. However, the present invention is not limited to this, and other devices may be used as the lower device and the higher device, respectively. Can be. Further, the data transfer device is not limited to the channel control unit, and other devices can be used.

Further, in the above-described embodiment, the case where two sets of channel control units are provided in the channel control device is taken as an example. However, the present invention is not limited to this, and an arbitrary set of channel control units may be provided. Can be. Also, the number of channel devices controlled by the channel control unit is not limited to two sets, and it is also possible to control an arbitrary set of channel devices.

[Effects of the Invention] As described above in detail, according to the present invention, when receiving a communication disconnection command, the wait control circuit operates to stop a new reception process, and the transfer control circuit operates in the channel control unit. By acting to disconnect the communication when all of the processing requests are gone, it is possible to provide a data transfer device capable of terminating the communication with the constituent elements without inconsistency when the communication is disconnected. Great effect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 3 is a diagram showing a detailed configuration example of a waiting control circuit, and FIG. FIG. 5 is a flowchart showing the operation of the wait control circuit, FIG. 6 is a flowchart showing the operation of the transfer control circuit, and FIG. 7 is a block diagram showing an example of a conventional configuration of the computer system. . In FIG. 1, reference numeral 20 denotes an upper device, 21 denotes a lower device, 22 denotes a data transfer device, and 30 denotes a data transfer device.
Is a wait control circuit, and 31 is a transfer control circuit.

Claims (2)

(57) [Claims] In a communication process with a lower-level device, when a command for disconnecting communication with the lower-level device is received, when all communication processes including a pending communication request are completed, communication with the lower-level device is performed. In the data transfer device for disconnecting, when receiving the command, without confirming the response from the lower device in the communication procedure to the lower device, unilaterally proceed with the processing procedure, and perform the communication process with the lower device A data transfer device comprising a control circuit for terminating the data transfer. 2. In communication processing with a lower-level device, when a command to disconnect communication with the lower-level device is received, when all communication processes including a pending communication request are completed, communication with the lower-level device is completed. In the data transfer device that disconnects, when receiving the command, the process during communication with the lower device continues, and the process of newly starting communication does not perform a substantial transmission procedure with the lower device, A data transfer device comprising a control circuit for discarding a communication request from a lower-level device performing new communication.