JP2747944B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device used for a microprocessor or the like.

2. Description of the Related Art Microprocessors are becoming faster and faster with the demands of the times. As one of the techniques for increasing the speed of a microprocessor, a register file having a configuration called a register window has been proposed.

In the conventional register file, the number of registers is limited. If the value of the register used in the main routine is left when branching to a subroutine or the like, the number of registers that can be used in the subroutine decreases, so the subroutine branch Sometimes register values are saved to memory, and the number of available registers is increased.
Although it is conceivable to increase the number of registers, it is difficult to manage the registers, and the load on the compiler increases.

On the other hand, in the register window in which the register file is divided into a plurality of windows, the window is switched every time the branch to the subroutine or the return from the subroutine is performed, so that the memory of the register data at the time of the subroutine branch is eliminated and the processing of the microprocessor is performed. Speed can be increased. Furthermore, since the number of registers in one window is about 32, there is an advantage that the load on the compiler is not increased. The registers between the windows partially overlap each other, so that data can be transferred between subroutines in the overlapping portions. Therefore, in such a configuration of the register file, the memory cells in the overlapping portion have two addresses.

In such a semiconductor memory device having a plurality of addresses for one memory cell, an address conversion as shown in FIG. 10 is performed in order to make the address and the memory cell correspond one-to-one. A semiconductor memory device employing a register window configuration as shown in the figure is used. In this semiconductor memory device, a precharge circuit is used as a charging means, and the operation is performed in synchronization with the clock Φ1. This register file has eight windows and 32 registers per window.

Next, a schematic configuration of the semiconductor memory device will be described. In FIG. 11, an address conversion means 1 receives an address signal Ai and a window signal Wi from the outside and outputs them to a decoding means 2. The decoding means 2 includes a word line Wr
1, the word line Wr1 is connected to the output means 5 of the memory cell 4 in the memory cell array 3 shown in FIG. 12, and the output means 5 is connected to the read bit line Br.
The read bit line Br is also connected to the precharge means 6 and the input / output means 7 shown in FIG. The address conversion means 8 receives an address signal Ci and a window signal Xi from outside and outputs them to the decoding means 9. The decoding means 9 is connected to the word line Ww1, the word line Ww1 is connected to the input means 10 shown in FIG. 12 of the memory cell 4 in the memory cell array 3, and the input means 10 is connected to the write bit line Bw. ing. A memory element 11 is connected between the input means 10 and the output means 5. Further, the write bit line Bw is connected to the input / output means 7 shown in FIG.

Next, the operation of the above conventional example will be described. First, in a read operation, an address signal Ai and a window signal Wi for designating a window are externally input to the address conversion means 1, and the address conversion shown in FIG. 10 is performed to obtain an address signal Bi. The address signal Bi is decoded by the decoding means 2, and the word line Wr1 corresponding to the address signal Bi is decoded.
Drive. The word line Wr1 controls the output unit 5 shown in FIG. 11 of the memory cell 4 in the memory cell array 3, and the output unit 5 discharges the read bit line Br precharged by the precharge circuit 6. , And outputs the data of the memory element 11 to the read bit line Br. Next, the read bit line Br is input to the input / output means 7, and the data of the memory element 11 is output from the input / output means 7 to the outside.

Next, in a write operation, an address signal Ci and a window signal Xi for designating a window are externally input to the address conversion means 8 and converted into an address shown in FIG. 10 to become an address signal Di. The address signal Di is supplied to the decoding means 9.
To drive the word line Ww1 corresponding to the address signal Di. Write data input from the outside is input to the input / output means 7 and output to the write bit line Bw. The word line Ww1 controls the input unit 10 shown in FIG. 12 of the memory cell 4 in the memory cell array 3, and the input unit 10 transmits the data of the write bit line Bw to the memory element.
11 and the write data is written to the memory element 11.

SUMMARY OF THE INVENTION However, in such a conventional semiconductor memory device, it takes a lot of processing time for address conversion.
The read and write operations are delayed by the time required for address conversion, and as a result, it has been difficult to speed up the read and write operations.

For example, when the address signal Ai = 8, the window signal Wi = 2, and the address signal Ai = 24, the window signal Wi = 1 in FIG. Bi = MOD ((Ai-8) + Wi × 16) (However, MOD represents a remainder.) For this reason, there is a problem that access to the register is started with respect to the register address of such an operation result, so that access becomes slow as a whole.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has made it possible to perform a read or write operation of a semiconductor memory device in which a plurality of addresses are assigned to one memory cell without performing address conversion. As a result, an object of the present invention is to provide a semiconductor memory device capable of speeding up a read or write operation.

Means for Solving the Problems In order to achieve the above object, the present invention has the following means.

The present invention (1) provides n (n is a natural number excluding 1) output means for outputting data of a memory element to one read bit line, and n read word lines connected to the output means And m (m is a natural number excluding 1) input means for inputting data of one write bit line and outputting the data to the memory element, and m write word lines connected to the input means. And a plurality of memory cell arrays connected to the n read word lines, receiving the same address signal and decoding addresses to drive the corresponding read word lines. Read decoding means, charging means connected to the read bit line for charging the read bit line, read bit line and write bit line. Is connected to a preparative lines, and output means for outputting the data of the read bit line and outputted to the outside, also the external data to the write bit line,
A semiconductor memory device having a plurality of write decoding means connected to the m write word lines, receiving the same address signal, decoding an address, and driving a corresponding write word line; Each of the plurality of read decoding means has different coding applied to the same read address signal, decodes specific different read address signals and drives the same read word line, Each of the plurality of write decoders has different coding applied to the same write address signal, and decodes different specific write address signals to drive the same write word line. Features.

Further, the present invention (2) has n (n is a natural number excluding 1) input / output means for inputting / outputting data of a memory element to / from a bit line, and n word lines connected to the input / output means. A memory cell array including a plurality of memory cells, a plurality of decoding means connected to the n word lines, receiving the same address signal, decoding an address, and driving a corresponding word line; Charge means connected to a bit line for charging the bit line; input / output means connected to the bit line for outputting data of the bit line to the outside and outputting external data to the bit line; Wherein each of the plurality of decoding means has a different coding applied to the same address signal, and decodes specific different address signals to generate the same A semiconductor memory device characterized by driving the lead wire.

Further, the present invention (3) includes a plurality of memory cells, and n (n is a natural number excluding 1) bit lines and m (m is a natural number excluding 1) word lines connected to the memory cells. An address decoder comprising a memory cell array, a decoding unit for inputting an address signal and a control signal from the outside and performing decoding, and a word line driving unit for receiving the output of the decoding unit and driving the word line A charging unit connected to the bit line for charging the bit line; a charging unit connected to the bit line to output data of the bit line to the outside; and to output external data to the bit line. Input / output means,
A semiconductor memory device, characterized in that the address decoding section has a function of calculating a logical product and a logical sum of an address signal and a control signal, and decodes different specific address signals to drive the same word line.

According to the present invention (4), as the address decoding unit according to the present invention (3), a (a is a natural number excluding 1) decoding means for inputting and decoding an address signal and a logic of an output of the decoding means are provided. And a gate that takes the sum.

According to the present invention (5), as the decoding unit according to the present invention (3), a series transistor (a is a natural number) in which a number of bits to be decoded and a single conduction type transistor for a control signal are connected in parallel is used. And a transistor of the other conduction type. One of the a series transistors is connected to the first potential, and the other is connected to the transistor to become an output. One is connected to the second potential.

The present invention (6) includes the present inventions (3), (4), and (5).
The memory cell array according to any one of the above, output means for outputting the data of the memory element to the read bit line, read word line connected to the output means, and input the data of the write bit line, An input means for outputting to a memory element, and a plurality of memory cells having a write word line connected to the input means are included, a charging means is connected to a read bit line, and It has a configuration in which it is connected to a bit line and a write bit line, outputs data of the read bit line to the outside, and outputs external data to the write bit line.

According to the present invention (1), with the above configuration, the n decoding means for decoding and selecting the read address and the data of the selected memory cell connected to the n decoding means are output to the read bit line. N output means, m decode means for decoding and selecting a write address, and data on a write bit line connected to the m decode means to output and write data to a selected memory cell. A plurality of input means, each of which decodes an overlapping address by the decoding means, and drives a corresponding word line, thereby enabling a memory cell to be selected and accessed. It is.

Further, the present invention (2) has a decoding means for decoding and selecting an address and an input / output means connected to the decoding means and inputting / outputting data of a selected memory cell to / from a bit line. This makes it possible to select and access a memory cell by decoding the overlapping address by the decoding means and driving the corresponding word line.

According to the present inventions (3), (4), (5) and (6), in the semiconductor memory device in which a plurality of addresses are assigned to one memory cell, By decoding and ORing the word lines to drive the word lines, it becomes possible to drive the word lines if any of the assigned addresses is selected. This enables reading and writing operations to be performed without performing conversion.

Therefore, according to the present invention, a read or write operation can be performed without performing address conversion,
There is an effect that reading or writing operation can be speeded up.

Embodiment FIG. 1 is a schematic block diagram of a semiconductor memory device having a register window configuration showing an embodiment of a semiconductor memory device according to claim (1) of the present invention. In this embodiment, the number of windows is 8, and the number of registers per window is 32. In FIG. 1, reference numeral 101 denotes a memory cell array of 136 words × 32 bits, and reference numeral 102 denotes one of the memory cells. As shown in FIG. 2, one memory cell 102 includes output means 103 and 104 for outputting data in the memory cell 102 to one read bit line Br, and a read word line Wr1 connected to these output means 103 and 104. , Wr2, and input means 105, 106 for inputting data of one write bit line Bw and outputting the data to the memory cell 102, and a write word line W connected to these input means 105, 106.
w1 and Ww2. 107 is output means 103, 104 and input means 10
5 and 106.

In FIG. 1, reference numerals 108 and 109 denote decoding means for reading, which are connected to the word line drive unit 110 and the address signal Ai and the window signal Wi. The word line driving section 110 includes decoding means 108 and 109 and word lines Wr1 and Wr.
Connected to two. A precharge circuit 111 is connected to the clock φ1 and the read bit line Br to charge the same. Reference numeral 112 denotes an input / output unit connected to the read bit line Br and the write bit line Bw to output data of the read bit line Br to the outside, and to output external data to the write bit line Bw. Decoding means 113 and 114 for writing are connected to the word line driving section 115, the address signal Ci and the window signal Xi. The word line driving section 115 is connected to the decoding means 103 and 104 and the word lines Ww1 and Ww2.

The decoding means for reading 108, 109 and the decoding means 103, 104 for writing have the same configuration. The precharge circuit 111 operates in synchronization with the clock Φ1. As shown in FIG. 3, the memory cell array 101 has a structure in which addresses are allocated such that two addresses overlap every eight words.

Next, the operation of the above embodiment will be described. First, in the read operation, the address signal Ai and the window signal Wi for specifying the window in FIG.
The word line Wr1 or the word line Wr2 is input to the word line drive unit 110, and the output is input to the word line drive unit 110. In a portion where addresses do not overlap, the word line is driven by decoding by one of the decoding means 108 and 109. When the word line Wr1 or the word line Wr2 is driven, the output bit 103 or the output bit 104 in the memory cell 102 shown in FIG. 2 is read by the precharge circuit 111 shown in FIG. Is discharged in accordance with the data of the memory element 107, so that the data of the memory element 107 is output to the read bit line Br. Next, the input / output means 112 connected to the read bit line Br
Output the data of r to the outside.

In the above operation, for example, when the address shown in FIG.
In the part where the window 2 is overlapped with the hatched address where the address is 24 and the window is 1, if the address signal Ai is 8 and the window signal Wi is 2, the word line
Wr1 is driven, and when the address signal Ai is 24 and the window signal Wi is 1, the word line Wr2 is driven,
Decoding means 108 and 109 are coded. Thus, the same memory cell 102 can be selected without address conversion, and high-speed reading can be performed.

On the other hand, in the write operation, the address signal Ci and the window signal Xi specifying the window are supplied to the decoding means 103,
The word line Ww1 or the word line Ww2 is input to the word line 104 and the output thereof is input to the word line driving unit 115, and the word line driving unit 115 drives the word line Ww1 or the word line Ww2. In the part where addresses do not overlap, the word lines are driven by decoding by either of the decoding means 103 and 104. Further, data is input from the outside to the input / output means 112, and the data is output from the input / output means 112 to the write bit line Bw. When the word line Ww1 or the word line Ww2 is driven, the input means 105 or 106 in FIG. 2 outputs data from the write bit line Bw to the memory element 107, and writes data to the memory element 107.

In the above operation, similarly, in the portion where the address indicated by the hatched portion in FIG. 3 is 8 and the window is 2, and the address where the address is 24 and the window is 1, the address signal is overlapped.
When Ci is 8 and the window signal Xi is 2, the word line Ww1 is driven, and when the address signal Ci is 24 and the window signal Xi is 2,
Is 1, the decoding means 103 and 104 are coded so that the word line Ww2 is driven. Thus, the same memory cell 102 can be selected without address conversion, and high-speed writing can be performed.

In the above embodiment, n = 2 and m = 2, but similar effects can be obtained in other cases. Although the above embodiment is a register file in the case of one write port and one read port, the register file of another port configuration can be implemented by using a plurality of read or write bit lines. It is. Further, the present invention can be applied to only reading or only writing.

FIG. 4 shows a configuration example of a memory cell in the case where the present invention is multiported, and o write ports, p read ports, overlap of write addresses are m, and overlap of read addresses is n. In FIG. 4, reference numerals 116 and 117 denote input means, respectively, and o write bit lines Bw1
To Bwo and m × o write word lines Ww11 to Wwm1,
Ww1o to Wwmo are connected. Output means 118 and 119 are p read bit lines Br1 to Brp and nxp read word lines Wr11 to Wrn1 and Wr1p to Wrnp, respectively.
Is connected. 120 is input means 116, 117 and output means 11
8 and 119 are connected to the memory device. Similar effects can be obtained in this embodiment.

Instead of using a precharge circuit as in each of the above embodiments, it is also possible to configure a charging means using a pull-up circuit or the like. In each of the above embodiments, input means
105, 106 and 116, 117 and output means 103, 104 and 118, 119
Are of a CMOS configuration, but can be implemented with other devices. It is also possible to assign a non-overlapping part to one of the decoding means,
Only the assigned decoding means increases the load capacity,
Since the access becomes slow, the load capacity of the decoding means can be equalized by allocating the addresses equally to the respective decoding means, and as a result, the load capacity is reduced as compared with the case where the addresses are assigned to one decoding means. Can be faster.

FIG. 5 is a schematic block diagram of a semiconductor memory device having a register window structure showing one embodiment of the semiconductor memory device according to claim (2) of the present invention. In this embodiment, the number of windows is 8, and the number of registers per window is 32. In FIG. 5, 201 is a memory cell array of 136 words × 32 bits, and 202 is one of the memory cells. As shown in FIG. 6, one memory cell 202 includes input / output means 203 and 204 for inputting / outputting data in the memory cell 202 to / from bit lines B1 and B2, and input / output means 203 and
04 and word lines W1 and W2. Reference numeral 205 denotes a memory element connected to the input / output units 203 and 204. In FIG. 5, reference numerals 206 and 207 denote decoding means, which are connected to the word line driving section 208 and the address signal Ai and the window signal Wi. The word line drive unit 208
6,207 and word lines W1 and W2. A precharge circuit 209 is connected to the clock Φ1 and the bit lines B1 and B2 to charge them. 210 is the bit line B1,
It is an input / output means connected to B2 to output data on the bit line B1 to the outside and output external data to the bit lines B1 and B2. 211 is a sense amplifier provided in the input / output means 210, 212 is a buffer, and 213 is an inverter.

The decoding means 206 and 207 have the same configuration. Precharge circuit 209 operates in synchronization with clock φ1. As shown in FIG. 3, the memory cell array 201 has a structure in which addresses are allocated such that two addresses overlap every eight words.

Next, the operation of the above embodiment will be described. First, in the read operation, the address signal Ai and the window signal Wi for designating the window in FIG.
The output is input to the word line drive unit 207, and the word line drive unit 208 drives the word line W1 or the word line W2. In the part where the addresses do not overlap, the word line is driven by decoding by one of the decoding means 206 and 207. Word line W1 or word line
When W2 is driven, the input / output means 203 or 204 in the memory cell 202 shown in FIG. 6 connects the bit line B1 or the bit line B2 precharged by the precharge circuit 209 in FIG. By discharging in accordance with the data of the memory element 205, the data of the memory element 205 is output to the bit line B1 or the bit line B2 as a potential difference. Since the potential difference generated at this time is small, when the control signal RE is next input, the sense amplifier 211 in the input / output means 210 connected to the bit lines B1 and B2 amplifies the potential difference between the bit lines B1 and B2, Outputs line data to the outside.

In the above operation, for example, when the address shown in FIG.
In the part where the window 2 is overlapped with the hatched address where the address is 24 and the window is 1, if the address signal Ai is 8 and the window signal Wi is 2, the word line
The decoding means 206 and 207 are coded so that W1 is driven, and when the address signal Ai is 24 and the window signal Wi is 1, the word line W2 is driven. Thus, the same memory cell 202 can be selected without address conversion, and high-speed reading can be performed.

On the other hand, in the write operation, similarly, the address signal Ai and the window signal Wi for specifying the window are input to the decoding means 206 and 207, and the output thereof is input to the word line driving unit 208, and the word line driving unit 208 outputs the word line W1 or the word line W1. Line W2 is driven. In the part where the addresses do not overlap, the word line is driven by decoding by one of the decoding means 206 and 207. When data is input from the outside to the input / output means 210 and the control signal WE is input, the data is output to the bit lines B1 and B2 by the buffer 212 and the inverter 213 in the input / output means 210, respectively. When the word line W1 or the word line W2 is driven, the input / output means 203 or the input / output means 204 in FIG. 6 outputs data from the bit lines B1 and B2 to the memory element 205, and outputs the data to the memory element 205. Write.

In the above operation, similarly, in the portion where the address indicated by the hatched portion in FIG. 3 is 8 and the window is 2, and the address where the address is 24 and the window is 1, the address signal is overlapped.
The decoding means 206 and 207 are coded so that when Ai is 8 and the window signal Wi is 2, the word line W1 is driven, and when the address signal Ai is 24 and the window signal Wi is 1, the word line W2 is driven. ing. Thus, the same memory cell 202 can be selected without address conversion, and high-speed writing can be performed.

In the above embodiment, n = 2, but the same effect can be obtained in other cases. It is also possible to assign a non-overlapping part to one of the decoding means. However, only the assigned decoding means increases the load capacity and slows down the access. By assigning to
The load capacities of the decoding means can be made equal, and as a result, the load capacities can be reduced as compared with the case where they are assigned to one, and the speed can be increased. Further, instead of the precharge circuit as in this embodiment, a pull-up circuit or the like may be used to constitute the charging means. Further, although the input / output means 203 and 204 have a CMOS configuration, the embodiment can be implemented with other devices.

FIG. 7 shows claims (3), (4), (5),
It is a schematic block diagram of the semiconductor memory device of the register window structure of one Example of the semiconductor memory device of (6), (7), and (9). In this embodiment, the number of windows is 8, and the number of registers per window is 32. In FIG. 7, reference numeral 301 denotes a memory cell array of 136 words × 32 bits, and 302 denotes one of the memory cells. One memory cell 302 is, as shown in FIG.
Output means 304 for outputting the data of the memory element 303 in the bit line 02 to the bit line Br, and a word line connected to the output means 304
It has an input unit 305 for inputting data of the write bit line Bw and outputting it to the memory element 303 in the memory cell 302, and a word line Ww1 connected to the input unit 305.

In FIG. 7, reference numeral 306 denotes a read address decode unit connected to the address signal Ai, the window signal Wi, and the word line Wr1. The address decoding unit 306 includes a decoding unit 307 that receives the address signal Ai, the window signal Wi, and the clock Φ1 as inputs, the decoding unit 307 and the word line Wr.
And a word line drive unit 308 connected to the first line. The decoding unit 307 further includes decoding units 309 and 310 connected to the address signal Ai and the window signal Wi, a clock Φ1, the decoding units 309 and 310, and the word line driving unit 308.
And a gate 311 connected to the gate. Reference numeral 312 denotes a precharge circuit which is connected to the read bit line Br and charges it. 314 is a read bit line Br
And an input / output means connected to the write bit line Bw to output the data of the read bit line Br to the outside and output the external data to the write bit line Bw.

315 is a write address decode unit connected to the address signal Ci, the window signal Xi, and the clock Φ1. The address decoding unit 315 receives the address signal Ci, the window signal Xi, and the clock Φ1 as inputs.
6 and a decoding unit 316 and a word line driving unit 317 connected to the word line Ww1. The decoding unit 316 further includes decoding units 318 and 319 connected to the address signal Ci and the window signal Xi, and a gate 320 connected to the clock φ1, the decoding units 318 and 319, and the word line driving unit 317.

The decoding means 309, 310, 318, 319 have the same configuration, the gates 311, 320 also have the same configuration, and the word line drive units 308, 317 also have the same configuration. The precharge circuit 312 operates in synchronization with the clock Φ1. The clock Φ1 is used as a control signal. Memory cell array 30
1, as shown in FIG. 3, the address allocation is such that two addresses overlap every eight words.

Next, the operation of the above embodiment will be described. First, in the read operation, the address signal Ai and the window signal Wi for specifying the window in FIG.
The input is provided to the decoding means 309, 310 of the decoding unit 307 in the 306, and the output of the decoding means 309, 310 is input to the gate 311. Since the logical sum of the decoding means 309 and 310 is obtained by the gate 311, one of the outputs of the decoding means 309 and 310 is driven, and when the clock Φ1 becomes high level, the gate 311
Outputs the word line driving unit 308 and the word line driving unit 3
08 drives the word line Wr1. When the word line Wr1 is driven, the output means 304 in the memory cell 302 shown in FIG.
The data of the memory element 303 is output to the bit line Br by discharging the read bit line Br precharged by the precharge circuit 312 in the figure in accordance with the data of the memory element 303. Next, the input / output means 314 connected to the bit line Br outputs the data on the bit line Br to the outside.

In the above operation, for example, when the address shown in FIG.
In the overlapping portion where the window is 2 and the address is 24 and the window is 1 and the window is 1, if the address signal Ai is 8 and the window signal Wi is 2, the decoding means 309
However, when the address signal Ai is 24 and the window signal Wi is 1, the decoding means 309 and 310 are coded such that the output of the decoding means 310 is driven. Thus, the same memory cell can be selected without address conversion, and high-speed reading can be performed.

In the part where the addresses do not overlap, the signal is decoded by one of the decoding means 309 and 310, and the output is input to the word line drive unit 308. When the clock Φ1 becomes high level, the word line Wr1 is driven.

On the other hand, in the write operation, the address signal Ci and the window signal Xi specifying the window are input to the decoding means 318 and 319 of the decoding section 316 in the address decoding section 315, and the outputs of the decoding means 318 and 319 are input to the gate 320. Since the output of the decoding means 318, 319 is ORed by the gate 320, one of the outputs of the decoding means 318, 319 is driven. When the clock φ1 becomes high level, the output of the gate 320 drives the word line driving unit 317. The word line drive unit 317 drives the word line Ww1. Also, data is input to the input / output means 314 from outside, and the input / output means 314
Outputs data to the bit line Bw. When the word line Ww1 is driven, the input means 305 in FIG. 8 outputs data from the bit line Bw to the memory element 303 and writes data to the memory element 303.

In the above operation, the address shown in FIG.
In the overlapping portion where the window is 2 and the address is 24 and the window is 1 and the window is 1, the address signal Ci is 8
When the window signal Xi is 2, the output of the decoding means 318 is output, and when the address signal Ci is 24 and the window signal Xi is 1
In this case, the decoding means 318 and 319 are coded so that the output of the decoding means 319 is driven. Thus, the same memory cell can be selected without address conversion, and high-speed writing can be performed.

Although this embodiment is a semiconductor memory device having one port for writing and one port for reading, as described with reference to FIG. 4, other port configurations can be realized by using a plurality of reading or writing bit lines. is there. In this embodiment, writing and reading are performed at different ports. However, by using a memory cell as shown in FIG.
The present invention can be applied to a case where writing and reading are performed by the same decoding means as in a RAM or a dynamic RAM. Furthermore, the present invention can be applied to only reading or only writing. As a coding of the decoding means, a portion where addresses do not overlap may be assigned to one of the decoding means.
Since the load capacity of the decoding means becomes large and the decoding speed becomes slower than other decoding means, the load capacity of the decoding means can be equalized by allocating the addresses equally to the respective decoding means.
The decoding speed is made uniform, and as a result, the speed can be increased. Even if the overlap of addresses becomes o (o is a natural number), it can be realized by taking OR of the OR. Furthermore, instead of the precharge circuit as in the present embodiment, it is possible to configure the charging means using a preup circuit or the like, and the output means 304 and the input means 3
Although a MOS transistor is used as 05, a bipolar transistor or the like can also be used.

FIG. 9 is a schematic block diagram of a semiconductor memory device having a register window configuration according to an embodiment of the semiconductor memory device according to the present invention. In this embodiment, the number of windows is 8, and the number of registers per window is 32. In FIG. 9, reference numeral 401 denotes a memory cell array of 136 words × 32 bits, and 402 denotes one of the memory cells. The configuration of one memory element 403 is the same as that shown in FIG. That is, output means for outputting data in the memory cell 402 to one read bit line Br
404, input means 405 having a word line Wr1 connected to the output means 404, inputting data of one write bit line Bw and outputting the data to the memory element 403, and connected to the input means 405. Word line Ww1.

In FIG. 9, reference numeral 406 denotes an address decoding unit connected to the address signal Ai, the window signal Wi, the clock φ1, and the word line Wr1. The address decoding unit 406 includes the series transistors 407 and 408 connected to the address signal Ai, the window signal Wi, and the clock φ1, and the clock φ.
The decoding unit 410 includes a transistor 409 connected to the word line 1 and a word line driving unit 411 connected to the output of the decoding unit 410 and the word line Wr1. Four
Reference numeral 12 denotes a precharge circuit which is connected to the bit line Br and charges the bit line Br. 413 is the bit line Br and bit line Bw
And input / output means for outputting data of the bit line Br to the outside and outputting external data to the bit line Bw. An address decoding unit 414 is connected to the address signal Ci, the window signal Xi, and the clock Φ1. 415
Is a word line drive unit connected to the output of the address decode unit 411 and the word line Ww1.

The address decoding units 406 and 414 have the same configuration. The series transistors 407 and 408 are constituted by nch transistors. The transistor 409 is formed by a pch transistor. The clock φ1 is used as a control signal of the decoding unit 410. The precharge circuit 410 operates in synchronization with the clock φ1. Memory cell array 40
1, as shown in FIG. 3, the address assignment has a structure in which two addresses overlap every eight words.

Next, the operation of the above embodiment will be described. First, in the read operation, in FIG. 9, the address signal Ai, the window signal Wi for specifying the window, and the clock Φ1
Is input to the decoding unit 410 in the address decoding unit 406, and is decoded by the serial transistors 407 and 408 in the decoding unit 410. The node D in FIG. 9 is precharged by the transistor 409 when the clock φ1 is at the low level. In the meantime, since the clock Φ1 is also input to the serial transistors 407 and 408, the serial transistors 407 and 408 are off. When the clock Φ1 becomes high level and the address signal Ai and the window signal Wi such that one of the series transistors 407 and 408 are all turned on are input, the node D becomes low level and the word line Wr1 is driven. When the word line Wr1 is driven, the output means 405 in the memory cell shown in FIG.
By discharging the read bit line Br precharged by 12 according to the data of the memory element 403, the data of the memory element 403 is output to the read bit line Br. The input / output means 413 connected to the read bit line Br outputs the data of the read bit line Br to the outside.

In the above operation, for example, when the address shown in FIG.
In the overlapping portion where the window is 2 and the address is 24 and the window is 1 and the window is 1, when the address signal Ai is 8 and the window signal Wi is 2, all the series transistors 407 in the decoding unit 410 are conductive. When the address signal Ai is 24 and the window signal Wi is 1, the serial transistors 408 and 408 in the address decode unit 406 are coded so that all the serial transistors 408 are turned on and the node D is set to the low level. Thus, the same memory cell can be selected without address conversion, and high-speed reading can be performed.

On the other hand, in the write operation, the address signal Ci, the window signal Xi specifying the window, and the clock Φ1
Is input to the address decoding unit 414, and performs the same operation as that of the address decoding unit 406 described above.
Is driven. Data is input from the outside to the input / output unit 413, and data is output from the input / output unit 413 to the bit line Bw. By driving the word line Ww1, the eighth
Input means 405 in the figure outputs data from the bit line Bw to the memory element 403, and writes data to the memory element 403.

In the above operation, similarly, in the portion where the address indicated by hatching in FIG. 3 is 8 and the window is 2 and the address is 24 and the window overlaps 1, the case where the address signal Ci is 8 and the window signal Xi is 2 and the address is When the signal Ci is 24 and the window signal Xi is 1, the series transistors 407, 40
The series transistors 407 and 408 in the address decoding unit 414 are coded so that all 8 are conductive and the word line Ww1 is driven. Thus, the same memory cell can be selected without address conversion, and high-speed writing can be performed.

Also, at the nodes A, B, and C in the address decoding unit 406, only the nch transistors are connected like the series transistors 407 and 408. Therefore, as in the conventional AND gate which is a CMOS type decoding circuit shown in FIG.
Compared with the case where two h transistors are connected, the capacitance can be reduced, high-speed decoding can be performed, and the area can be reduced. The same applies to the address decoding unit 411.

The above operation is performed when addresses are overlapped. However, in a portion where addresses are not overlapped, decoding can be performed by one of the serial transistors 407 and 408, thereby enabling access. At this time, by uniformly assigning an address to each of the series transistors 407 and 408, the load capacity of the decoding unit can be made uniform and the speed can be increased.

In this embodiment, the semiconductor memory device has one write port and one read port. However, as described with reference to FIG. 4, other port configurations can be realized by using a plurality of read or write bit lines. It is possible. In this embodiment, writing and reading are performed by different address decoding units. However, by using one memory cell as shown in FIG. 6 and having one input / output means, writing and reading can be performed by the same decoding means. Decoding can also be performed. Furthermore, the present invention can be applied to only reading or only writing.
Further, it is possible to configure the charging means using a pull-up circuit or the like instead of the precharge circuit as in this embodiment. Furthermore, although the present embodiment is an example using a MOS transistor, a bipolar transistor or the like can be used. Further, an nch transistor and a transistor 40 are added to the series transistors 407 and 408 in the address decoding unit 406.
Although a p-channel transistor is used for 9, even if a reverse conduction type transistor is used, the power supply connection can be changed and the word line drive unit can be configured as a buffer or omitted.

As described above, according to the present invention, in the case of a semiconductor memory device in which a plurality of addresses are assigned to one memory cell as in a register window configuration, selection is made for each assigned address. By adding a decoding means, a memory cell can be selected without performing address conversion, which has an effect of enabling high-speed writing or reading, which is extremely effective in practical use.

Also, the present invention provides a method in which a decoding unit is added to each assigned address, and a word line is driven by taking the logical sum of outputs of decoding units for decoding overlapping addresses. Even if they overlap, it is possible to select the memory cell by driving the same word line without performing address conversion, and has the effect of enabling high-speed writing or reading, which is extremely effective in practical use.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a semiconductor memory device having a register window configuration according to an embodiment of the present invention, and FIG. 2 is a schematic block diagram showing the configuration of the memory cell of FIG. FIG. 3 is a diagram showing the assignment of addresses in the register window of the semiconductor memory device according to the embodiment of the present invention. FIG. 4 is a diagram showing the configuration of a memory cell when the semiconductor memory device according to claim 1 of the present invention has a multiport structure. FIG. 5 is a schematic block diagram of a semiconductor memory device having a register window configuration according to an embodiment of the present invention, and FIG. 6 is a schematic block diagram of the memory cell shown in FIG. FIG. 7 is a schematic block diagram showing the configuration, and FIG.
(4), (5), (6), (7), and (9) are schematic block diagrams of a semiconductor memory device having a register window configuration according to an embodiment, and FIG. 8 is a schematic block diagram of FIG. 7 and FIG. FIG. 9 is a schematic block diagram showing a configuration of a memory cell, FIG. 9 is a schematic block diagram of a semiconductor memory device having a register window configuration according to an embodiment of the present invention, and FIG. And FIG. 11 is a schematic block diagram of a conventional semiconductor memory device having a register window configuration for performing address conversion, and FIG. 12 is a configuration of a memory cell of FIG. FIG. 13 is a circuit diagram showing an example of a conventional CMOS address decode circuit. Wr1, Wr2 ... read word lines, Ww1, Ww2 ... write word lines, Br ... read bit lines, Bw ... write bit lines. 101: Memory cell array, 102: Memory cell, 103, 10
4 ... output means, 105, 106 ... input means, 107 ... memory elements, 108, 109 ... read decoding means, 110, 115 ...
… Word line drive unit, 111… precharge circuit, 112…
Input / output means, 113,114 ... Write decoding means. 201: Memory cell array, 202: Memory cell, 203, 20
4 ... I / O means, 205 ... Memory elements, 206, 207 ... Decoding means, 208 ... Word line driver, 209 ... Precharge circuit, 210 ... I / O means. 301: Memory cell array, 302: Memory cell, 306, 31
5: Address decoding unit, 307, 316: Decoding unit, 30
8,317: Word line drive unit, 312: Precharge circuit,
314 ... I / O means, 311,320 ... Gate. 401 …… Memory cell array, 402 …… Memory cell, 403…
... memory element, 404 ... output means, 405 ... input means, 40
6,414 address decode unit, 407,408 nch transistor, 409 pch transistor, 410 decode unit, 411,415 word line drive unit, 412 precharge circuit, 413 input / output means.

Claims (9)

(57) [Claims] 1. An n-number (n is a natural number excluding 1) output means for outputting data of a memory element to one read bit line; n read word lines connected to the output means; M pieces of data (m is a natural number excluding 1) for inputting data of one write bit line and outputting the data to the memory element
And a memory cell array including a plurality of memory cells having m write word lines connected to the input means, and a memory cell array connected to the n read word lines, A plurality of read decoding means for receiving an address signal and decoding an address to drive a corresponding read word line; a charging means connected to the read bit line for charging the read bit line; An input / output unit connected to the read bit line and the write bit line for outputting data of the read bit line to the outside, and outputting external data to the write bit line; It is connected to the write word line, receives the same write address signal and decodes the address. A plurality of write decoding means for driving corresponding write word lines, wherein each of the plurality of read decode means has a different coding applied to the same read address signal, and The same read word line is driven by decoding different read address signals, and each of the plurality of write decode means has a different coding applied to the same write address signal, and A semiconductor memory device which decodes different write address signals and drives the same write word line. 2. An n-number (n is a natural number excluding 1) input / output means for inputting / outputting data of a memory element to / from a bit line, and a memory cell having n word lines connected to the input / output means. A plurality of memory cell arrays connected to the n word lines, a plurality of decoding means receiving the same address signal, decoding an address and driving a corresponding word line; Charging means connected to charge the bit line; input / output means connected to the bit line to output data of the bit line to the outside and output external data to the bit line; Each of the plurality of decoding units is differently coded with respect to the same address signal, and decodes a specific different address signal to generate the same word. A semiconductor memory device for driving a line. 3. A memory cell including a plurality of n (n is a natural number excluding 1) bit lines and m (m is a natural number excluding 1) word lines connected to the memory cell. An address decoding unit including a memory cell array, a decoding unit that inputs and decodes an address signal from the outside, and a word line driving unit that inputs the output of the decoding unit and a control signal to drive the word line; Charging means connected to the bit line for charging the bit line; input / output means connected to the bit line for outputting data of the bit line to the outside and outputting external data to the bit line And the address decoding unit has a function of performing a logical sum and an AND operation of the address signal and the control signal, and outputs a specific different address signal. A semiconductor memory device which decodes and drives the same word line. 4. An address decoding section comprising: a (a is a natural number excluding 1) decoding means for inputting and decoding an address signal; and a gate for obtaining a logical sum of outputs of the decoding means. 4. The semiconductor memory device according to claim 3, wherein: 5. An address decoding unit comprising: a serially connected a series transistor (a is a natural number excluding 1) comprising a number of bits to be decoded and a transistor of one conductivity type for a control signal; , One of the a series transistors is connected to a first potential, the other is connected to the transistor to provide an output, and the other of the transistors is connected to a second potential. The semiconductor device according to claim 3, wherein the semiconductor device is connected. 6. A memory cell array, comprising: an output unit for outputting data of a memory element to a read bit line; a read word line connected to the output unit; and data of a write bit line. An input unit for outputting to the memory element, and a plurality of memory cells having a write word line connected to the input unit; a charging unit connected to a read bit line; And (4) being connected to the write bit line and the write bit line, outputting data of the read bit line to the outside and outputting external data to the write bit line. The semiconductor device according to claim 5. 7. A memory cell including a plurality of n (n is a natural number excluding 1) bit lines and m (m is a natural number excluding 1) word lines connected to the memory cell. A memory cell array and a number (a
Is a natural number excluding 1), a decoding unit constituted by a gate for taking the logical sum of outputs of the decoding unit, and a word line driving unit which inputs the output of the decoding unit and drives the word line An address decoding unit comprising: a charge unit connected to the bit line to charge the bit line; connected to the bit line to output data of the bit line to the outside; And input / output means for outputting the same address signal to the bit line, wherein each of the a decoding units is differently coded with respect to the same address signal, and decodes specific different address signals to obtain the same A semiconductor memory device for driving the word line of the semiconductor memory device. 8. A memory cell including a plurality of n (n is a natural number excluding 1) bit lines and m (m is a natural number excluding 1) word lines connected to the memory cell. A memory cell array, a series connection of a series transistors (a is a natural number excluding 1) composed of a single conduction type transistor for the number of bits to be decoded and a control signal, and another conduction type transistor; a decoding unit in which one of the a series transistors is connected to a first potential, the other is connected to the transistor and becomes an output, and the other of the transistors is connected to a second potential; An address decoding unit comprising an output of the decoding unit and a word line driving unit for driving the word line; and an address decoding unit connected to the bit line. Charge means for charging a line; and input / output means connected to the bit line for outputting data of the bit line to the outside and outputting external data to the bit line. A semiconductor memory device wherein different coding is applied to the same address signal, and a specific different address signal is decoded to drive the same word line. 9. A memory cell array, comprising: an output unit for outputting data of a memory element to a read bit line; a read word line connected to the output unit; and a memory for inputting data of a write bit line. An input means for outputting to the element; and a plurality of memory cells having a write word line connected to the input means. A charge means is connected to the read bit line, and the input / output means is the read bit line. 9. The semiconductor memory device according to claim 7, further comprising a structure connected to the write bit line to output data of the read bit line to the outside and output external data to the write bit line. Semiconductor device.