JP2745250B2 - Data flow type information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data flow type information processing apparatus, and more particularly to a data flow type information processing apparatus in which a plurality of instructions are simultaneously driven by data.

[0002]

2. Description of the Related Art In a conventional Neumann computer, various instructions are stored in a program memory in advance as programs, and instructions are sequentially read out by sequentially specifying addresses of the program memory by a program counter, and the instructions are executed. You.

On the other hand, a data flow type information processing device is a type of non-Neumann computer which does not have the concept of executing instructions sequentially by a program counter. Such a data flow type information processing apparatus employs an architecture based on parallel processing of instructions. In a data flow type information processing device, an instruction can be executed as soon as data to be processed is prepared, and a plurality of instructions are simultaneously driven by the data, so that a program is executed in parallel according to a natural flow of data. Is done. as a result,
It is considered that the time required for the operation is significantly reduced.

FIG. 16 is a block diagram showing an example of the configuration of a conventional data flow type information processing apparatus. FIG.
FIG. 3 is a diagram showing an example of a field configuration of a data packet processed by the information processing device.

[0005] The data packet shown in FIG. 17 includes a destination field, an instruction field, a data 1 field and a data 2 field. Destination information is stored in the destination field, instruction information is stored in the instruction field, and operand data is stored in the data 1 field or the data 2 field.

The information processing apparatus shown in FIG. 16 has a program storage unit 1, a paired data detection unit 2, and an arithmetic processing unit 3.
including. The program storage unit 1 stores a data flow program 10 shown in FIG. Each line of the data flow program 10 includes a destination information 11, an instruction information 12, a copy presence / absence information 13, and a constant presence / absence information 14.
Consists of When the constant presence / absence information indicates “present”, the next row stores the constant data 15. As shown in FIG. 18, the program storage unit 1 specifies the destination based on the destination information of the input data packet, as shown in FIG. / No information 14 is read out, the destination information 11 and the instruction information 12 are stored in the destination field and the instruction field of the data packet, and the data packet is output.

[0007] The paired data detecting unit 2 includes a program storage unit 1
Queuing of data packets output from
That is, when the instruction information indicates a two-input instruction, two different data packets having the same destination information are detected, and the operand data (data 1 in FIG. 17) of one of the data packets is detected.
Is stored in the data 2 field of the other data packet, and the other data packet is output. If the command information indicates a one-input command,
The input data packet is output as it is.

The arithmetic processing unit 3 performs an arithmetic process on the data packet output from the data detecting unit 2 based on the instruction information, stores the result in the data 1 field of the data packet, and Is output to the program storage unit 1.

The program storage unit 1 and the data detection unit 2 are connected by two data transmission lines 4a and 4b. A data packet output from the program storage unit 1 is selectively transmitted through one of the data transmission paths 4a and 4b in accordance with whether operand data is right operand data or left operand data in arithmetic processing. You. The paired data detection unit 2 and the arithmetic processing unit 3 are connected by a data transmission line 5, and the arithmetic processing unit 3 and the program storage unit 1 are connected by a data transmission line 6.

The data packet is stored in the program storage unit 1,
By continuing to go around the paired data detecting unit 2, the arithmetic processing unit 3, and the program storage unit 1 in order, the arithmetic processing based on the data flow program 10 stored in the program storage unit 1 proceeds.

FIG. 19 is a diagram showing an example of a data flow graph. In FIG. 19, node N1 indicates an addition instruction, node N2 indicates a multiplication instruction, and node N3 indicates a subtraction instruction. Node N4 indicates a decrement instruction, and node N5 indicates an increment instruction. The instructions at nodes N1, N2, and N3 are two-input instructions,
The instructions of 4, N5 are one-input instructions. The operation result of the node N1 is referred to by the nodes N2 and N3. In this case, copy processing is performed in the program storage unit 1.

Next, the copying process will be described.
First, from the data flow program 10, the contents of the row specified by the address based on the destination information of the input data packet are read. At this time, copy existence / non-information 1
If 3 indicates "absent", a data packet in which the contents of the destination field and the instruction field are updated is output, and the process ends.

On the other hand, if the copy presence / absence information 13 indicates "present", a data packet in which the contents of the destination field and the instruction field are updated is output, and
Destination information 11, instruction information 12, stored in the next line,
The copy presence / absence information 13 and the constant presence / absence information 14 are read. If the copy presence / absence information 13 read from the next row indicates "absence", the same data as the input data packet is stored in the data 1 field of the new data packet, and the new data packet is stored. The destination information and the instruction information currently read are stored in the destination field and the instruction field, respectively, and the new data packet is output. With copy read from next line /
If the non-information 13 indicates "present", a similar copy process is further performed.

If the constant presence / absence information 14 indicates "present", constant output processing for reading the constant data 15 stored in the next row is performed.

In the above information processing apparatus, once the copy process or the constant output process is performed, the flow rate of the data packet input to the program storage unit 1 and the flow rate of the data packet output from the program storage unit 1 The ratio will always be 1: 2. Here, the data packet flow rate refers to the number of data packets passing through each part per unit time.

FIGS. 20 and 21 show the flow rate of data packets in each data transmission path when the flow rate of data packets in the data transmission path 6 is 1. FIG.

FIG. 20 shows the flow rate when one input instruction is 0%, two input instructions is 100%, and all instructions have copy processing or constant output processing.
When copy processing or constant output processing is performed in the program storage unit 1, the flow rates of the data transmission paths 4a and 4b become 1 respectively. When the command information indicates a two-input command, the paired data detector 2 waits for a paired data packet to be input, so that the data flow rate 1 of each of the data transmission paths 4a and 4b is On the other hand, data packets with a flow rate of 0.5 are output. Therefore, the data packet of the flow rate 1 is input to the arithmetic processing unit 3.

FIG. 21 shows that one input instruction is 100%,
The worst case shows the flow rate when the 2-input instruction is 0% and all instructions have a copy process or a constant output process. When copy processing or constant output processing is performed in the program storage unit 1, the flow rates of the data transmission paths 4a and 4b become 1 respectively. Instruction information is 1
When the input command is indicated, the paired data detecting unit 2 does not wait for a paired data packet, so that the flow rate of each of the data transmission paths 4a and 4b is 1
, A data packet with a flow rate of 1 is generated.
However, since the maximum flow rate of the data transmission line 5 is 1, only data packets of the flow rate 1 are input to the arithmetic processing unit 3 as in the case of FIG.

[0019]

As described above, the conventional data flow type information processing apparatus performs processing at the highest operation rate when the data flow program to be executed has 100% two-input instructions. Do. Therefore, as the number of one-input instructions in the data flow program increases, the processing efficiency inherent in the data flow program cannot be achieved.

A data packet which makes a round between the processing units in the information processing apparatus in order based on the execution order of the data flow program stored in the program storage unit 1 is always processed in the form shown in FIG. Therefore, the width of the data line (data transmission path) connecting the processing units is useless.

That is, originally, when reading a data flow program from the program storage unit 1, only the contents of the destination field in the data packet designating the next instruction information are necessary. The contents of the field and the data 2 field are unnecessary. Also in the arithmetic processing unit 3, the contents of the instruction field, the data 1 field and the data 2 field in the data packet are necessary, and the contents of the destination field in the data packet are unnecessary. Therefore, there is a problem that a great waste is physically generated when configuring the information processing apparatus.

An object of the present invention is to provide a data flow type information processing apparatus which can achieve high processing efficiency even when there are many one-input instructions and has a reduced physical scale.

[0023]

A data flow type information processing apparatus according to the present invention comprises a first and a second program storage means, a first and a second arithmetic processing means, a first, a second and a third processing means. The apparatus includes a merging unit, a paired data detecting unit, and a supplying unit.

The first and second program storage means include:
A data flow program is stored, and at least next-order destination information and instruction information are read from the data flow program based on the input destination information. The first and second arithmetic processing means are provided corresponding to the first and second program storage means, and based on input command information,
The arithmetic processing is performed on the input data, and data indicating the operation result is output.

The first merging means merges the destination information and the instruction information read from the first program storing means with the data output from the first arithmetic processing means. The second merging unit merges the destination information and the instruction information read from the second program storage unit with the data output from the second arithmetic processing unit. The third merging means arbitrates the outputs of the first and second merging means.

The paired data detecting means receives the destination information and the command information output from the third merging means together with the data corresponding to the information, and receives one or a plurality of data corresponding to the same destination information as the destination information and the command. Output with information. The supply means supplies the destination information of the output from the data pair detection means to the first or second program storage means, and supplies the instruction information and the data to the corresponding arithmetic processing means.

The first merging means, when the destination information and the instruction information and other information are simultaneously read out from the first program storage means, transfers the other information in parallel with the destination information and the instruction information to a third merging means. Give to the means. The second merging means, when the destination information and the instruction information and the other information are simultaneously read out from the second program storage means, supplies the other information to the third merging means in parallel with the destination information and the instruction information. . The third merging means, when another information is provided in parallel with the destination information and the instruction information from the first or second merging means, the other information in parallel with the destination information and the instruction information and the data detecting means. Give to.

[0028]

In the data flow type information processing apparatus according to the present invention, two program storage means and two operation processing means are provided, and the data output from the output unit of the data detection means is used for two operation processing. Since each instruction is given to each means, even if one input instruction is included 100% and all instructions have copy processing or constant output processing, the processing efficiency is twice as high as that of the conventional data flow type information processing apparatus. be able to.

Further, a supply means for separating the destination information from the command information and the data, and first, second and third merging means for combining the destination information, the command information and the data separated by the supply means are provided. Have been. Thereby, the minimum information is sent to each processing means. Therefore, the width of the data line (data transmission path) connecting each processing means can be reduced.

Further, even when other information is simultaneously read out together with the destination information and the instruction information from the first or second program storage means, the first or second merging means and the third merging means keep the information. Are given to the paired data detecting means in parallel. Therefore, the destination information can be combined with the corresponding instruction information and data without adding special identification information to the separated destination information and instruction information.

[0031]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a data flow type information processing apparatus according to one embodiment of the present invention.

Referring to FIG. 1, a data flow type information processing apparatus includes first and second program storage units 1a and 1b,
A pair data detection unit 2 and first and second arithmetic processing units 3a and 3b are included. The first on the input side of the data detector 2
Second and third merging sections 21 a, 21 b, 21 c are provided, and a branch section 22 is provided on the output side of the data detecting section 2. An input unit 23 for inputting a data packet from outside and an output unit 24 for outputting a data packet to the outside are provided. The input unit 23 and the branch unit 22 have a packet buffering function.

The first and second program storage units 1a, 1a
The configuration and operation of each of 1b are the same as the configuration and operation of program storage unit 1 shown in FIG. The configuration and operation of paired data detection unit 2 are the same as the configuration and operation of paired data detection unit 2 shown in FIG. The configuration and operation of each of first and second arithmetic processing units 3a and 3b are the same as the configuration and operation of arithmetic processing unit 3 shown in FIG.

FIG. 2 shows the structure of the first junction 21a. The first junction 21a has four input ports I1, I
2, I3, I4 and four output ports O1, O2, O
3, O4. The data packets output from the output ports O1 and O2 are synchronized with each other. The data packets output from the output ports O3 and O4 are synchronized with each other.

The configuration of the second junction 21b is the same as the configuration of the first junction 21a. FIG. 3 shows the third junction 21.
The configuration of c is shown. The third junction 21c includes two circuit portions 7A and 7B.

Data transmission path 3 from first junction 21a
7A is connected to the junction circuit 71A, and the first junction 21a
Is connected to a junction circuit 72A via a buffer 73A. The data transmission path 37B from the second junction 21b is connected to the junction circuit 72A,
The data transmission path 39B from the second junction 21b is connected to a junction circuit 71A via a buffer 74A.

Data transmission path 3 from first junction 21a
8A is connected to the merging circuit 71B and the first merging portion 21a
Is connected to a merging circuit 72B via a buffer 73B. The data transmission line 38B from the second junction 21b is connected to the junction circuit 72B,
The data transmission path 40B from the second junction 21b is connected to a junction circuit 71B via a buffer 74B.

The junction circuit 71A outputs the data packet from the data transmission path 37A and the data packet from the data transmission path 39B to the data transmission path 7L on a first-come, first-served basis.
The junction circuit 72A outputs the data packet from the data transmission path 39A and the data packet from the data transmission path 37B to the data transmission path 8L on a first-come, first-served basis.

When a data packet from the data transmission path 37A and a data packet from the data transmission path 39B are input simultaneously, the data packet from the data transmission path 37A is input to the joining circuit 71A with priority and the data transmission is performed. The data packet from the path 39B is stored in the buffer 74A.
Is stored temporarily. When the data packet from the data transmission path 37B and the data packet from the data transmission path 39A are input simultaneously, the data transmission path 37B
Is given to the joining circuit 72A with priority, and the data packet from the data transmission path 39A is temporarily stored in the buffer 73A. The operation of the circuit portion 7B is similar to the operation of the circuit portion 7A.

Next, with reference to FIG. 4, a configuration of a portion related to the first program storage section 1a and the first arithmetic processing section 3a will be described.

Data transmission paths 31A and 32A are connected to two input ports of the input section 23, respectively. As shown in FIG. 5, a data packet 31P including a destination field 31a and an instruction field 31b is provided to the data transmission path 31A. As shown in FIG. 5, a data packet 32P including a data field 32a is provided to the data transmission path 32A. Input unit 23-2
The two output ports are connected to the input ports I1 and I2 of the first junction 21a via the data transmission lines 33A and 34A.

Data transmission lines 35A and 36A are connected to the two output ports of the first program storage section 1a, respectively. The data transmission path 35A is connected to the first junction 21
a of the data transmission line 3
6A is connected to the input ports I1 and I3 of the first junction 21a. As shown in FIG. 6, a destination field 35a and an instruction field 35
b or a data packet 35PB including a constant data field 35c. In the data transmission path 36A, as shown in FIG.
A data packet 36P including a destination field 36a, a flag 36b, and an instruction field 36c is provided.

On the other hand, a data transmission line 48A is connected to an output port of the first arithmetic processing unit 3a. The data transmission line 48A is connected to the input ports I2 and I4 of the first junction 21a.
It is connected to the. As shown in FIG. 7, a data packet 48P including a data field 48a is provided to the data transmission path 48A.

Four output ports O of the first junction 21a
1, O2, O3, and O4 are data transmission paths 37A, respectively.
-40A to the third junction 21c. As shown in FIG. 8, a data packet 37P including a destination field 37a and an instruction field 37b is provided to the data transmission path 37A. Data transmission path 38
A is provided with a data packet 38P including a data field 38a, as shown in FIG. As shown in FIG. 9, a destination field 39 is provided in the data transmission path 39A.
a and a data packet 39P including an instruction field 39b. As shown in FIG. 9, a data packet 40PA including a constant data field 40a or a data packet 40PB including a data field 40b is provided to the data transmission path 40A.

The two output ports of the data detector 2 are
It is connected to two input ports i1 and i2 of the branch unit 22 via the data transmission lines 41A and 42A. As shown in FIG. 10, a destination field 4
A data packet 41P including 1a and an instruction field 41b is provided. FIG. 1 shows the data transmission path 42A.
As indicated by 0, a data packet 42P including a data 1 field 42a and a data 2 field 42b is provided.

The first output port o1 of the branch unit 22 is connected to the first program storage unit 1a via the data transmission path 43A.
Connected to the first input port of the output unit 24 via the data transmission path 44A, and connected to one input port of the first arithmetic processing unit 3a via the data transmission path 45A. I have. The second output port o2 of the branch unit 22 is connected to the second output port o2 of the output unit 24 via the data transmission line 46A.
And the other input port of the second arithmetic processing unit 3a via the data transmission path 47A. In the data transmission path 43A, as shown in FIG.
A data packet 43P including a destination field 43a is provided, and a data packet 45 including an instruction field 45a is provided on a data transmission path 45A as shown in FIG.
P is given. As shown in FIG. 12, a data packet 47P including a data 1 field 47a and a data 2 field 47b is provided to the data transmission path 47A.

The two output ports of the output section 24 are connected to data transmission lines 49A and 50A, respectively. As shown in FIG. 13, a data packet 49P including a destination field 49a and an instruction field 49b is provided to the data transmission path 49A, and a data packet 50A including a data field 50a is provided to the data transmission path 50A as shown in FIG. Packet 50P is provided.

Second program storage section 1b in FIG.
And the configuration of a portion related to the second arithmetic processing unit 3b is as follows:
First program storage unit 1a and first arithmetic processing unit 3
The configuration is the same as that of the parts related to the data transmission paths 31A to 50A.
50B.

Next, with reference to FIG. 4, the operation of the parts related to the first program storage unit 1a and the first arithmetic processing unit 3a will be described.

First, a pair of data packets 31P and 32P are input to the input unit 23. These data packets 31P and 32P are sent to the input ports I1 and I2 of the first junction 21a, respectively. At the first time, these data packets 31P, 32P are connected to the output ports O1,
From O2, as the data packets 37P and 38P, respectively, via the third merging unit 21c, the data detecting unit 2
Sent to The above operation is repeated. When two pairs of data packets having the same destination information are detected by the paired data detection unit 2, the paired data detection unit 2 outputs a pair of data packets 41P and 42P.

The branching unit 22 receives these data packets 4
Continue internal processing for 1P, 42P, or
The user selects whether to send these data packets 41P and 42P to the output unit 24. If internal processing continues,
The branching unit 22 separates the data packet 41P into a data packet 43P including a destination field and a data packet 45P including an instruction field.
P is sent to the first program storage unit 1a, and the data packet 45P is sent to the first arithmetic processing unit 3a. Further, the branching unit 22 converts the data packet 42P into the data packet 47P.
To the first arithmetic processing unit 3a.

The data packets 41P and 42P are output from the output unit 2
4, the data packet 41P is not separated. The data packet 41P sent to the output unit 24 is output as a data packet 49P, and the data packet 42P sent to the output unit 24 is output as a data packet 50P.

The first arithmetic processing unit 3a performs an arithmetic operation on one or two operand data stored in the data packet 47P based on the instruction information stored in the data packet 45P, and indicates the operation result. Only the data is output as the data packet 48P.

On the other hand, in the first program storage section 1a,
By address designation based on the destination information stored in the data packet 43P, the next destination information 11, instruction information 12, copy presence / absence information 13, and constant presence / absence information 14 of the data flow program 10 shown in FIG. Is read. In the data transmission path 36A, destination information, instruction information, and flags (copy / no information and constant / no information)
Is output. With copy /
When the non-information indicates “present”, the data transmission path 3
5A, a data packet 35PA including destination information and instruction information at the next address is output. With constant /
When the non-information indicates "present", a data packet 35PB including the constant data 15 (see FIG. 18) at the next address is output to the data transmission path 35A. When the copy presence / absence information indicates “absence” and the constant presence / absence information indicates “absence”, a data packet including information at the next address is output to the data transmission path 35A.
The data packet is deleted at the first junction 21a.

Thereafter, similarly, each data packet sequentially circulates through each processing unit, whereby the processing according to the data flow program 10 proceeds.

The first junction 21a arbitrates between a data packet supplied from the outside and a data packet processed inside. The data packets output from the first junction 21a are classified into the following four cases.

(1) When both the copy presence / absence information and the constant presence / absence information indicate “absence”, the data packet 36
P is output from output port O1 as data packet 37P, and data packet 48P is output from output port O2 as data packet 38P.

(2) When the copy presence / absence information indicates “present”, the data packet 36P is
And the data packet 48P is output from the output port O1 as the data packet 38P.
2 output. At the same time, data packet 35PA is output from output port O3 as data packet 39PA, and data packet 48P is output as data packet 4PA.
It is output from the output port O4 as 0PB.

(3) When the constant presence / absence information indicates "present", the data packet 36P is output from the output port O1 as the data packet 37P, and the data packet 48P is output as the data packet 38P from the output port O2.
Output from At the same time, the data packet 36P is output from the output port O3 as the data packet 39PB, and the data packet 35PB is
It is output from the output port O4 as 0PB.

(4) Data packets 31P, 3 from outside
If 2P are given, those data packets 3
1P and 32P are data packets 37P and 38P, respectively.
Are output from the output ports O1 and O2.

When the internally processed data packet 36P and the externally applied data packet 31P compete with each other, the internally processed data packet 36P is output from the output port O1 with priority. Non-prioritized data packets are kept waiting until there is no competitor.

At the output port O2, if the data packet 36P internally processed at the output port O1 is selected, the data packet 48 output from the first arithmetic processing section 3a is output.
When P is selected and the externally supplied data packet 31P is selected at the output port O1, the externally supplied data packet 32P is selected. Data packet 38P is output in synchronization with data packet 37P. Unselected data packets are waited.

On the other hand, when both the copy presence / absence information and the constant presence / absence information indicate "absence", nothing is output from the output port O3. When the externally supplied data packet 31P is selected at the output port O1, the output from the output port O3 is waited.

Data packet 35PA at output port O3
Is selected, the data packet 48P is selected at the output port O4. When the data packet 36P is selected at the output port O3, the data packet 35PB is selected at the output port O4. Data packet 40
PA and 40PB are output in synchronization with data packets 39PB and 39PA.

However, unlike the output port O2, at the output port O4, the unselected pair of the pair of data packets 35PA and 48P and the pair of data packets 36P and 35PB is deleted. When both the copy presence / absence information and the constant presence / absence information indicate “absence”,
Nothing is output from the output port O4. That is, the two sets of data packets are both erased.

The data packet 42P output from the data detection unit 2 has the corresponding instruction information of 1
When an input command is indicated, operand data is stored only in the data 1 field, and when the corresponding command information indicates a 2-input command, operand data is stored in the data 1 field and the data 2 field.

As described above, even when another data packet 35PA or 35PB is output simultaneously with the data packet 36P including the destination information and the instruction information, such as when the copy processing is performed or when a constant is output. , The first merging unit 21a supplies the data packets in parallel to the paired data detecting unit 2 via the third merging unit 21c.

Therefore, without giving special identification information to the data packet separated by the branching unit 22,
A new data packet read from the first program storage unit 1a can be combined with a corresponding data packet processed by the first arithmetic processing unit 3a.

The operation of the portion related to the second program storage section 1b and the second arithmetic processing section 3b in FIG. 1 is the same as the above operation.

FIGS. 14 and 15 show the flow rate of the data packet of each part. FIG. 14 shows the flow rate when one input instruction is 0%, two input instructions is 100%, and all instructions have copy processing or constant output processing. First and second program storage units 1a and 1b
It is assumed that a data packet with a flow rate of 0.5 is input to each of the. When the copy processing or the constant output processing is performed in the first program storage unit 1a, data packets having a flow rate of 0.5 are output to the data transmission paths 35A and 36A, respectively. Similarly, the second program storage unit 1b
When a copy process or a constant output process is performed in the data transmission paths 35B and 36B,
Is output. Therefore, the flow rate of the data packets output to the data transmission lines 7L, 8L, 9L, and 10L is 1 respectively.

When the command information of the data packet from the data transmission line 7L indicates a two-input command, the flow rate of the data packet output from the two output ports of the data detector 2 is 0.5 and 0.5, respectively. Become. When the command information of the data packet from the data transmission line 9L indicates a two-input command, the flow rate of the data packet output from the remaining two output ports of the data detector 2 is 0.5 Becomes Therefore, the data transmission lines 45A, 47A, 4
Data packets with a flow rate of 0.5 are sent via 5B and 47B, respectively.

Each of the first and second arithmetic processing units 3a and 3b processes a data packet having a flow rate of 0.5.
The flow rate of data packets processed by the entire information processing device is 1
Becomes The processing efficiency in this case is the same as the processing efficiency shown in FIG.

FIG. 15 shows that one input command is 100%,
The worst case shows the flow rate when the 2-input instruction is 0% and all instructions have a copy process or a constant output process. In this case, it is assumed that a data packet with a flow rate of 1 is input to each of the first and second program storage units 1a and 1b. When a copy process or a constant output process is performed in the first program storage unit 1a, a data packet with a flow rate of 1 is output to each of the data transmission paths 35A and 36A. Similarly, when copy processing or constant output processing is performed in the second program storage unit 1b, a data packet with a flow rate of 1 is output to each of the data transmission paths 35B and 36B. Third junction 2
1c arbitrates the data packet from the first junction 21a and the data packet from the second junction 21b, so that the data packets having the flow rate 1 are output to the data transmission paths 7L, 8L, 9L, and 10L, respectively. .

When the command information of the data packet from the data transmission path 7L indicates one input command, the data packet from the data transmission path 7L and the data packet from the data transmission path 8L are output to the data transmission paths 41A and 42A as they are. You. When the command information of the data packet from the data transmission path 9L indicates one input command, the data transmission path 9L
The data packet from L and the data packet from data transmission path 10L are output to data transmission paths 41B and 42B as they are. Therefore, the first and second arithmetic processing units 3a, 3b are provided with data transmission lines 45A, 47A, 45A.
Data packets with a flow rate of 1 are sent via B and 47B, respectively. Since each of the first and second arithmetic processing units 3a and 3b processes the data packet of the flow rate 1, the information processing device processes the data packet of the flow rate 2.
In this case, a processing efficiency twice as high as the processing efficiency shown in FIG. 21 is achieved.

As described above, according to the above embodiment, even if one input instruction is 100% and all instructions have copy processing or constant output processing (worst case), the conventional information processing is performed. It is possible to draw out twice the processing efficiency as compared with the apparatus.

Further, since a data packet including only information required by the processing unit is sent to each processing unit, the width of a data line forming a data transmission path for transmitting the data packet can be reduced. it can.

[0078]

As described above, according to the present invention, even when the data flow program has many one-input instructions, it is possible to achieve the processing efficiency inherent in the program. Therefore, the processing efficiency of the data flow type information processing device is improved.

Further, since the minimum data packet required by each processing unit is sent to each processing unit in the information processing apparatus, the width of the data line connecting each processing unit can be reduced.

Further, when other information is read simultaneously with the destination information and the instruction information from the first or second program storage means, the information is sent in parallel to the paired data detection means, so that special identification information is obtained. , The separated destination information, instruction information and data can be combined.

Therefore, the size of the packet can be reduced, and the chip area when the information processing apparatus is formed into an LSI can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data flow type information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a first merging unit included in the embodiment.

FIG. 3 is a block diagram illustrating a configuration of a third merging unit included in the embodiment.

FIG. 4 is a diagram for explaining the operation of the embodiment.

FIG. 5 is a diagram showing a field configuration of a data packet processed by the embodiment.

FIG. 6 is a diagram showing a field configuration of a data packet processed by the embodiment.

FIG. 7 is a diagram showing a field configuration of a data packet processed by the embodiment.

FIG. 8 is a diagram showing a field configuration of a data packet processed by the embodiment.

FIG. 9 is a diagram showing a field configuration of a data packet processed by the embodiment.

FIG. 10 is a diagram showing a field configuration of a data packet processed by the embodiment.

FIG. 11 is a diagram showing a field configuration of a data packet processed by the embodiment.

FIG. 12 is a diagram showing a field configuration of a data packet processed by the embodiment.

FIG. 13 is a diagram showing a field configuration of a data packet processed by the embodiment.

FIG. 14 is a diagram showing the flow rate of each unit when the two-input command is 100%.

FIG. 15 is a diagram showing a flow rate of each unit when one input command is 100%.

FIG. 16 is a diagram illustrating an example of a configuration of a conventional data flow type information processing apparatus.

FIG. 17 is a diagram illustrating a field configuration of a data packet processed in the data flow type information processing apparatus.

FIG. 18 is a diagram illustrating a part of a data flow program stored in a program storage unit of the data flow type information processing device.

FIG. 19 is a diagram showing a part of a data flow graph including a copy process.

FIG. 20 is a diagram showing a flow rate of each unit of the conventional data flow type information processing apparatus when a two-input instruction is 100%.

FIG. 21 is a diagram showing a flow rate of each unit of the conventional data flow type information processing apparatus when one input command is 100%.

[Explanation of symbols]

1a: first program storage unit 1b: second program storage unit 2: paired data detection unit 3a: first arithmetic processing unit 3b: second arithmetic processing unit 21a: first merging unit 21b: second Merging part 21c: Third merging part 31A to 50A, 31B to 50B, 7L to 10L ... Data transmission line In each drawing, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A data flow type information processing apparatus for performing information processing based on a data flow program including a plurality of sets of destination information and instruction information, the data flow type information processing apparatus storing a data flow program, and based on input destination information. First and second program storage means for reading at least the next-order destination information and instruction information from the data flow program, provided corresponding to the first and second program storage means, First and second arithmetic processing means for performing arithmetic processing on the input data based on the input data and outputting data indicating an arithmetic result, and reading destination information and instruction information read from the first program storage means into the first and second arithmetic processing means. First merging means for merging with data output from the first arithmetic processing means, and reading from the second program storage means A second merging means for merging the obtained destination information and instruction information with the data output from the second arithmetic processing means, a third merging means for arbitrating the outputs of the first and second merging means, Paired data detecting means for receiving destination information and instruction information output from the third merging means together with data corresponding to the information, and outputting one or more data corresponding to the same destination information together with the destination information and instruction information; And supply means for providing destination information to the first or second program storage means and providing instruction information and data to the corresponding arithmetic processing means, among the outputs from the paired data detection means, Means for reading the destination information and the instruction information when other information is simultaneously read out from the first program storage means together with the destination information and the instruction information; The other information is provided to the third merging means in parallel, and the second merging means reads the other information together with the destination information and the instruction information from the second program storage means, The other information is provided to the third merging unit in parallel with the destination information and the instruction information, and the third merging unit includes:
When the other information is given in parallel with the destination information and instruction information from the first or second merging means, the other information is sent to the paired data detection means in parallel with the destination information and instruction information. Give, data flow type information processing device.