JP2744457B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a fine semiconductor device having a large storage capacity and a method for manufacturing the same as a dynamic random access memory (DRAM) particularly suitable for high integration. .

[Conventional technology]

DRAM (Dynamic Randam Access Memory) has achieved a fourfold improvement in integration in three years, and mass production of megabit-class memories has already been carried out. The high integration has been achieved mainly supported by miniaturization of element dimensions. However, due to the decrease in storage capacitance due to miniaturization of elements, problems such as a decrease in signal-to-noise (SN) ratio and signal inversion (soft error) due to the incidence of α-rays have become apparent, and maintaining reliability has been an issue. It has become.

Therefore, as a memory cell whose storage capacity can be increased,
As described in JP-A-63-58958, a memory cell structure in which storage capacitance portions are stacked in several layers,
As described in JP-A-63-209157, there has been proposed a structure utilizing a side capacitance component due to a side wall of a capacitor.

[Problems to be solved by the invention]

FIG. 2 shows the above-mentioned conventional memory cell. The memory cell of this structure can theoretically increase the storage capacity by stacking multiple charge storage electrodes. However, in view of the actual capability of the manufacturing technology such as the depth of focus of the exposure apparatus, it is not preferable to generate a large step. The step allowed in the storage capacitor is 0.5 μm in a 64 mega DRAM using a 0.3 μm technology.
Will be about. That is, in the case of the structure shown in FIG.
If the thickness of each electrode is 0.1 μm, it is considered that the limit is two storage electrodes and three plate electrodes. The number of opposing surfaces of the storage electrode and the plate electrode which can be constituted by this number of electrodes is a maximum of four. The cell area is estimated to be about 1 μm ^{2 in a} 64 mega DRAM. Assuming that 1 × 1 μm ² can be used as it is as a storage capacitor and that there is a 40% ineffective area for connecting the upper and lower electrodes, the effective area as a capacitor in the structure shown in FIG. 2 is 1 μm × 1 μm × 4 faces × 0.6 = 2.4 μm ² (1)

Further, in order to realize the above structure, at least two deposition steps of the storage electrode (material), at least two formation steps of the inter-electrode insulating film, at least one processing step of connecting the upper and lower electrodes, A step of forming a capacitor insulating film, a step of forming a plate electrode, and the like are required, resulting in a problem that the number of steps is extremely large.

On the other hand, the present invention shown in FIG. 1 reduces the number of steps and
It is possible to form a large area storage capacitor. For example, in the case of forming a storage capacitor of 1 × 1 μm ² and a thickness of 0.5 μm in the same manner as described above, if electrodes having a thickness of 0.1 μm are used, the total surface area of the storage capacitor can be calculated as follows (because there is no connection portion, There is no invalid area).

Outer wall side surface component (height) 0.4 μm × 1 μm × 4 = 1.6 μm ² (2) Inner wall side surface component (height) 0.3 μm × (1-0.1 × 2) μm × 4 = 0.96 μm ²
(3) Planar area component 1 μm × 1 μm = 1 μm ² (4) Therefore, the total is considered as follows.

1.6 + 0.96 + 1 = 3.56 μm ² (5) Although the structure is simple and the process is short, a storage capacitor surface area 50% larger than that of the memory cell shown in FIG. 2 can be realized.

[Means for solving the problem]

Increasing the area of storage capacitance is the biggest challenge for DRAM, and to achieve this challenge, as described above,
It is better to double the peripheral side wall component than to double the plane area component. This is because DRAMs reduce the cell area and storage capacity area by 1/3 for each generation, but the peripheral length of storage capacity,
That is, the peripheral area component is This is because they only shrink. Doubling the peripheral area component having a small reduction ratio has a greater area increasing effect.

That is, in the present invention, a wall-shaped storage electrode structure is used, and the outer and inner walls thereof are used as storage capacitors.
With a structure in which the area is not easily reduced even with miniaturization of cells,
It is to obtain a manufacturing method.

[Action]

In the present invention, since the wall-shaped storage electrode structure is used as described above, the occupied area of the side wall can be doubled by utilizing the outer wall and the inner wall of the wall as capacitors. Further, by increasing the number of walls concentrically, it is possible to further increase the side wall area component.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. First
FIGS. 3A to 3J are cross-sectional views showing a semiconductor device according to a first embodiment of the present invention, FIGS. 3A to 3J are diagrams showing manufacturing steps of the above-described embodiment, respectively, and FIG. 4 is a second embodiment of the present invention. 5, (a) and (b) are views showing the manufacturing method of the above embodiment, FIG. 6 is a view showing an example of the layout, and FIG. 7 is a view showing another example of the layout. FIG. 8 is a sectional view showing a third embodiment of the present invention.

First Embodiment In FIG. 1, since the storage electrodes 18 are stacked on the word lines 14 and the bit lines 16, the plane area of the storage electrodes 18 can be maximized except for the space between the storage electrodes. Can be bigger. Furthermore, as a result of adopting a wall-shaped structure for the storage electrode 18, the inner wall surface of the wall can be used as a storage capacitor, so that the storage capacity can be increased.

3 (a) to 3 (j) are views showing respective steps for manufacturing the structure of the first embodiment shown in FIG. Next, the manufacturing method will be described with reference to FIG. First, a p-type (100) oriented Si substrate 1 having a specific resistance of 10 Ωcm
On FIG. 1, an isolation 12 and a gate oxide film 13 are formed as shown in FIG. Then polycrystalline Si14 SiO ₂ and a CVD method doped with phosphorus than about 10 ²⁰ cm ^-3 (Chemical
After deposition by the Vapor Deposition method, these SiO ₂ and polycrystalline Si are processed by anisotropic dry etching using a resist pattern (not shown) as a mask.
As shown in FIG. 3B, a word line 14 (polycrystalline Si) and an SiO ₂ layer 31 are formed. Polycrystalline Si thickness 150nm, SiO
The thickness of the _two layers 31 is 200 nm.

The word line 14 is masked to form the n ⁺ diffusion layer 113 in FIG.
As shown in FIG. Next thickness
100 nm of SiO ₂ is deposited by CVD and processed by anisotropic dry etching to form SiO ₂ 32 on the side walls of the word lines. Thereafter, SiO ₂ 33 having a thickness of 50 nm is deposited by a CVD method. A region where the bit line is to be brought into contact with the diffusion layer in the future is processed by anisotropic dry etching using a resist as a mask (not shown), and a desired portion of the n ⁺ diffusion layer 113 is formed as shown in FIG. Expose. Next, polycrystalline Si (poly Si) 34 and SiO ₂ 35 doped with about 10 ²⁰ cm ^{−3 of} phosphorus are deposited by a CVD method as shown in FIG. Although not shown, the resist pattern is used as a mask to form the Si
O ₂ 35 and polycrystalline Si 34 are processed to form bit lines whose upper surfaces are covered with SiO ₂ 35, as shown in FIG. 3 (f). 100 nm thick SiO ₂ 36, 200 nm thick SiN ₄ 37, 150 n thick
Each of m ₂ SiO ₂ is deposited using a CVD method. At this time,
Note that the O ₂ 36 Figure 3 regions shown in (g) A (region where the future storage electrode and the n ⁺ diffusion layer contact) is not Shimawa filled is required. In this embodiment assuming a 64-Mega DRAM, the thickness of SiO ₂ 36 should be 200 nm or less. Further, the thickness of Si ₃ N ₄ 37 is such that the region A is almost completely filled,
In order to make the surface almost flat, a film thickness of about 100 nm or more is required. In the case of this embodiment, the thickness of Si ₃ N ₄ is made 100 nm or more. The thickness of the finally deposited SiO ₂ 38 is set so that the sum of the thicknesses of the already deposited SiO ₂ 36 and Si ₃ N ₄ 37 is equal to the height of the wall of the wall-shaped storage electrode, or a little. Set to be equal to the added margin.

Then, although not shown, the SiO ₂ 38, Si ₃ N ₄ 37, SiO ₂ 36, and SiO ₂ 33 are each etched using anisotropic dry etching using the resist pattern as a mask, thereby exposing the substrate of the portion A. . At this time, as apparent from FIG. 3 (g), the Si ₃ N ₄ 37 is buried in the portion A, that is, in the gap between the word lines 14, and the substantial film thickness to be etched is large. For this reason, an Si ₃ N ₄ etching technique having a high etching selectivity with respect to the underlying SiO ₂ 33 is required. Specifically, CF ₃ + O ₂ to etch the _{Si 3 N 4, CH 2 F} 2, CHF 3, CH
₃ F, a plasma etching technique using plasma, such as CH ₄ + F ₂ are preferred. When these gases are used, Si
The etching speed of Si ₃ N ₄ is about 10 times or more that of O ₂ , and it is possible to process Si ₃ N ₄ 37 without giving any damage (sharpening) to the underlying SiO ₂ 33 .

After the processing of these films is completed, polycrystalline Si39 doped with about 10 ²⁰ cm ^{-3 of} phosphorus is deposited by a CVD method. The film thickness is 100
nm was used. This film thickness is set so as not to completely fill the depressions such as SiO ₂ 36, Si ₃ N ₄ 37, and SiO ₂ 38. Thereafter, a resist having a thickness of 1 μm is applied, and the resist 131 is buried in the recess as shown in FIG. Subsequently, the polycrystalline Si39 is etched using anisotropic dry etching. The etching amount is slightly larger than the thickness of the polycrystalline Si39. Next, SiO ₂ 38 is etched with an HF aqueous solution, and Si ₃ N ₄ 37 is further etched with a phosphoric acid aqueous solution. Phosphoric acid temperature 1
If you choose about 60 ℃ ~ 180 ℃, about 100 nm Si ₃ N ₄ 37 will be several minutes ~
In several tens of minutes, etching can be performed as shown in FIG. Finally, a capacitor insulating film 132 and a plate electrode 133 are formed. In the present embodiment, SiO ₂ is used as the capacitor insulating film, but it goes without saying that an insulating film such as Ta ₂ O ₅ or Si ₃ N ₄ or a composite film thereof can be used. More KNO ₃
And other ferroelectric materials can be used. In this embodiment, polycrystalline Si in which phosphorus is diffused is used as the plate electrode 133. However, in addition to W, Mo, WSi ₂ and MoSi ₂ , various metal materials,
Metal silicide materials can be used.

Second Embodiment The second embodiment shown in FIG. 4 shows an example in which the storage electrode 18 has a double wall concentrically. Compared to the first embodiment shown in FIG. 1, it is possible to make the storage capacity about 50% higher.

FIGS. 5 (a) and 5 (b) are views showing a method for manufacturing the semiconductor device shown in the second embodiment, and FIGS. 3 (a) to 3 (g) are prior to FIG. 5 (a). The step ()) is easy to carry out. That is, after the step shown in FIG.
SiO ₂ 38, Si ₃ N ₄ 37, and SiO ₂ 36 were respectively etched by anisotropic dry etching, and phosphorus was successively added to 10 ²⁰ cm ^−3.
Lightly doped polycrystalline Si39 is deposited by CVD.
The thickness was 50 nm. Next, SiO ₂ 51 having a thickness of 80 nm is applied by a CVD method, and is further etched by an anisotropic dry etching method to leave SiO ₂ on the inner wall of the concave portion. Subsequently, polycrystalline Si52 doped with about 10 ²⁰ cm ^{-3 of} phosphorus was applied to a thickness of 50 nm by a CVD method as shown in FIG. Polycrystalline Si52 and polycrystalline using anisotropic dry etching
Etch Si39. Polycrystalline Si etching amount is 100n
m + α. α is the polycrystalline Si remaining in the adjacent recess,
As shown in FIG. 5B, the thickness is set so as not to cause a short circuit.

Thereafter, when a capacitor insulating film and a plate electrode are formed, a structure equivalent to the second embodiment shown in FIG. 4 is completed.

Further, this embodiment is shown an example of double wall concentrically, by repeating deposition of SiO ₂ as shown in FIG. 5, dry Etsu quenching, the polycrystalline Si deposition, triple In principle, it is also possible to make a quadruple wall.
However, in this case, each film thickness must be reduced so that the concave portion is not completely filled.

FIG. 6 is a diagram showing one layout of the semiconductor device according to the present invention. In the first or second embodiment shown in FIG. 1 or FIG. 4, since the bit line 16 is formed before the storage electrode, the wiring portion of the bit line is a portion where the storage electrode is in contact with the substrate. Need to be avoided. Therefore,
In this embodiment, the bit lines are formed above the memory cell area (upper in FIG. 6). In this embodiment, the storage electrode
The layout pattern for forming 65 is indicated by a hole pattern (a pattern in which the inside of a specified region is etched).

In the figure, 61 is an active region, 62 is a gate electrode (word line), 63 is a bit contact hole, 64 is a bit line,
Reference numeral 66 denotes a portion where the storage electrode 65 is in contact with the substrate.

Since the hole pattern generally tends to cause a hole thickening phenomenon at the time of processing, the distance between adjacent hole patterns is narrowed upon completion. That is, the distance between the hole patterns cannot be less than the resolution limit of the lithography technology, but the substantial hole pattern distance can be reduced by utilizing the hole thickening phenomenon at the time of processing as described above. . The hole pattern can be enlarged accordingly, and the storage electrode formed inside the hole can be enlarged.

FIG. 7 is a diagram showing another layout example. In this example, a transistor channel formed by a word line and an active region or a region of a diffusion layer (this is referred to as an active region 61)
Is arranged obliquely with respect to the word lines 62 and the bit lines 64, so that the portion 66 where the storage electrode is in contact with the substrate can be laid out in the gap between the bit lines 64 while the bit lines 64 are laid out in a straightforward manner. is there.

In the layouts shown in FIGS. 6 and 7, the etching mask of the insulating film for making the storage electrode contact the substrate is used as it is as the storage electrode formation mask. A feature of the present invention is that the mask pattern, the mask process, and the like can be simplified as compared with the case where separate mask patterns and separate mask steps are conventionally required.

Third Embodiment A third embodiment shown in FIG.
An example in the case of forming after the formation of is shown. Even if the bit line 16 is formed later, the wall-shaped storage electrode 18 can be formed without any problem.

Although the embodiment of the present invention has been described with reference to an n-channel type memory cell, it is needless to say that the present invention can be applied to a p-channel type memory cell.

Further, in the embodiment of the present invention, the bent beat line (2
Although an example of an intersection / bit method is shown, it is needless to say that the present invention can be applied to an open bit (one intersection / bit) method.

In addition, it goes without saying that by using the present invention only for forming a capacitor, a capacitor having a larger storage capacitance value can be formed even with the same area.

〔The invention's effect〕

As described above, according to the semiconductor device and the method of manufacturing the same according to the present invention, in a one-transistor and one-capacitor type semiconductor device having a storage electrode, the peripheral portion of the storage electrode region is formed in a thin wall shape concentrically in two or more layers. Since the inner wall and the outer wall of the wall form the storage electrode, there is an effect of forming a storage capacitor having a larger capacitance value in a fine cell area as compared with the conventional structure. Therefore, a memory with a high degree of integration can be formed.

In addition, the number of times the mask pattern is used can be reduced by one at the time of formation of the storage capacitor as compared with the conventional case, so that the process can be shortened.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view of a conventional semiconductor device, and FIGS. 3 (a) to 3 (j) show manufacturing steps of the first embodiment. 4, FIG. 4 is a sectional view showing a second embodiment of the present invention, FIGS. 5 (a) and (b) are diagrams showing a manufacturing method of the second embodiment, respectively, and FIG. 6 is a layout. Diagram showing an example of
FIG. 7 is a view showing another example of the layout, and FIG. 8 is a sectional view showing a third embodiment of the present invention. 14 ... word line, 16 ... bit line 18,65 ... storage electrode, 19 ... capacitor insulating film

Claims (6)

(57) [Claims] In a one-transistor and one-capacitor type semiconductor device having a storage electrode, a peripheral portion of the storage electrode region is formed as a thin wall concentrically in two or more layers, and an inner wall and an outer wall of the wall are formed. A semiconductor device comprising a storage electrode. 2. The capacitor according to claim 1, wherein said insulating film material comprises Si.
_{2. The} semiconductor device according to claim 1, wherein O ₂ , Si ₃ N ₄ , Ta ₂ O ₅ or a composite film thereof is used. 3. The capacitor according to claim 1, wherein said capacitor having said thin-walled storage electrode is incorporated in an LSI mainly for performing a logical operation.
A semiconductor device according to any one of the above items. 4. A semiconductor device having a storage electrode extending over a bit line, wherein the active region is laid out obliquely with respect to both the word line and the bit line, and the surface forming the capacitance of the storage electrode is formed on the substrate surface. A semiconductor device formed in a direction perpendicular to the semiconductor device. 5. A step of forming a word line substantially surrounded by an insulating film, and depositing SiO ₂ and Si ₃ N ₄ on at least a part of a substrate between the word lines or at least a portion of the word line. Using a hole pattern mask extending to the area including a part,
A step of forming a hole pattern by etching in the order of Si ₃ N ₄ and SiO ₂ , and thereafter, applying a conductive thin film, and filling a resist in a hole covered with the conductive thin film, A method of manufacturing a semiconductor device, comprising: a step of etching the conductive thin film while leaving the inner wall surface; and a step of forming a capacitor insulating film and a plate electrode after etching Si ₃ N ₄ . 6. A step of forming the hole pattern is, Si ₃ N ₄ After depositing the SiO ₂ on the time of the subsequent hole pattern formation, the SiO ₂ etching First, the SiO ₂ after the conductive thin film formed 6. The method for manufacturing a semiconductor device according to claim 5, further comprising a step of removing the semiconductor device.