JP2633251B2 - Image memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generates a figure or an image from coordinate data or the like, and restores or restores an image obtained from a camera or the like.
The present invention relates to an image memory element used in a system for displaying on a display device while performing processing such as emphasis and recognition.

2. Description of the Related Art Conventional image memory devices include, for example, Satoru Kobayashi, "for a frame buffer that enables uninterrupted serial output.
Development of 256Kbit Dual Port Memory], Nikkei Electronics, August 12, 1985, No. 375, PP. 211-
Shown at 240.

FIG. 4 is a diagram showing a configuration method of the conventional image memory device. A serial access port is provided independently of a random access port of a general dynamic memory device. Is a memory that can serially output data for one row of the memorial array from another port. In the figure, 1 is a memory cell array for storing image information, 2 is an address buffer for inputting an address divided into row address information and column address information, 3 is a row decoder, 4 is a serial port side for reading one row of data. Amplifier, 5 is a data register for temporarily latching this one row of data, 6 is a selector for selecting one bit from this one row of data, and 7 is a column address of data to be read to the serial port side. Column address register to hold,
9 is a serial output buffer, 10 is a driver for reading and writing one row of data on the random access side.
A sense amplifier 12 is a selector for selecting one bit indicated by a column address from the data of one row, 13 is a random access input / output buffer, 14 is a timing generation circuit, and 15 is an incrementer.

In the conventional image memory device configured as described above, when serially reading out a bit sequence after a specific column address of a certain row in a serial manner, a row address is first input to a row address decoder 3 via an address buffer 2. The row address decoder 3 decodes the row address and outputs a read signal to one row of the memory cell array 1. The read data of one row is latched by the data register 5 via the sense amplifier 4. Next, the column head address similarly input from the address buffer 2 is latched by the column address register 7, and the selector 6 decodes the output signal of the column address register 7 to select one bit of the data register 5, and this 1 bit Data is output via the serial output buffer 9. Subsequently, when the serial clock SC is input, the value of the column address register 7 is added one by one by the incrementer 15, so that a continuous column address of one row of data latched in the data register 5 can be sequentially read. As described above, by providing a circuit for serial reading separately from the circuit for random access, high-speed serial access can be realized completely independently of random access, and used as a frame memory of a display device such as a raster scan type CRT. be able to.

Problems to be Solved by the Invention However, due to the restriction that continuous output data to the display device must be horizontal pixel information, it is necessary to allocate continuous column addresses in the horizontal direction of the screen in the above configuration. However, this has the following problems.

When configuring an image generation / processing system from an image processor and an image memory device, a plurality of (M) image memory devices are connected in parallel, and the image processor can read and write a plurality of pieces of pixel information at a time to speed up processing. It is common to make The unit that can be read and written at once is 1
It is called a word, and in this case, 1 word = M bits. When a binary image is handled, information of M pixels is included in one word. When the image processor proceeds with the processing in such a system, the position of the pixel continuously accessed from the random access port is almost always the pixel adjacent to the pixel position currently being processed. If it happens to be in the left-right direction, the information will be in the same word unless it crosses a word boundary. Therefore, if a one-word cache buffer is provided in the image processor, by accessing it, access to the image memory can be omitted, and the processing can be speeded up. However, when the pixels to be subsequently accessed are vertically or obliquely, they are allocated in a word of a completely different address which is not an adjacent address, and the cache buffer has no effect.

In view of the above, an object of the present invention is to provide an image memory device that enables high-speed image generation and processing in combination with a cache buffer in an image processor.

Means for Solving the Problems The present invention provides an address input buffer for inputting a read / write address of a memory cell array as row address information and column address information in a time-division manner, and decoding the row address information from the address input buffer. A first decoder for reading / writing data between a row decoder for outputting a selection line to one row of memory cells of the memory cell array and a memory cell of the selected one row located on the random access port side. A data selector, a first selector for selecting one bit to access the first data register based on the example address information from the address input buffer, and a data read from the memory cell array located on the serial access port side. A second data register for holding the data of the one row, At the time of setting the initial address of the real output, the column address information from the address input buffer is stored. At the time of the serial read operation, the column address counter is incremented by N (> = 2) and the column address information output by the column address counter is used. An image memory device including a second selector for selecting one bit from a second data register.

According to the present invention, the random access port can access the address in one row of the memory cell array at a high speed from the random access port, and can continuously output pixel information every N bits from the serial port. M image memory elements are connected in parallel, and two-dimensional image information of a total (NxM) pixels of N pixels in the vertical direction and M pixels in the horizontal direction is stored in a memory block of N consecutive words, and a plurality of words are stored in the image processor. , It is possible to substantially speed up memory access by utilizing high-speed data transfer between the image memory element and the cache buffer.

Embodiment FIG. 1 is a block diagram showing a configuration method of an image memory device according to an embodiment of the present invention. In FIG. 1, 8 is a constant adder, 11 is a data register for latching one row of data at the random access port side,
7, 9, 10, 12 to 14 are the same as those in FIG.

The operation of the image memory device of the present embodiment configured as described above will be described below.

First, when reading data from the random access port, the row address input from the address buffer 2 is input to the row address decoder 3, which decodes the row address and outputs a read signal to one row of the memory cell array 1. Output. The read data of one row is latched by the data register 11 via the driver / sense amplifier 10. Next, the selector 12 decodes the column address input from the address buffer 2 to select one bit of the data register 11, and this one bit data is output via the random access input / output buffer 9. If the address to be read continuously is the same row address, the data is already in the data register 11 and can be read only by giving the column address information. It becomes possible. As described above, the random access reading has been described, but the writing can be performed at a high speed in one row only by changing the transfer timing between the memory cell array 1 and the data register 11.

On the other hand, when reading serially, input the row address,
The operation until the one-row data of the memory cell array 1 is latched in the data register 5 and the column head address is latched in the column address register 7 is exactly the same as the conventional example of FIG. The selector 6 also decodes the output signal of the column address register 7 and selects one bit of the data register 5 as in FIG. 4, and this 1-bit data is output via the serial output buffer 9. Subsequently, when the serial clock SC is input, the value of the column address register 7 is added N by N by the constant adder 8, and the column address of every Nth row of data for one row latched in the data register 5 can be sequentially read. .

Next, an example of the configuration of an image memory device using a plurality (M) of the image memory elements shown in FIG.
A configuration example of an image processing apparatus in which an image processor is combined with an image processor will be described with reference to FIG. In FIG. 3, 31 is an image processor, 32 is an image memory, 33 is a cache buffer, and 34 is image data corresponding to this cache buffer.

In FIG. 2 (a), one word of the image memory stores information on M (= 8) pixels in the horizontal direction, and as shown in FIG. Pixel blocks arranged in N lines in the vertical direction are assigned to word addresses, and further, pixel blocks arranged in the horizontal direction are assigned to continuous memory blocks using the N words as a unit of memory block. FIG. 4C collectively shows an arrangement relationship between a memory address and a pixel position to be stored in a memory cell array in the image memory element. With the above-described configuration, data of a two-dimensional pixel block can be read and written by a transfer operation of a plurality of words that does not cross the boundary of a memory block.

In FIG. 3, the image processor 31 has image data 34 of K (> = 2, an integral multiple of N) words in the image memory 32.
, A K word cache buffer 33 is incorporated. Here, the K word is called one sector. For example, to draw a straight line vector or an arc in a graphic / image generation application, calculate the pixel position to be drawn and replace the corresponding pixel with data of a predetermined color (black or white).
Alternatively, a process of performing a logical operation (raster operation) on the predetermined color data and the color data originally in the image memory 32 and writing the result to the image memory 32 again is performed. In this case, to start drawing, first, K words in the cache buffer 33 are cleared. Next, pixel information to be drawn is included in a word address in which sector address in which sector, and the position in that word is calculated. Therefore, the cache buffer 33 is temporarily considered to be the data of the corresponding sector address, and the position in the word of the above-mentioned word address in the sector of the cache buffer 33 is replaced with predetermined color data. Further, a position to be drawn next is calculated, and if the sector address including the pixel coincides with the previous sector address, the corresponding word address in the sector and the position in the word of the cache buffer 33 are continuously specified. Perform processing to replace with color data. If the address does not match the previous sector address, the image processor 31 reads the image data 34 of the K word of the previous sector address in the image memory 32 once for each word, and stores it in the cache buffer.
A logical operation (raster operation) with the corresponding word data in 33 is performed, and the data is written again at the same address position in the image memory 32 (read-modified-write). Thereafter, the cache buffer 33 is cleared to zero, the cache buffer 33 considers it as a K word of a corresponding new sector address, and the above processing is continued.

Also, in the image processing application, when the image restoration, enhancement, and recognition processing is performed on the original image stored in the image memory 32, the same processing as described in the above-described graphic / image generation application is performed for pixel data access. Perform address calculation. However, in this application, it is necessary to refer to the original image, and the transfer timing between the cache buffer 33 and the corresponding image data 34 is different. That is, first, the image data 34 of the corresponding sector address is loaded into the cache buffer 33, and as long as the necessary pixel data exists in the cache buffer 33, the word data is continuously referred to. Load new sector data. In the image memory device of the present invention, access within one row of the memory cell array can be performed at a higher speed than access beyond that. Therefore, if the memory block (consecutive N words) is set so as not to extend over this one line, K words (one sector) of the cache buffer 33 and the corresponding image data 34 in the image memory 32 can be transferred continuously. Can be performed at high speed.

In the image generation / processing, pixel information required continuously in the process has a stochastic property that it is adjacent as described above. In the above example, the image processor 31
By providing a cache buffer 33 of K words in the memory, there is a high probability that reading and writing to the cache buffer 33 is sufficient without accessing the image memory 32 for each processing of one pixel. Time can be reduced as much as possible.

As described above, according to the present embodiment, the function of continuously outputting the image data of the column address of every image memory element N from the serial output terminal is provided, and the image memory device is further provided by using M image memory elements. By constructing and allocating two-dimensional pixel information within consecutive N words and providing a cache buffer of K words inside the image processor, the speed of image generation and processing can be remarkably increased.

Although a binary image has been described in the above embodiment, in the case of multi-valued (n bits / pixel), M / M
It goes without saying that the same effect can be obtained by assigning n pixels (> = 2). Further, if N is determined to be expressed as a power of 2, hardware including a constant adder can be simplified at the time of system configuration.

As described above, according to the present invention, the image memory element is provided with the function of continuously outputting the image data of the Nth column address in the data of one row of the memory cell array from the serial output terminal. Thus, a very high-speed image generation / processing device can be configured, and its practical effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an image memory device according to one embodiment of the present invention, FIG. 2 is a memory configuration diagram showing the structure of an image memory device using the image memory device of the embodiment,
FIG. 3 is a block diagram of an image processing device using the image memory device of the embodiment, and FIG. 4 is a block diagram of a conventional image memory device. 1 ... memory cell array, 3 ... row decoder, 5,11 ...
Data register, 6, 12 ... selector, 7 ... column address register, 8 ... constant adder.

Claims (1)

(57) [Claims] An address input buffer for inputting read / write addresses of a memory cell array consisting of M (M> = 2) as row address information and column address information in a time-division manner, and row address information from the address input buffer. And a data read / write transfer between a row decoder that decodes data and outputs a selection line to one row of memory cells of each memory cell array and the selected one row of memory cells located on the random access port side. The first to do
A data selector, a first selector for selecting one bit to access the first data register based on column address information from the address input buffer, and a data read from each memory cell array located on the serial access port side. A second data register for holding the data of one row, and column address information from the address input buffer when the initial address of the serial output is set, and increments by N (> = 2) at the time of the serial read operation. A column address counter and a second selector for selecting one bit from the second data register according to the column address information output from the example address counter. The image is stored at the same address in each of the M memory cell arrays. Stores information on horizontal M pixels and includes the address M pixels to be stored in N columns of addresses following the N columns of addresses, and to store information of N vertical lines including the horizontal M pixels in the following N columns of addresses. An image memory element, wherein the pixel block information arranged in a horizontal direction of a two-dimensional image is sequentially stored by setting the N pixel lines as a pixel block.