JP2626300B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a self-aligned emitter-base separation.

[0002]

2. Description of the Related Art In recent years, the speed of semiconductor integrated circuits has been increased,
In particular, for a bipolar semiconductor integrated circuit, a self-aligned device has been developed and put into practical use. Here, as an example,
SST process (Super Self-aligned process technology)
Need process technology) will be briefly described. The description of the collector region, the embedding process, and the epitaxial process is omitted for convenience of description, and only the method of forming the base / emitter region will be described with reference to FIGS.

[0003] First, as shown in FIG.
01 (assuming that a collector region, a buried layer, etc., not shown) are formed. After the surface is thinly oxidized, a silicon nitride film 203 is grown to a thickness of 200 nm by a vapor phase epitaxy method. By implanting boron, it is converted into a boron-doped polysilicon film 204a. Next, the boron-doped polysilicon film 204a on the base and emitter formation regions is selectively removed by etching.

Next, as shown in FIG. 14, the exposed portion of the boron-doped polysilicon film 204a is oxidized to a thickness of 200
A silicon oxide film 216 having a thickness of about nm is formed.

Then, as shown in FIG. 15, the exposed portion of the silicon nitride film 203 is removed by etching using hot phosphoric acid, and further, an undercut is made to a region covered with the boron-doped polysilicon film 204a. Next, after a thin silicon oxide film (not shown) covering the surface of the silicon substrate 201 is removed by etching, the second non-doped polysilicon film 2 is buried so as to fill the undercut region.
Grow 08.

Next, as shown in FIG. 16, boron is diffused from the boron-doped polysilicon film 204a to the second non-doped polysilicon film 208 embedded in the undercut region by heat treatment, and furthermore, the boron diffusion is performed. Boron is also diffused into the silicon substrate 201 immediately below the region,
A graft base region 210 is formed. After this, KOH
Using an aqueous solution or hydrazine, only the non-doped polysilicon film 208 is selectively etched away.

Thereafter, as shown in FIG. 17, the exposed portion of the boron-doped polysilicon film 204a and the silicon substrate 20 are removed.
The exposed portion 1 is oxidized to form a base-emitter separation film 216a of a thin silicon oxide film having a thickness of about 70 nm. Next, boron is ion-implanted through the thin silicon oxide film (216a) to form a base region 20 in the silicon substrate 201.
7 is formed.

After that, as shown in FIG. 18, an emitter contact is opened by using an anisotropic ion etching apparatus, and after growing a third polysilicon, arsenic is ion-implanted at a high concentration to thereby perform arsenic doping. Polysilicon film 2
Convert to 17. Next, arsenic is diffused from the arsenic-doped polysilicon film 217 into the base region 207 by heat treatment to form an emitter region 211.

As described above, the emitter-base separation is formed in a self-aligned manner.

[0010]

The above-described conventional SST
The problem in manufacturing the self-aligned bipolar transistor by the process is as follows.
Second, the processing accuracy of the undercut portion is poor, and secondly, is potassium used to degrade the performance of the transistor element used for selective etching of the second non-doped polysilicon film 208 and the boron-doped polysilicon film 204a? The use of hydrazine, which is prohibited in the United States as a carcinogen, must be used.

[0013] Further, as a problem in characteristics, first, there is a variation in resistance value or an increase in base lead-out resistance due to oxidation of the boron-doped polysilicon film 204a. The arsenic concentration due to the ion implantation in the emitter decreases as the opening becomes narrower due to the groove shape, and the DC current amplification factor hFE varies. Third, the metal electrode material such as Al becomes grooved. The fourth problem is that the emitter resistance increases because it is difficult to adhere to the emitter portion.
04a) Since a thin silicon oxide film is formed directly above the emitter electrode (218) via 216, the base-
Points such as a large capacitance between the emitters are listed.

An object of the present invention is to provide an SST
It is an object of the present invention to provide a method of manufacturing a semiconductor device which does not impair the excellent characteristics of a self-aligned bipolar transistor and the like and in which the above disadvantages are greatly improved.

[0013]

According to a method of manufacturing a semiconductor device of the present invention, a silicon oxide film, a first silicon nitride film, and a first polysilicon film are sequentially formed on one main surface of a first conductivity type semiconductor substrate. Forming, selectively adding first conductivity type and second conductivity type impurities to the first polysilicon film, forming a second silicon nitride film, forming a first pattern in the first pattern. The first conductivity type impurity region and the second conductivity type impurity region;
Etching the first polysilicon film and the first and second silicon nitride films so as to include a conductive impurity region, and removing the first polysilicon film and the first and second silicon nitride films through the exposed region of the silicon oxide film to the first conductive semiconductor substrate. Forming a first second conductivity type impurity region, etching and removing at least a portion of the exposed portion of the silicon oxide film, growing a second polysilicon film, and forming the second polysilicon film Anisotropically etching at least a portion of the first polysilicon film to leave it on the side wall of the first polysilicon film; and removing a first conductivity type impurity and a second conductivity type impurity from the first polysilicon film to a second polysilicon film. Diffusion into the semiconductor substrate through the remaining part of the film,
Simultaneously forming a first conductivity type impurity region in the second second conductivity type impurity region and the first second conductivity type impurity region.

[0014]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIGS. 1 to 6 are sectional views showing a first embodiment of the present invention in the order of steps for explaining the first embodiment. The description of the collector region, the embedding process, and the epitaxial process is omitted for convenience of description, and only the method of forming the base and emitter regions will be described.

First, as shown in FIG.
A silicon oxide film 102 having a thickness of 200 nm is formed on the surface of the semiconductor device 01 by thermal oxidation, and a silicon oxide film 102 having a thickness of 300
A first silicon nitride film 103 is grown, and a first polysilicon film 104 having a thickness of 500 nm is formed by a vapor growth method.
After the growth, boron and arsenic of a high concentration are selectively implanted by ion implantation to be converted into an arsenic-doped polysilicon film 104a and a boron-doped polysilicon film 104b.
Next, a second silicon nitride film 105 having a thickness of 500 nm is formed by a vapor deposition method.

Next, as shown in FIG. 2, the second silicon nitride film 10 is formed using the first photoresist film 106 as a mask.
5 and the arsenic-doped polysilicon film 104a, the boron-doped polysilicon film 104b, and the first silicon nitride film 103 are sequentially removed by etching. At this time, a pattern is designed so that the arsenic-doped polysilicon film 104a and the boron-doped polysilicon film 104b are etched by substantially equal amounts in a region to be etched using the first photoresist film 106 as a mask. Subsequently, low-concentration boron is ion-implanted through the silicon oxide film 102 to form a base region 107.

Next, as shown in FIG. 3, after the exposed silicon oxide film 102 is removed by etching, a second non-doped polysilicon film 108 is grown to a thickness of 500 nm by a vapor growth method.

Next, as shown in FIG.
The second non-doped polysilicon film 108 is etched by anisotropic etching until the thickness becomes about 0 nm.

Next, as shown in FIG. 5, the non-doped polysilicon film 108 in the flat portion is oxidized until the entire silicon oxide film 109 is formed.

Next, as shown in FIG. 6, arsenic from the arsenic-doped polysilicon film 104a and boron from the boron-doped polysilicon film 104b are simultaneously diffused into the remaining portion of the non-doped polysilicon film 108 by thermal diffusion. Further, boron and arsenic are pushed into the silicon substrate 101 to form a graft base region 110 and an emitter region 111. Thereafter, the base electrode outlet and the emitter electrode outlet are respectively connected to the boron-doped polysilicon film 1.
The aluminum electrodes 112a and 112b are formed on the silicon oxide film 104b and the arsenic-doped polysilicon film 104a.

As described above, according to the present embodiment, the separation between the base and the emitter is formed in a self-aligned manner, and the excellent feature of the SST process that can be miniaturized is maintained.
The manufacturing problems and characteristics problems described above can be solved.

In other words, the poor precision of the undercut of the silicon nitride film, which is the first problem in manufacturing, is improved by replacing the thickness of the second polysilicon film with the thickness of the second polysilicon film. Is unnecessary because the supply of impurities to the second non-doped polysilicon film is performed not from the bottom surface of the first doped polysilicon film but from the side surface thereof.
Variations in resistance value, which is a first problem in characteristics,
The second problem, the dispersion of hFE, is stabilized by supplying arsenic stably from the first doped polysilicon film having a high concentration of arsenic. The third problem, the increase in the emitter resistance, is also solved by using the first doped polysilicon film of arsenic at a high concentration. The structure can be greatly improved because no emitter electrode is formed.

Next, a second embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. FIGS. 7 and 8 are the same as FIGS. 1 and 2, respectively, and are the same as the first embodiment up to the formation of the base region 107.

After the formation of the base region 107, as shown in FIG. 9, a second photoresist film 113 is applied and then a silica film is applied, and a heat treatment at about 150 ° C. is performed to form a silicon oxide film 114.

Next, as shown in FIG. 10, the silicon oxide film 114 in the flat portion is removed by anisotropic etching so that the silicon oxide film 114 accumulated in the recess of the second photoresist film 113 is left. Using the silicon oxide film 114 remaining in the recess of the second photoresist film 113 as a mask, the second photoresist film 113 is removed by anisotropic etching.

Next, as shown in FIG. 11, a part of the silicon oxide film 102 is etched and removed simultaneously with the remaining second photoresist film 113 as a mask, and the second photoresist is also removed. After removing the film 113, a second non-doped polysilicon film 108 is grown to a thickness of 500 nm by a vapor growth method.

Next, as shown in FIG. 12, after the second non-doped polysilicon film 108 in the flat portion is entirely removed by anisotropic etching, the silicon oxide film 105 is formed to a thickness of 500 nm by a vapor growth method. After the growth and heat treatment, the graft base region 110 and the emitter region 11 are formed.
By forming No. 1, a base and an emitter of a self-aligned bipolar transistor having substantially the same structure and performance as those of the first embodiment can be obtained.

This embodiment has an advantage that the step of oxidizing the second non-doped polysilicon film 108 can be omitted.

[0030]

As described above, according to the present invention, since the undercut of the silicon nitride film is not used, high-precision processing is possible, and the step of selectively removing the non-doped polysilicon film with respect to the doped polysilicon film. And the use of harmful chemicals, which is a problem in the prior art, is not required, and there is no step of oxidizing the first doped polysilicon film. Since the emitter region is formed by diffusion from the silicon film, the DC current amplification factor is stabilized. Since the emitter electrode and the base electrode are not arranged close to each other with an insulating film interposed therebetween, the parasitic capacitance between the emitter and the base is reduced. Becomes smaller.
That is, there is an effect that a high-performance self-aligned bipolar transistor can be realized safely and reliably.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view used for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view used for explaining the first embodiment of the present invention.

FIG. 3 is a cross-sectional view used for explaining the first embodiment of the present invention.

FIG. 4 is a cross-sectional view used for explaining the first embodiment of the present invention.

FIG. 5 is a sectional view used for describing the first embodiment of the present invention.

FIG. 6 is a sectional view used for explaining the first embodiment of the present invention.

FIG. 7 is a cross-sectional view used for describing a second embodiment of the present invention.

FIG. 8 is a cross-sectional view used for describing a second embodiment of the present invention.

FIG. 9 is a sectional view used for describing a second embodiment of the present invention.

FIG. 10 is a cross-sectional view used for describing a second embodiment of the present invention.

FIG. 11 is a sectional view used for explaining a second embodiment of the present invention.

FIG. 12 is a cross-sectional view used for describing a second embodiment of the present invention.

FIG. 13 is a sectional view used for explanation of the related art.

FIG. 14 is a cross-sectional view used for explanation of the related art.

FIG. 15 is a cross-sectional view used for explanation of the related art.

FIG. 16 is a cross-sectional view used for explanation of the related art.

FIG. 17 is a cross-sectional view used for explanation of the related art.

FIG. 18 is a cross-sectional view used for explanation of the related art.

[Explanation of symbols]

 101, 201 silicon substrate 102 silicon oxide film 103, 203 silicon nitride film 104a, 204a boron-doped polysilicon film 104b arsenic-doped polysilicon film 105 silicon nitride film 106 first photoresist film 107, 207 base region 108, 208 Non-doped polysilicon film 109 Silicon oxide film 110 Graft base region 111 Emitter region 112a Aluminum electrode (emitter electrode) 112b Aluminum electrode (base electrode) 113 Second photoresist film 114 Silicon oxide film 115 Silicon oxide film 216, 216a Silicon oxide film 217 Arsenic doped polysilicon film 218a Aluminum electrode (emitter electrode) 218b Aluminum electrode (boehm electrode)

Claims (1)

(57) [Claims] A step of sequentially forming a silicon oxide film, a first silicon nitride film, and a first polysilicon film on one main surface of a first conductivity type semiconductor substrate; Adding a first conductivity type impurity and a second conductivity type impurity, forming a second silicon nitride film, and forming the first conductivity type impurity region and the second conductivity type impurity in a first pattern. Etching the first polysilicon film and the first and second silicon nitride films so as to include the first region and the first conductive type semiconductor substrate through the exposed region of the silicon oxide film. Forming a second conductivity type impurity region, etching and removing at least a part of the exposed portion of the silicon oxide film, growing a second polysilicon film, and forming at least one of the second polysilicon film; Department is anisotropic Leaving the first polysilicon film on the side wall of the first polysilicon film, and removing a first conductivity type impurity and a second conductivity type impurity from the first polysilicon film, respectively.
Diffusing into the semiconductor substrate through the remaining portion of the polysilicon film, and simultaneously forming the first conductivity type impurity region in the second second conductivity type impurity region and the first second conductivity type impurity region. A method for manufacturing a semiconductor device, comprising: