JP2622012B2 - Shift circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift circuit, and more particularly, to a shift circuit in a floating-point data arithmetic unit, which shift-controls a mantissa of non-normalized input data.

2. Description of the Related Art In floating-point addition and subtraction, when floating-point data that has not been normalized is input, first, processing for normalizing non-normalized data is performed in order to increase calculation accuracy.

A normalization amount for normalizing the exponent part and the mantissa part is calculated from the value of the unnormalized mantissa part. The exponent is normalized by adding or subtracting a value based on the normalized amount to or from the value of the exponent, and the mantissa is normalized by shifting the bidirectional shifter using the normalized amount as a shift amount. .

When the normalized data is prepared, the exponents are aligned next, so that the normalized exponents are compared with each other, and the mantissa of the data is not shifted based on the data having the largest value of the exponent. The mantissa part of the other data is shifted to the right by the difference between the exponent part having the largest value and its own exponent part. Then, addition and subtraction between the digit-aligned mantissa parts may be performed.

As a conventional example, a floating point adder having two operands as inputs will be specifically described with reference to FIG.

The first operand is a normalized floating point data composed of a sign part SA, an exponent part EA, and a mantissa part MA. Is non-normalized floating-point data.

The second operand is a binary number, and is expressed as (-1) ^SB0 × (GB0 + MB0) × 2 ^EB0 . In particular, the mantissa part MB0 and the mantissa part overflow protection unit GB0 are expressed as follows.

MB0 = M0 × 2 ^-1 + M1 × 2 ^-2 + ... + Mm × 2 ^m-1 GB0 = Gn × 2 ^n-1 + ... + G2 × 2 ¹ + G1 × 2 ^{0 In} this case, it is called non-normalized floating point data. Is GB0 = 0 and at least the most significant bit M0 of MB0 is 0
(Hereinafter referred to as left-shifted data), an overflow occurs from MB0 due to the result of addition / subtraction, etc., and GB0 ≠ 0 (hereinafter referred to as overflow data).

The normalized floating-point data is a value such that there is no overflow from the mantissa (GB = 0) and the maximum significant bit M0 is 1.

The normalization amount calculation circuit 1 receives the mantissa part MB0 and the mantissa part overflow protector GB0 as inputs and determines whether the mantissa part has overflowed. If "mant overflow occurs, the mantissa part overflows to the right. The shift is performed by shifting the mantissa to the left by the value of the leading zero counter if there is no overflow, "a normalized shift amount NSB0 is output. The normalized shift amount NSB0 is expressed as a value for the shift by which the mantissa is to be shifted, as a negative value for left shift and a positive value for right shift. Therefore, if the data has a mantissa part overflow, it will be a positive number, and if it has left shift data, it will be a negative number.

The mantissa part MB0 is normalized by the bidirectional shifter 8 based on the normalized shift amount NSB0. The normalized mantissa
Call it MB. The exponent part EB0 is normalized by the exponent part normalization circuit 2 by adding the normalized shift amount NSB0. The normalized exponent is called EB.

The exponent part comparison circuit 31 compares the two exponent parts EA and EB with each other and compares their magnitudes. When EA = EB, CI (S0, T0) = (0, 0) When EA> EB, CI (S0 , T0) = (0, 1) When EA <EB, the comparison information CI (S0, T0) expressed as CI (S0, T0) = (1, 0) is output as the comparison result.

Also, the exponent part subtraction circuit 32 subtracts EA from EB, and calculates the difference
The SBBA is output, and the exponent part subtraction circuit 33 subtracts EB from EA, and outputs the difference SBAB.

Then, the comparison information CI derived from the exponent part comparison circuit 31
Based on (S0, T0), the selection circuit 34, when T0 = 0,
(When EA ≦ EB), the output result SBBA of the exponent part subtraction circuit 32
, When S0 = 0 (when EA ≧ EB), zero is selected. Similarly, when S0 = 0 (when EA ≧ EB), the selection circuit 35 selects the output result SBBA of the exponent part subtraction circuit 33, and when T0 = 0 (when EA ≦ EB), selects zero. .

The outputs of these selection circuits are the shift amounts SFA and SFB of the mantissa parts MA and MB of the first and second operands, respectively. Similarly to the normalization amount, the digit shift amount is expressed by a negative number for left shift and a positive number for right shift.

The exponent part comparing circuit 31, the exponent part subtracting circuits 32 and 33, and the selecting circuits 34 and 35 constitute the shift amount calculating part 3.

When S0 = 0 (when EA ≧ EB), the selection circuit 4
When T0 = 0 (when EA ≦ EB), the exponent part EA of the operand is selected as the exponent part EB of the second operand, and output as the addition result exponent part EC.

The rightward shifter 5 is the first shifter based on the digit shift amount SFA.
The mantissa MA of the operand is shifted, and the rightward shifter 9 shifts the mantissa M of the second operand based on the digit shift amount SFB.
Shift B.

The two mantissa parts MAS and MBS that have been digit-aligned are added by a mantissa addition circuit 7 and output as an addition result mantissa MC.

As described above, the mantissa part of the non-normalized operand in the floating-point arithmetic unit having non-normalized data as an input is subjected to the normalization shift, and further, the digit shift is performed. Must be treated. That is, two shifters are required for one mantissa. In general, a shifter circuit is composed of select gates corresponding to the bit width of data to be shifted, so that a shifter for a mantissa part having a very large bit width requires many select gates. Therefore, the requirement of two stages of shifters in series causes a problem of an increase in the amount of hardware and an operation time.

As described above, the mantissa part of the denormalized floating-point data is subjected to the normalization shift and the alignment shift separately, but if these two shift processes are collectively performed by one process, The above-mentioned problem is solved. For this purpose, it is necessary to consider the normalization shift and the digit alignment shift in the same manner, and to generate a shift amount that requires only one shift process.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of such problems of the prior art, and an object of the present invention is to make it possible to shift the mantissa of non-normalized data only once. Another object of the present invention is to provide a shift circuit that reduces the amount of hardware and the operation time.

According to the present invention, an operation of normalized first floating-point data and non-normalized second floating-point data is performed after normalizing the second floating-point data. A floating-point arithmetic unit configured to shift a mantissa of the second floating-point data, wherein the shift circuit calculates a normalization amount according to the mantissa of the second floating-point data; Means for normalizing the exponent part of the second floating-point data in accordance with the normalization amount, the normalized exponent part, the exponent part of the first floating-point data, and the normalization Means for calculating a shift amount of the mantissa part of the second floating-point data in accordance with the amount, and means for shifting the mantissa part in accordance with the shift amount. Send to Thus, a shift circuit characterized by performing the above operation is obtained.

According to the present invention, the operation of the normalized first floating-point data and the normalized second floating-point data is performed after the second floating-point data is normalized. A floating-point arithmetic unit for shifting a mantissa part of the second floating-point data, wherein the shift circuit calculates a normalization amount according to a mantissa part of the second floating-point data; Means for normalizing the exponent part of the second floating-point data according to the normalization amount; and the second exponent part of the first and second floating-point data and the second exponent part according to the normalization amount. Means for calculating the shift amount of the mantissa of the floating-point data, and means for shifting the mantissa in accordance with the shift amount;
The shift circuit is characterized in that the shifted data is sent to the computing unit.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings. First
FIG. 3 is a circuit diagram of an embodiment of the present invention. The embodiment is an example applied to a floating-point adder that receives two operands as in the conventional example.
A, normalized floating-point data composed of an exponent part EA and a mantissa part MA. Use normalized floating point data.

The same parts as those in FIG. 3 are denoted by the same reference numerals, and calculation of the normalized amount for the denormalized data, generation of processing comparison information for normalizing the denormalized data exponent part, calculation of the addition result exponent part, and the addition result mantissa part , And the process of digit-aligning the mantissa of the first operand, which is the normalized data, is exactly the same as in the conventional example of FIG.

The process until the mantissa of the second operand, which is the denormalized data, is normalized and aligned will be described in detail below.

The shift amount for normalization is obtained from the normalization amount calculation circuit 1.
It has been demanded.

Normalized shift amount = NSB0 The shift amount for digit alignment is obtained by the exponent part subtraction circuit 33.

Digit shift = SBAB = EA-EB (Effective when ≥ 0) These shifts are negative numbers for left shift,
A right shift is represented by a positive number.

By the way, when the exponents are compared in magnitude, if their own is larger or equal, since the exponent of their own is used as a reference, there is no need to shift the significand, and only the normalized shift. Just think. Conversely, when the exponent part of the other operand is used as a reference, both the normalized shift and the alignment shift are required, and the result ADS of the shift amount adding circuit 36 for adding the normalized shift amount and the alignment shift amount is used.
Becomes effective.

Summarizing the above, based on the comparison information CI (S0, T0), the selection circuit 35 sets the normalized shift amount NSB0 when T0 = 0 (when EA ≦ EB) and sets the normalized shift amount NSB0 when S0 = 0 (EA ≧ EB ), The result ADS of the shift amount adding circuit 36 is selected, and becomes the shift amount SFB0 for the mantissa part of the second operand.

When T0 = S0 = 0 (when EA = EB), the normalized shift amount NSB0 and the addition result ADS are simultaneously selected. These are expressed as ADS = NSB0 + (EA−EB) = NSB0. There is no problem because they are equivalent.

Based on the shift amount SFB0, the mantissa part MB0 and the mantissa part overflow protector GB0 are simultaneously subjected to normalization and digit matching by the bidirectional shifter 6.

FIG. 2 is a circuit diagram of another embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. This embodiment is also applied to a floating-point adder having two operands as in the embodiment of FIG. 1. The first operand is composed of a sign SA, an exponent EA, and a mantissa MA. Normalized floating-point data, second operand is sign part SB
0, exponent part EB0, mantissa part MB0, mantissa part overflow protection part GB0
And denormalized floating-point data.

Calculation of the normalized amount for the denormalized data, generation of processing comparison information for normalizing the denormalized data exponent part, calculation of the addition result exponent part, calculation of the addition result mantissa part, and mantissa part of the first operand which is the normalized data The digit alignment process is exactly the same as in the conventional example.

The process until the mantissa of the second operand, which is the denormalized data, is normalized and aligned will be described in detail below. The shift amount for normalization is obtained by the normalization amount calculation circuit 1.

Normalized shift amount = NSB0 The shift amount for digit alignment is the difference between the normalized exponent parts. For the second operand, the digit shift amount = SBAB = EA-EB (≥ 0) is there.

Incidentally, the exponent part EB is a value after normalization, and is originally the sum of the non-normalized exponent part and the normalized shift amount.

EB = EB0 + NSB0 These shift amounts are the same as in the conventional example.
A right shift is represented by an integer.

By the way, if the exponents are larger or equal when comparing the exponents, since the exponent of the own is used as a reference, there is no need to shift the mantissa by a digit. Just think. Conversely, if the exponent of the other operand is the reference, both a normalized shift and an alignment shift are required. In this case, the normalized shift amount and the digit shift amount may be added. That is, NSB0 + SBAB = NSB0 + EA-EB. Further, since EB = EB0 + NSB0, NSB0 + SBAB = NSB0 + EA- (EB0 + NSB0) = EA-EB0 (= SBAB0), which is the shift amount when normalization and digit matching are considered simultaneously.

This is the output SBAB0 of the exponent part subtraction circuit 33 for subtracting the denormalized data exponent part EB of the second operand from the normalized data exponent part EA of the first operand.

Summarizing the above, based on the comparison information CI (S0, T0), the selection circuit 35 sets the normalized shift amount NSB0 when T0 = 0 and EA ≦ EB, and when S0 = 0 (EA ≧ EB At this time, the result SBAB0 of the exponent part subtraction circuit 33 is selected and set as the shift amount SFB0 for the second operand mantissa.

When T0 = S0 = 0 (when EA = EB), the normalized shift amount NS
Although B0 and the subtraction result SBAB0 are selected at the same time, they are expressed as SBAB0 = EA-EB0 = EB-EB0 = (EB0 + NSB0) -EB0 = NSB0, so that there is no problem.

Based on the shift amount SFB0, the mantissa part MB0 and the mantissa part overflow protector GB0 are simultaneously subjected to normalization and digit matching by the bidirectional shifter 6.

Effects of the Invention As described above, according to the present invention, the normalization shift and the alignment shift that must be performed on the mantissa part of the denormalized floating-point data can be performed by one shift process. Providing a shift amount calculating means for calculating a shift amount capable of performing two shifts at a time requires only one shifter for the mantissa, thereby reducing the operation time and reducing the amount of hardware. There is.

[Brief description of the drawings]

1 and 2 are circuit diagrams showing an embodiment of the present invention, respectively.
FIG. 3 is a circuit diagram of a floating point arithmetic unit showing the prior art. Description of Signs of Main Parts 1 Normalization amount calculation circuit 2 Exponent part normalization circuit 3 Shift amount calculation unit 6 Bidirectional shifter 33 Exponent part operation circuit 35 Selector 36 Shift Quantity addition circuit

Claims (2)

(57) [Claims] 1. A floating-point apparatus which performs an operation on normalized first floating-point data and non-normalized second floating-point data after normalizing the second floating-point data. In the decimal point arithmetic unit, a shift circuit for shifting a mantissa part of the second floating-point data, comprising: means for calculating a normalized amount according to a mantissa part of the second floating-point data; Means for normalizing the exponent part of the floating-point data according to the normalization amount, the normalized exponent part, the exponent part of the first floating-point data, and the normalization amount. Means for calculating the shift amount of the mantissa part of the second floating-point data, and means for shifting the mantissa part according to the shift amount, so that the shifted data is sent to the arithmetic unit. Made Shift circuit, wherein the door. 2. The floating-point apparatus according to claim 1, wherein the operation of the normalized first floating-point data and the non-normalized second floating-point data is performed after normalizing the second floating-point data. In the decimal point arithmetic unit, a shift circuit for shifting a mantissa part of the second floating-point data, comprising: means for calculating a normalized amount according to a mantissa part of the second floating-point data; Means for normalizing the exponent part of the floating-point data according to the normalization amount, and the second floating-point part according to each exponent part of the first and second floating-point data and the normalization amount. Means for calculating a shift amount of the mantissa of the data, and means for shifting the mantissa in accordance with the shift amount, wherein the shifted data is sent to the arithmetic unit. shift Road.