JP2619075B2 - Video signal storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal storage device for writing and reading a luminance signal and a color difference signal having a smaller number of pixels than the luminance signal to a memory.

[Related Art] The following method has been proposed as a method of storing a color video signal in a memory.

It is converted into a digital signal in the state of the color video signal and written into the memory.

The color video signal is separated into a luminance signal Y and a carrier chrominance signal C, converted into digital signals by two systems, and written into a memory.

The color video signal is separated into a luminance signal Y and a carrier chrominance signal C. Further, the red chrominance signal RY and the blue chrominance signal BY are demodulated from the carrier chrominance signal C, converted into digital signals by three systems, and stored in a memory. Write to.

The color video signal is separated into a luminance signal Y and a carrier chrominance signal C, a red difference signal RY and a blue difference signal BY are demodulated from the carrier chrominance signal C, and these signals are matrixed to form red and green. , Blue primary color signals R, G, and B are converted into digital signals by three systems and written into the memory.

The method of (1) can omit a device for componentization as in the method of (1). However, the sampling clock must be set high because the frequency component increases. Therefore, since the memory capacity is large, it is not often used.

Is used in a VTR or the like, and the carrier color signal C
Although the memory capacity is reduced by a method of performing digital processing by converting a low frequency band, it is not suitable for performing special reproduction processing such as image size compression.

 Is the most commonly used method.

Is used in an image input device of a personal computer. In order to match the screen configuration (primary color signals R, G, B) of the personal computer, the color video signal is often input-processed with the primary color signals R, G, B.

By the way, in the case of the method, since the frequency components of the color difference signals RY and BY are lower than the luminance signal Y in a normal system, the frequency of the sampling clock of the color difference signals RY and BY is Is set lower than that of the luminance signal Y, and the capacity of the memory for writing the color difference signals RY and BY is reduced.

For example, if a 256 × 256 dot configuration (resolution) is adopted for the luminance signal Y, a 64 × 64 dot configuration or the vertical resolution is the luminance for the color difference signals RY and BY. To make the same as the signal Y, a 64 × 256 dot configuration is adopted.

When the horizontal direction of the screen is 256 dots, the vertical direction is 240 dots due to the number of effective lines in the NTSC signal.
It is common to take dots.

Therefore, the above-mentioned 256 × 256 dot configuration, 64 × 64 dot configuration, and 64 × 256 dot configuration are actually 256 × 240 dot configuration, 64 × 60 dot configuration, 64 ×
It has a 240 dot configuration.

Further, regarding the gradation (the direction of depth), the luminance signal Y
Is 6 bits, the color difference signals RY and BY often have 5 bits.

FIG. 6 shows that the luminance signal Y is 5 × 256 × 240 dots.
This is an example of a storage device when 64 bits × 240 dots and 4 bits are used for bits and color difference signals RY and BY.

In the figure, reference numerals 21 to 23 denote memories, for example, a 256K bit (64K × 4 bit) video RAM is used.

For example, of the 5-bit luminance signal Y from the A / D converter, four bits are written to the first to fourth bits of the memory 21 and the remaining one bit is written to the first bit of the memory 22.

Also, for example, a 4-bit color difference signal R from an A / D converter
-Y and BY are supplied to a switch circuit 24, and the switch circuit 24 outputs a luminance signal Y of 2 based on a switching control signal SW1.
The color difference signals RY and BY are output alternately for each dot. Then, of the four-bit color difference signals output from the switch circuit 24, three bits are written to the second to fourth bits of the memory 22, and the remaining one bit is written to the first bit of the memory 23.

FIG. 7A shows a luminance signal Y (Y00) in the memories 21 and 22.
2 to (Y256).
FIG. 6B shows the color difference signals RY and BY in the memories 22 and 23.
(Pixel data of RY01 to RY64, pixel data of BY01 to BY64).

The 5-bit luminance signal Y read from the memories 21 and 22 is supplied to, for example, a D / A converter.

The 4-bit color difference signals read from the memories 22 and 23 are supplied to a switch circuit 25. The switch circuit 25 outputs the color difference signals RY and BY for every two dots of the luminance signal Y by a switching control signal SW2. Are output alternately. The 4-bit color difference signals RY and BY output from the switch circuit 25 are, for example, D / A
Supplied to the converter.

[Problems to be Solved by the Invention] According to the example shown in FIG. 6, the color difference signal is written in the first bit of the memory 23, but nothing is written in the remaining 2nd to 4th bits. I have. That is, the memory cannot be used efficiently. The dot configuration and the bit configuration in the example of FIG. 6 are merely examples, and when other configurations are adopted, the efficient use of the memory similarly becomes a problem.

By the way, when data is transmitted using a general telephone line using a modem or the like, the data is generally transmitted in units of bytes (8 bits) due to CPU processing.

However, according to the example of FIG. 6, the output signals of the memories 21 to 23 have a total of 9 bits, and 1 bit needs to be transmitted later. However, in a general modem, even if amplitude modulation, phase modulation, frequency modulation, or AM-PM modulation combining these are used, gray scales are assigned to amplitude and the like.
The transmission speed is the same for both bytes and 1 bit. That is, in the example shown in FIG. 6, the output signals of the memories 21 to 23 become 9 bits in total and exceed 1 byte by 1 bit, so that twice the transmission time is required.

Therefore, an object of the present invention is to improve the use efficiency of the memory.

[Means for Solving the Problems] The present invention provides luminance signal data represented by 5 bits generated by A / D conversion of a luminance signal of a pixel, and 1/4 of the number of pixels of the luminance signal data. A video signal storage device that stores color difference signal data expressed by 4 bits generated by A / D conversion of color difference signals of pixels of a number of samples using a plurality of memory units for simultaneously writing and reading 4-bit parallel data. The luminance signal data is input to all bits of the first unit and 1 bit of the second unit of the memory at the same time as 5-bit parallel data, and the chrominance signal data is converted into serial data by parallel / serial conversion means. After that, the color difference signal data input to the remaining bits of the second unit memory and output from the second unit memory is serial / After being converted into parallel data by the parallel conversion means, the parallel data is held by the latch means until the next parallel data of the next color difference signal is generated, and the luminance signal data output from the memory is held by the latch means by the delay means. The color difference signal data is time-adjusted, and the luminance signal data and the color difference signal data are simultaneously output as parallel data.

[Operation] In the above-described configuration, the color difference signals RY and BY of pixels having a sample number of 1/4 of the number of pixels of the luminance signal Y are converted into serial data, input to the memory, and written. After the color difference signals RY and BY are read from the memory, they are returned to parallel data. Therefore, the memory can be used efficiently.

That is, when the luminance signal Y is, for example, 256 × 240 dots, the color difference signal R−Y,
BY becomes 4 bits at 64 × 240 dots, and 4 bits of the 5-bit luminance signal Y are stored in the first memory (256K = 64K ×
4K), and the remaining one bit is written to the second memory (256K = 64K × 4 bits). Also, 4
The serial data of the color difference signals RY and BY are written in the second and third bits of the second memory, respectively. Therefore, instead of three memories conventionally required, only two memories are required.

Embodiment An embodiment of the present invention will be described below with reference to FIG. In this example, the luminance signal Y is 256 × 2
5 bits at 40 dots, 6 for color difference signals RY and BY
4 × 240 dots and 4 bits.

In the figure, 1 and 2 are memories, for example, 25
A 6K bit (64K × 4 bit) video RAM is used.

The luminance signal Y is supplied to the A / D converter 3 and is sampled by a clock CK1 (shown in FIG. 3A) so as to form a 256 × 240 dot configuration, and is converted into a 5-bit digital signal per sample. You. 4 bits of the 5-bit luminance signal Y from the A / D converter are
The fourth bit is written, and the remaining one bit is written to the first bit of the memory 2. FIG. 3B shows the A / D converter 3
, Y00, Y01,... Are pixel data.

Also, for example, the red difference signal R supplied from the color demodulation circuit
−Y is supplied to the A / D converter 4 and 25 is supplied by the clock CK1.
Sampled into a 6 x 240 dot configuration, 1
The sample is converted to a 4-bit digital signal. this
The 4-bit color difference signal RY from the A / D converter 4 is supplied to a parallel / serial converter (P / S converter) 5. FIG. 3C shows an output signal of the A / D converter 4, and R-Y
00, R-Y01, ... are pixel data, respectively, and R-Y1
.About.R-Y4 are bit data constituting each pixel data.

A register (not shown) of the P / S converter 5 stores every four pixel data R-Y00, R-Y04,... Among the pixel data R-Y00, R-Y01,. It is captured. Then, each bit data is sequentially output by the clock CK1 and converted into serial data (shown in FIG. 3D). As described above, since the P / S converter 5 takes in every four pixel data, the dot configuration of the color difference signal RY is substantially 64.
× 240.

The serial data output from the P / S converter 5 is supplied to the memory 2 and written into the second bit.

Also, for example, the blue difference signal B supplied from the color demodulation circuit
-Y is supplied to the A / D converter 6, and 25 is supplied by the clock CK1.
Sampled into a 6 x 240 dot configuration, 1
The sample is converted to a 4-bit digital signal. this
The 4-bit color difference signal BY from the A / D converter 6 is supplied to the P / S converter 7. FIG. 3E shows an output signal of the A / D converter 6, where BY00, BY01,... Represent pixel data, and BY1 to BY4 represent each pixel data. Bit data to be configured.

A register (not shown) of the P / S converter 7 stores every four pixel data B-Y00, B-Y04,... Among the pixel data B-Y00, B-Y01,. It is captured. Then, each bit data is sequentially output by the clock CK1 and converted into serial data (shown in FIG. 6F). As described above, the P / S converter 7 captures every four pixel data, so that the dot configuration of the color difference signal BY is substantially 64.
× 240.

The serial data output from the P / S converter 7 is supplied to the memory 2 and written in the third bit.

Even if not described above, the clock CK1 is supplied to the memories 1 and 2 as a write clock.

FIG. 2 shows a data array in the memories 1 and 2. As is clear from this figure, the luminance signal Y is general, but the color difference signals RY and BY are developed in a 4-bit depth direction for four dots of the luminance signal Y. It becomes the array to be performed.

Returning to FIG. 1, the clock CK2 is output from the memories 1 and 2.
(Shown in FIG. 4A)
(Shown in FIG. 4B) is supplied to the delay circuit 8.

Further, the serial data of the red color difference signal RY read out from the memory 2 with the clock CK2 (illustrated in FIG. D)
Are supplied to a serial / parallel converter (S / P converter) 9 and sequentially taken into a register (not shown) with a clock CK2. 4-bit parallel data is output from the output side of the S / P converter 9, and the parallel data is supplied to a latch circuit 10.

As shown in FIG. 4E, the output signal of the S / P converter 9 is 4
Bit data RY1 to RY4 constituting the pixel data of the color difference signal RY for each clock. The latch circuit 10 latches this pixel data with a latch pulse LA (shown in FIG. 4F) and holds it until the next pixel data is latched four clocks later (shown in FIG. 4G).

The color difference signal RY output from the latch circuit 10 is converted into an analog signal by the D / A converter 11 and output.

Further, serial data of the blue difference signal BY read from the memory 2 with the clock CK2 (shown in FIG. 7H)
The clock is supplied to the S / P converter 12 and sequentially taken into a register (not shown) with the clock CK2. This S / P converter 12
Outputs 4-bit parallel data from the output side,
This parallel data is supplied to the latch circuit 13.

As shown in FIG. 4I, the output signal of the S / P converter 12 is 4
Bit data BY-1 to BY-4 constituting pixel data of the color difference signal BY at each clock. The latch circuit 13 latches this pixel data with a latch pulse LA (shown in FIG. 4F) and holds it until the next pixel data is latched after 4 clocks (shown in FIG. 4J).

The color difference signal BY output from the latch circuit 13 is converted into an analog signal by the D / A converter 14 and output.

As described above, the chrominance signals RY and BY are delayed by approximately four clocks with respect to the luminance signal Y by the processing of the S / P converters 9 and 12, so that the luminance signal Y and the chrominance signals RY and B are delayed. For the time adjustment of −Y, the luminance signal Y is delayed by four clocks in the delay circuit 8 (shown in FIG. 4C).

The luminance signal Y output from the delay circuit 8 is a D / A converter 15
Is converted into an analog signal and output.

This example is configured as described above. The color difference signals RY and BY are converted into serial data and written into the memory 2, and the color difference signals RY and BY are read out from the memory 2. By returning the data to the parallel data later, the memory which conventionally required three memories (see FIG. 6) can be reduced to two. That is, according to this example, the memory can be used efficiently.

Further, according to this example, the output signals of the memories 1 and 2 have a total of 7 bits, which can be less than 1 byte, and can be transmitted in byte units. That is, the transmission speed can be doubled as compared with the related art.

Even if not described above, the remaining one bit not used in the memory 2 can be used as a control bit (for example, a parity bit) or the like, and can be configured for data transmission.

In the above embodiment, the luminance signal Y
256 × 240 dots, 64 for color difference signals RY and BY
Although the screen configuration of × 240 dots is shown, even if the screen configuration is half this, the transmission number of data for one line only changes from 256 times to 128 times, and the transmission algorithm is specially changed. There is an advantage that data transmission can be performed without necessity.

Further, the dot configuration and the bit configuration in the above-described embodiment are merely examples, and the present invention is not limited to these.

For example, when the luminance signal Y is 256 × 240 dots and 5 bits, and the color difference signals RY and BY are 64 × 60 dots and 6 bits, the color difference signals RY and BY are The upper three bits correspond to the first dot of the luminance signal Y, the lower three bits correspond to the second dot of the luminance signal Y, and six bits of the color difference signals RY and BY are allocated to four dots of the luminance signal Y. be able to. FIG. 5B shows the data arrangement in the memories 1 and 2 in this case. In this case, the color difference signals RY,
BY is converted into serial data between the upper 3 bits and the lower 3 bits and input to the memory. Also, in this case, since all 8 bits in the memories 1 and 2 are used, control bits cannot be created as in the example of FIG.

FIG. 5A shows the data array of the example of FIG. In FIG. 5, C1, C2,... Are control bits, and Y1 to
Y5 is bit data constituting each pixel data Y00, Y01,... Of the luminance signal Y, and R-Y1 to R-Y6 and B-Y1 to
BY6 is the pixel data R of the color difference signals RY and BY.
. -Y00, R-Y01,... And BY-00, BY-Y01,. It should be noted that the luminance signal
Of course, the order of the bit data of the Y, color difference signals RY, BY can be changed arbitrarily.

[Effects of the Invention] As described above, according to the present invention, a 4-bit color difference signal of a pixel having 1/4 of the number of samples of a 5-bit luminance signal is converted into serial data, and is then transmitted together with 1 bit of the luminance signal. By inputting and writing, this color difference signal is read out from the memory and then returned to parallel data, so that there are only two memory units for writing and reading 4-bit parallel data simultaneously as memory. The memory can be used efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2 to 4 are diagrams for explaining the embodiment, FIG. 5 is a diagram for explaining another embodiment of the present invention, and FIG. The figure shows the configuration of the conventional example, and FIG.
The figure is a diagram for the explanation. 1,2 memory 3.4,6 A / D converter 5,7 parallel / serial converter 8 delay circuit 9,12 serial / parallel converter 10,13 latch circuit 11,14,15 …… D / A converter

Claims (1)

(57) [Claims] A luminance signal data represented by 5 bits generated by A / D conversion of a luminance signal of a pixel and a color difference signal of a pixel having a sample number of 1/4 of the number of pixels of the luminance signal data. In a video signal storage device for storing color difference signal data expressed by 4 bits generated by A / D conversion by using a plurality of memory units for simultaneously writing and reading 4-bit parallel data, the luminance signal data is 5 bits Are input simultaneously to all bits of the first unit and 1 bit of the second unit of the memory as parallel data, and the color difference signal data is converted to serial data by parallel / serial conversion means, and then the second data is converted to the second data. The color difference signal data input to the remaining bits of the unit memory and output from the second unit memory are converted into parallel data by serial / parallel conversion means. After that, this parallel data is held by the latch means until the next parallel data of the next color difference signal is generated, and the luminance signal data output from the memory is stored in the memory by the delay means. Wherein the luminance signal data and the chrominance signal data are simultaneously output as parallel data.