JP2617611B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a check pattern for measuring transistor characteristics.

[Conventional technology]

In general, a check pattern for measuring the threshold voltage of a transistor is inserted in a semiconductor integrated circuit in order to monitor the characteristics of a transistor used therein.

Check patterns of a conventional semiconductor integrated circuit will be described with reference to FIGS. 3 (a) and 3 (b).

As shown in FIGS. 3 (a) and 3 (b), the n-channel transistor Q _n1 and the p-channel transistor Q _p1 in the semiconductor integrated circuit have source terminals S _n and S _p and gate terminals G _n and G _n , _respectively , of external connection terminals. G _p and the drain terminal D _n, are connected to the D _p.

Next, a method of measuring the threshold voltage of the check pattern shown in FIG. 3 will be described.

In the case of the n-channel transistor _Qn1 , a positive potential is applied to the gate terminal _Gn , and the threshold voltage is measured.

In the case of the p-channel transistor Q _p1 , the gate terminal G _p
, And a threshold voltage is measured.

[Problems to be solved by the invention]

In a current semiconductor integrated circuit, a transistor is miniaturized for high integration and high density, and a channel length of the transistor is also shortened.

Due to this miniaturization, the channel length also varies between adjacent transistors, and the variation in the threshold value of those transistors becomes large.

Therefore, in a circuit using adjacent transistors such as a sense amplifier, it is difficult to utilize the symmetry of transistor characteristics in circuit design, and the circuit characteristics are degraded.

Therefore, in designing a semiconductor integrated circuit that does not degrade the circuit characteristics, it is necessary to understand the variation in the characteristics of adjacent transistors and reflect the variations in the circuit design.

However, a conventional semiconductor integrated circuit having a check pattern for measuring a threshold voltage has a configuration in which the threshold voltage is measured with a single transistor, so that the threshold voltage of an adjacent transistor can be measured. When measuring the threshold voltage of a transistor having a plurality of check patterns, there is a disadvantage in that an error occurs in the measurement of the transistor threshold voltage due to a variation in contact resistance generated when a measuring device is connected.

In addition, in order to form a check pattern of a plurality of transistors, there are disadvantages that the number of external output terminals for the gate and the drain increases, and the chip area increases.

That is, since the external output terminal is measured by a deep needle, a pad for a deep needle of about several tens of μm ² is required, and therefore, a chip area becomes large in order to measure a plurality of check pattern transistors.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit having a check-patterned transistor capable of ascertaining variations in threshold voltages of adjacent transistors with a small chip area.

[Means for solving the problem]

A semiconductor integrated circuit according to the present invention includes an address decoder circuit that inputs a plurality of address signals and outputs a decoder signal in a logical combination, and transfers a gate voltage for measurement applied to a common gate terminal by inputting the decode signal. A gate voltage output switching circuit for switching and outputting via a gate; and a plurality of MOS transistors to be measured whose gate receives the switched gate voltage and whose source is connected to a common source terminal and whose drain is connected to a common drain terminal. It is configured.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a schematic diagram of a check pattern according to a first embodiment of the present invention.

The semiconductor integrated circuit receives address signals S _A1 and S _A2 and outputs decoder signals S _{1 to} S _4.
When the gate voltage output switching circuit supplies by switching the gate voltage v _G of the common gate terminal G to the gate of the p-channel MOS transistor Q _p1 to Q _p4 to be measured is inputted to the transfer gate T ₁ through T ₄ decoder signal And 2.

The address decoder circuit 1 includes inverter circuits I ₁ , I ₂ and N
It is composed of AND circuits N _{1 to} N ₄ . Decoder signals S _{1 to} S ₄ input and output from the address input terminals A ₁ and A ₂ are applied to the gates of the transfer gates T _{1 to} T ₄ . Common drain terminal D and the common source terminal S is connected in common to the drain and source of the p-channel transistor Q _p1 to Q _p4.

Common gate terminal G is applying a potential to the gates of p-channel transistor Q _p1 to Q _p4 through the transfer gate T ₁ through T _4.

 Next, the operation will be described.

When the address signal S _A1 of the address decoder circuit 1 is “0”, S
For _A2 is "0", the inverter circuit I ₁ and the output signal of I ₂ are "1", among the NAND circuit N ₁ of N ₄ receives the signal, only a decoder signal S ₄ of the N ₄ is " 0 "and the remaining NAND
Decoder signal S ₁ to S ₃ output of N ₃ from the circuit N ₁ is "1".

When receiving the output signal S ₁ to S ₄ of the NAND circuit to the transfer gate T ₁ through T ₄ which receives the gate voltage v _G, the transfer gate T ₄ of the transfer gates T ₁ through T ₄
Only is turned on, the gate voltage as the gate signal p ₄
v by applying a _G at the gate of the transistor Q _p4 measuring the threshold voltage V _TP4 of the transistor Q _p4.

Next, when the address signal S _A1 is “0” and S _A2 is “1”, the decoder signal S ₃ of the NAND circuit N ₃ of the address decoder circuit 1 becomes “0” and the threshold voltage V _{TP3 of the} transistor Q _p3 Is measured.

Similarly, the threshold voltage V of the transistors Q _p1 and Q _p2
Measure _TP1 and _VTP2 .

According to this embodiment, the instrument may be connected once the common terminal G, S, to D, the measurement error of the threshold voltage V _T due to the difference of the connection is eliminated. In addition, one for a plurality of transistors
It suffices to provide a set of common gate, common source and common drain terminals, and the total terminal area is small.

FIG. 2 is a schematic diagram of a check pattern according to a second embodiment of the present invention.

Address decoder circuit 1 _a is an output signal with positive logic outputs to change the NAND logic of the address decoder 1 of FIG. 1 to the AND logic, the four by a gate voltage output switching circuit 2 _a n-channel MOS transistor Q _n1 to Q _n4 The threshold voltages V _{Tn1 to} V _Tn4 are measured by switching sequentially.

〔The invention's effect〕

As described above, the present invention uses an address decoder circuit and selects a transistor to be measured from a plurality of check pattern transistors according to an address signal of an external output terminal. The threshold voltages of a plurality of check patterns can be measured.

Also, by selecting the check pattern transistor based on the output of the address decoder circuit, the threshold voltage of a plurality of adjacent check pattern transistors can be measured without changing the connection of the measuring device. It becomes the threshold voltage of the transistor of the adjacent check pattern ignoring the variation.

Therefore, there is an effect that the variation of the threshold voltage of the transistor of the adjacent check pattern can be accurately grasped.

Further, according to the present invention, the gate area, the source terminal, and the drain terminal of each transistor can be made common to reduce the chip area.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a check pattern according to a first embodiment of the present invention, FIG. 2 is a schematic diagram of a check pattern according to a second embodiment of the present invention, and FIGS. 3 (a) and 3 (b) are conventional semiconductors. FIG. 3 is a schematic diagram of a check pattern of an n-channel MOS transistor and a p-channel MOS transistor of an integrated circuit. 1,1a ...... address decoder circuit, 2,2a ...... gate voltage output switching circuit, D ...... common drain terminal, G ...... common gate terminal, I ₃ ~I ₆ ...... inverter, M ₁ ~M ₄ ...... AND circuit, N _{1 to} N ₄ ... NAND circuit, Q _{n1 to} Q _n4.
Transistors, Q _{p1 to} Q _p4 ... P-channel MOS transistors, S... Common source terminals, S _{1 to} S ₄ .
S _A1 , S _A2 ... Address signal, T _{1 to} T ₈ ... Transfer gate, v _G ... Gate voltage.

Claims (1)

(57) [Claims] An address decoder circuit for inputting a plurality of address signals and outputting a decoder signal in a logical combination, and for inputting the decode signal and applying a gate voltage for measurement applied to a common gate terminal via a transfer gate. And a plurality of MOS transistors to be measured whose gates receive the switched-out gate voltage and whose sources are connected to a common source terminal and whose drains are connected to a common drain terminal. Semiconductor integrated circuit.