JP2615076B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to a DRAM.
(Dynamic Random Access Memory) and a technology effective when applied to a semiconductor integrated circuit device having the same.

[Conventional technology]

A DRAM memory cell includes a MISFET for selecting a memory cell and an information storage capacitor connected in series to one of the semiconductor regions. MISF for selecting the memory cell
The gate electrode of the ET is connected to a word line extending in the row direction, and is controlled by the word line. The other semiconductor region of the MISFET for selecting a memory cell is connected to a data line extending in the column direction.

This type of DRAM is highly integrated for increasing the capacity, and the size of the memory cell tends to be reduced. When the size of the memory cell is reduced, the size of the information storage capacitor is also reduced, so that the amount of stored charges forming information is reduced. The decrease in the amount of accumulated charge is largely affected by minority carriers generated by α-rays, and is liable to cause a so-called soft error. 1
The above phenomenon is remarkable in a DRAM having a large capacity of [Mbit] or more.

Therefore, a stacked structure (STC) is employed for the information storage capacitor of the memory cell of the DRAM. The information storage capacitor having the stacked structure is configured by sequentially laminating a first electrode layer, a dielectric film, and a second electrode layer on a semiconductor substrate. After forming the MISFET for selecting a memory cell, a part of the first electrode layer is connected to one semiconductor region of the MISFET,
The other portion is configured to be extended above the gate electrode of the MISFET. The first electrode layer is formed of an impurity (P or
As) is formed of a polycrystalline silicon film. The dielectric film is formed of a silicon oxide film formed by oxidizing the surface of the polycrystalline silicon film of the first electrode layer. The second electrode layer is formed integrally with the second electrode layer of another adjacent memory cell,
It is configured as a common plate electrode. The second electrode layer is formed of a polycrystalline silicon film like the first electrode layer.

The memory cell constituted by the stacked information storage capacitor element has a feature that a soft error can be reduced because a semiconductor substrate in which minority carriers are generated by incidence of α rays is not used for information storage. The stacked information storage capacitor is a MISF for memory cell selection.
By utilizing the step shape of the ET, the areas of the first electrode layer and the second electrode layer can be increased in the height direction. In other words, the information storage capacitor having the stacked structure can increase the amount of stored charges forming information, and thus has the characteristic of further reducing soft errors.

A DRAM in which a memory cell is composed of a stacked structure information storage capacitor is disclosed in, for example, Japanese Patent Application Laid-Open No. 61-18 / 1986.
3952 publication.

[Problems to be solved by the invention]

The inventor has found that prior to the development of a large-capacity DRAM, the following problems occur.

The memory cell of the DRAM is a MISFET for selecting a memory cell.
After that, a stacked structure information storage capacitor is formed. The source region and the drain region of the MISFET are formed by ion implantation with a high impurity concentration of 10 ¹⁵ [atoms / cm ² ] or more. The introduction of high-concentration impurities by ion implantation frequently causes crystal defects in the main surface of the semiconductor substrate (actually, the well region). This crystal defect cannot be sufficiently recovered by heat treatment (annealing) in a subsequent step.
For this reason, the charge stored in the information storage capacitor having the stacked structure leaks to the semiconductor substrate due to a crystal defect, so that the information holding characteristic of the DRAM deteriorates. This deterioration of the information retention characteristics increases the frequency of refreshing, so the DR
AM operation speed decreases.

An object of the present invention is to provide a technique capable of improving information holding characteristics in a DRAM in which a memory cell is formed by a stacked information storage capacitor.

Another object of the present invention is to provide a technique capable of achieving the above object and increasing the operating speed of a DRAM.

Another object of the present invention is to provide a technique capable of reducing the area of the memory cell and achieving high integration of the DRAM.

Another object of the present invention is to provide a technique capable of reducing a resistance value of a connection portion between one semiconductor region of a MISFET for selecting a memory cell of the memory cell and an information storage capacitor having a stacked structure. It is in.

It is another object of the present invention to provide a technique capable of preventing a short circuit between a data line connected to the memory cell and a substrate.

The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application is briefly described as follows.

MISF for memory cell selection in DRAM memory cells
One semiconductor region on the side to which the information storage capacitor of the ET stacked structure is connected is used for peripheral circuits other than memory cells.
It is configured by ion implantation with a lower impurity concentration than the semiconductor region of the MISFET.

Further, one of the semiconductor regions of the MISFET of the memory cell is formed by a low impurity concentration semiconductor region formed by the ion implantation and a high impurity concentration formed by diffusion of an impurity introduced into the electrode layer of the information storage capacitor. And a semiconductor region having an impurity concentration.

Further, the other semiconductor region of the MISFET of the memory cell is introduced through a connection hole connecting the low impurity concentration semiconductor region formed by the ion implantation and the other semiconductor region to a data line. And a semiconductor region with a high impurity concentration formed by the above.

[Action]

According to the above-described means, it is possible to reduce the occurrence of crystal defects on the substrate surface due to ion implantation and to reduce the leakage of electric charges serving as information stored in the information storage capacitor. Characteristics can be improved. As a result, the refresh characteristics can be improved, and the operating speed of the DRAM can be increased.

Further, since the semiconductor region of the MISFET for selecting a memory cell is formed with a low impurity concentration, the short channel effect can be suppressed, and the area of the memory cell can be reduced. As a result, DR
High integration of AM can be achieved.

Further, the contact resistance between one semiconductor region of the memory cell selecting MISFET and the electrode layer of the information storage capacitor can be reduced.

Further, a short circuit between the data line and the substrate due to misalignment of the mask between the other semiconductor region of the MISFET for selecting a memory cell and the data line can be prevented.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a large-capacity DRAM.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

(Example of the invention)

FIG. 1 (equivalent circuit diagram of a main part) shows a large-capacity DRAM according to an embodiment of the present invention.

As shown in FIG. 1, the DRAM is configured by a folded bit line system (a folded bit line system).
A memory cell array (memory cell mat) is arranged at the center of FIG.

The memory cell array has complementary data lines DL,
▲ ▼ is extended. A plurality of sets of the complementary data lines DL are arranged in the row direction. One end of each of the complementary data lines DL is connected to the sense amplifier SA.

A word line WL extends in a row direction crossing the complementary data line DL. A plurality of word lines WL are arranged in the column direction. Although not shown, each word line WL is connected to a row decoder circuit X-DE arranged at the end of the memory cell array.
It is configured to be connected to C and selected.

At the intersection of each of the complementary data lines DL and the word line WL, a memory cell M for storing 1 [bit] information is arranged. The memory cell M includes an n-channel MISFET Qs for selecting a memory cell and an information storage capacitor C having one electrode connected in series to one semiconductor region.

In the MISFETQs of the memory cell M, the other semiconductor region is connected to the complementary data line DL, and the gate electrode is connected to the word line WL. The other electrode of the information storage capacitor C is connected to a power supply voltage of 1/2 _Vcc . The power supply voltage 1 / 2V _cc is the circuit reference voltage V _ss (= 0 [V]) and the circuit power supply voltage 1 / 2V _cc
(= 5 [V]). Supply voltage 1 / 2V _cc applied to the other electrode reduces the electric field strength applied between the electrodes of the information storage capacitor C, and so as to reduce the deterioration of the dielectric strength of the dielectric film.

The sense amplifier SA is configured to amplify information of the memory cell M transmitted through the complementary data line DL. The information amplified by the sense amplifier SA is supplied to the common data line I / O, ▲ through the n-channel MISFETQy for the Y switch.
Output to ▼.

The MISFETQy for the Y switch has a gate electrode Y
It is configured to be connected to and controlled by the select signal line YSL. One Y select signal line YSL is provided for one set of complementary data lines DL. Y select signal line
The YSL extends in the same column direction as the complementary data lines DL, and is arranged between the complementary data lines DL. That is,
In other words, the complementary data line DL and the Y select signal line YSL
Are alternately arranged in the row direction. Y select signal line
The YSL is configured to be connected to and selected by a column decoder circuit Y-DEC disposed at an end of the memory cell array.

The common data line I / O is connected to a main amplifier MA arranged at an end of the memory cell array. The main amplifier MA is composed of a switch MISFET (not numbered), an output signal line DOL, ▲ ▼, and a data output buffer circuit DoB.
Are connected to the output transistor Dout. That is, the information of the memory cell M further amplified by the main amplifier MA is output to the output transistor Dout through the output signal line DOL, the data output buffer circuit DoB, and the like.

Next, a specific structure of the elements forming the memory cell M of the DRAM and the peripheral circuits of the DRAM (such as the sense amplifier SA and the column decoder circuit Y-DEC) will be described.

A memory cell array of the DRAM is shown in FIG. 2 (a plan view of a main part), and elements of the memory cell array and peripheral circuits are shown in FIG. 3 (a cross-sectional view of a main part). The left side of FIG. 3 shows a cross section of the memory cell M section taken along the line II of FIG. 2, and the central part of FIG. 3 shows the guard ring section taken along the line II-II of FIG. It shows a cross section. The right side of FIG. 3 shows a cross section of a complementary MISFET (CMOS) constituting a peripheral circuit.

As shown in FIGS. 2 and 3, the DRAM is constituted by a p ^- type semiconductor substrate 1 made of single crystal silicon. Memory cell M (memory cell array) formation region of semiconductor substrate 1 and n
A p-type well region 2 is provided on the main surface of the channel MISFET Qn formation region. P-channel MISF of semiconductor substrate 1
An n-type well region 3 is provided on the main surface of the ET formation region Qp. That is, the DRAM of the present embodiment employs a twin-well structure.

On the main surface between the semiconductor element formation regions of the well regions 2 and 3, an element isolation insulating film (field insulating film) 5 is formed.
Is provided. The element isolation insulating film 5 is configured to electrically isolate semiconductor elements. A p-type channel stopper region 4A is provided below the element isolation insulating film 5 and on the main surface of the well region 2. The parasitic MOS having the element isolation insulating film 5 as a gate insulating film is n
Since the mold is easily inverted, the channel stopper region 4A is provided at least on the main surface of the well region 2.

A p-type potential barrier layer 4B is provided on a main surface of the well cell 2 in the memory cell M formation region. The potential barrier layer 4B is provided on substantially the entire surface of the memory cell M formation region. Potential barrier layer 4B
As will be described in detail later, is formed using the same manufacturing process and the same manufacturing mask as the channel stopper region 4A. This potential barrier layer 4B is formed by a p-type impurity (B) introduced into a formation region for forming a channel stopper region.
Is extended to below the memory cell M formation region and diffused.

The MISFETQs for selecting the memory cell of the memory cell M is the second MISFETQs.
As shown in FIG. 3, FIG. 3 and FIG. 4 (main part plan views in a predetermined manufacturing process), the well region 2 (actually, the potential barrier layer 4B) is formed on the main surface portion. MISFETQs
Are the insulating film 5 for element isolation and the channel stopper region 4A
Surrounds the area and defines its shape. This MI
The SFET Qs is basically mainly composed of a well region 2, a gate insulating film 6, a gate electrode 7, and a pair of n-type semiconductor regions 9 which are a source region or a drain region.

The well region 2 is used as a channel forming region of the MISFETQs.

Gate insulating film 6 is formed of a silicon oxide film formed by oxidizing the main surface of well region 2.

The gate electrode 7 is provided on the gate insulating film 6, and is made of, for example, a polycrystalline silicon film deposited by CVD. In this polycrystalline silicon film, an n-type impurity (P or As) for reducing a resistance value is introduced.

The gate electrode 7 is made of a refractory metal (Mo, Ti, Ta, W) film or a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WS).
i ₂ ) It may be composed of a single layer of a film. Also, the gate electrode 7
May be composed of a composite film in which the metal film is laminated on a polycrystalline silicon film.

As shown in FIGS. 2 and 4, the gate electrode 7 is integrally formed with a word line (WL) 7 extending in the row direction. That is, the gate electrode 7 and the word line 7 are formed of the same conductive layer. The word line 7 is configured to connect the respective gate electrodes 7 of the MISFETs Qs of the plurality of memory cells M arranged in the row direction.

The semiconductor region 9 is formed by ion implantation with a low impurity concentration at least on one side (one side) to which the information storage capacitive element C is connected, as compared with the semiconductor region (17) of the MISFETQs constituting the peripheral circuit. Specifically, one of the semiconductor regions 9 includes 1
It is configured by ion implantation with a low impurity concentration of less than × 10 ¹⁴ [atoms / cm ² ]. According to the inventor's basic research, 1
The semiconductor region 9 formed by ion implantation with a low impurity concentration of less than × 10 ¹⁴ [atoms / cm ² ] has few crystal defects generated on the main surface of the well region 2 due to the introduction of the impurity, The result that the crystal defect can be sufficiently recovered by the heat treatment is obtained.

The semiconductor region 9 is configured to be self-aligned with the gate electrode 7. Since the semiconductor region 9 has a low impurity concentration on the channel forming region side, an LDD (Lightly Doped) is formed.
Drain) structure MISFETQs.

FIGS. 2, 3, and 5 (plan views of main parts in a predetermined manufacturing process) of the information storage capacitive element C of the memory cell M.
As shown in the figure, mainly, the first electrode layer (lower electrode layer) 13,
The dielectric film 14 and the second electrode layer (upper electrode layer) 15 are sequentially laminated. The information storage capacitive element C has a so-called stacked structure (stacked type: STC).

A part (center part) of the first electrode layer 13 of the information storage capacitor C having the stacked structure is connected to one semiconductor region 9 of the MISFETQs. This connection is made through a connection hole 12A formed in the interlayer insulating film 12. Connection hole 12A
Is larger than the size between the gate electrode 7 of the MISFET Qs and the side wall spacer 11 provided on each side wall of the word line 7 adjacent to the gate electrode 7 of the MISFET Qs. Is determined by the size between the sidewall spacers 11. Connection hole 12
The difference between the opening size of A and the size between the sidewall spacers 11 is at least larger than the size corresponding to the mask alignment margin in the manufacturing process. First electrode layer 13
The other portion (peripheral portion) of the gate electrode 7 and the word line 7 are interposed with the sidewall spacer 11 and the interlayer insulating film 8 interposed therebetween.
Are extended to the respective upper portions.

The first electrode layer 13 is made of, for example, a polycrystalline silicon film into which an n-type impurity (As or P) for reducing a resistance value is introduced at a high concentration. The n-type impurity introduced into the polycrystalline silicon film is transferred from the connection between the first electrode layer 13 and the one semiconductor region 9 defined by the sidewall spacer 11 to the one semiconductor region 9.
The n ⁺ -type semiconductor region 13A is diffused to the side and has a high impurity concentration and is formed integrally with the semiconductor region 9.

The other part of the first electrode layer 13 is a set of complementary data lines (21).
It is drawn in the row direction (upward or downward) from the area defined by DL. That is, the first electrode layer 13 is extended from the memory cell M formation region surrounded by the element isolation insulating film 5 to a region outside the memory cell M formation region. The first electrode layer 13 is separated from the first electrode layer 13 (formed of the same conductive layer) of the information storage capacitor C of another memory cell M adjacent in the row direction so as not to be in contact therewith. , The plane shape is a pentagon. The first electrode layer 13 is configured to extend to a position overlapping the Y select signal line (21) YSL adjacent in the row direction to the complementary data line (21) DL to which the memory cell M having the first electrode layer 13 is connected. Have been. Actually, since the Y select signal line (21) YSL is formed above the first electrode layer 13, the first electrode layer 13 extends below the Y select signal line (21) YSL at a position overlapping therewith. It is configured as follows.

The dielectric film 14 is basically formed by stacking a silicon nitride film 14A deposited on the first electrode layer (polycrystalline silicon film) 13 by CVD and a silicon oxide film 14B obtained by oxidizing the silicon nitride film 14A at a high pressure. It has a two-layer structure. In practice, the dielectric film 14
Since a natural silicon oxide film is formed on the surface of the polycrystalline silicon film (in which an n-type impurity is introduced) which is the first electrode layer 13,
It has a three-layer structure in which a natural silicon oxide film (not shown because it has a very small thickness of less than 50 [Å]), a silicon nitride film 14A and a silicon oxide film 14B are sequentially laminated.

Since the silicon nitride film 14A of the dielectric film 14 is deposited by CVD,
Irrespective of the crystal state or the step shape of the underlying polycrystalline silicon film (first electrode layer 13), it can be formed under independent process conditions for the underlying layer. That is, the silicon nitride film 14A has a higher dielectric breakdown voltage and a smaller number of defects per unit area than the silicon oxide film formed by oxidizing the surface of the polycrystalline silicon film, so that the leak current is very small. Moreover, a silicon nitride film
14A is characterized by a higher dielectric constant than a silicon oxide film. Since the silicon oxide film 14B can be formed of a very high quality film, the characteristics of the silicon nitride film 14A can be further improved. As will be described later in detail, since the silicon oxide film 14B is formed by high-pressure oxidation (1.5 to 10 [toll]), the silicon oxide film 14B can be formed with a shorter oxidation time, that is, a heat treatment time than normal-pressure oxidation.

The dielectric film 14 is provided along the upper surface and the side wall of the first electrode layer 13, and uses the side wall portion of the first electrode layer 13 to increase the area in the height direction. The increase in the area of the dielectric film 14 can improve the amount of charge stored in the information storage capacitor C having the stacked structure. The planar shape of the dielectric film 14 is defined by the shape of the upper second electrode layer 15, and is substantially the same shape as the second electrode layer 15.

The second electrode layer 15 is provided above the first electrode layer 13 with the dielectric film 14 interposed therebetween. The second electrode layer 15 is formed integrally with the second electrode layer 15 of the information storage capacitor C of another adjacent memory cell M. The second electrode layer 15 is configured so that a power supply voltage of 1/2 _Vcc is applied. The second electrode layer 15 is formed of, for example, a polycrystalline silicon film into which an n-type impurity for reducing a resistance value is introduced.

The memory cell M thus configured is connected to another memory cell M adjacent in the column direction. This connection is made by integrally configuring the other semiconductor regions 9 of the MISFETs Qs for selecting the memory cells of the memory cells M.

In the other semiconductor region 9 of the MISFETQs of the memory cell M,
The complementary data line (DL) 21 is connected. The complementary data line 21 is connected to the semiconductor region 9 through a connection hole 19C formed in the interlayer insulating film 19.

As shown in FIGS. 2 and 3, a high impurity concentration n ⁺ -type semiconductor region 20 is provided at a connection portion between the complementary data line 21 and the semiconductor region 9. The semiconductor region 20 has a connection hole
It is formed by introducing an n-type impurity (As or P) by ion implantation through 19C. That is, the semiconductor region 20 is formed integrally with the semiconductor region 9. In the semiconductor region 20, when the connection hole 19C is misaligned in the manufacturing process with respect to the semiconductor region 9 and the connection hole 19C is formed on the end of the isolation insulating film 5, the well region 2 and the complementary data line are formed. This is provided to prevent short circuit with 21.

The interlayer insulating film 19 is a silicon oxide film 19 in this embodiment.
A, It has a two-layer structure in which a silicon oxide film (BPSG) 19B capable of glass flow is laminated. Upper silicon oxide film 19B
Is configured so that its surface can be flattened by applying a glass flow. The lower silicon oxide film 19A is provided in order to secure a withstand voltage and prevent B and P introduced into the upper silicon oxide film 19B from leaking to the element.

The complementary data line 21 includes a barrier metal film 21A (metal wiring), an aluminum film 21B (metal wiring), and a protective film 21C.
(Metal wiring) are sequentially laminated.

The aluminum film 21B is added with an element (Si) for preventing aluminum spikes and an element (Cu, Pd, Ti, or the like) for reducing migration. The aluminum film 21B according to the present embodiment has about 1.5 [% by weight] of
It is constituted by adding about 5% by weight of Cu.

The barrier metal film 21A is configured to prevent single crystal silicon from being deposited at a connection portion between the aluminum film 21A and the semiconductor region 9 (actually, the semiconductor region 20), thereby preventing the resistance value of the connection portion from increasing. I have. Barrier metal film 21A is composed of MoSi _2. Further, the barrier metal film 21A may be formed of a refractory metal silicide film or a refractory metal film other than the above.

The protective film 21C is configured to protect the aluminum film 21B from a liquid used in a wet process for forming the aluminum film 21B (for example, a stripping solution process for removing a photoresist film as an etching mask or a water washing process). . The aluminum film 21B to which the element (Cu) for reducing migration is added constitutes a battery using aluminum as a base as an anode and an intermetallic compound formed of the aluminum and Cu as a cathode. This battery is
The cell reaction is caused by the liquid used in the wet processing. The protective film 21C is configured to prevent this battery reaction. When a battery reaction occurs, aluminum around the intermetallic compound is scraped off (pit corrosion occurs).

The protective film 21C is made of MoSi _x . In addition, the protective film 21C
Other high melting point metal silicides (TiSi _x , TaSi _x , WS
i _x) may be constituted by a film or a refractory metal film. Protective film 21C
Is formed with a thin film thickness of about 100 to 4000 [Å].

When the protective film 21C is formed of a high melting point metal silicide film such as MoSi _{x, the} aluminum film 21 is formed depending on the content of silicon (Si).
Aluminum particles diffuse from B, and aluminum oxide (Al ₂ O ₃ ) is deposited on the surface of the protective film 21C. The deposition of the aluminum oxide causes poor contact between the protective film 21C and the upper wiring (23). As a result of the basic research conducted by the inventor, as shown in FIGS. 6 to 8 (a diagram showing the composition of the wiring by Auger electron spectroscopy), the silicon content of MoSi _x as the protective film 21C is less than 0. It is set to be larger than 2 (0 <x <2).

6 to 8 show the structure (Al
-Cu-Si / MoSi _x / Si substrate) was subjected to a heat treatment at 475 [° C.] for 3 hours, and thereafter, the sample in which the upper layer of Al-Cu-Si was removed with aqua regia was measured by Auger electron spectroscopy. Represents data. The horizontal axis indicates the sputter etching time [min] from the surface of MoSi _x . The vertical axis indicates the intensity of Auger electrons emitted from each element (Mo, Si, O, Al) on the sample surface corresponding to each sputtering time. Auger electron spectroscopy measures the energy of Auger electrons emitted from the sample surface by irradiating the sample surface with electrons each time the sample surface is sputter-etched for a predetermined time.
The element can be identified and the content of the element can be measured.

FIG. 6 shows that the silicon content x is 2, that is, MoSi ₂ (Mo: Si =
1: 2). As shown in FIG. 6, when the silicon content x exceeds 2, aluminum particles that have passed through MoSi ₂ are precipitated at the interface between MoSi ₂ and the Si substrate, and the aluminum particles and oxygen are combined. As a result, aluminum oxide (Al ₂ O ₃ ) is generated.

FIG. 7 shows that the silicon content x is less than 2
FIG. 8 shows data in the case of _1.2 (Mo: Si = 1: 1.2), and FIG. 8 shows data in the case of a silicon content x of 0.8, ie, MoSi _0.8 (Mo: Si = 1: 0.8). As shown in FIGS. 7 and 8, when the silicon content x is less than 2, aluminum particles that have passed through MoSi _x are precipitated at the interface between MoSi _x (0 <x ≦ 1.2) and the Si substrate. No aluminum oxide was generated. As a result of basic research by the present inventors, the silicon content x of the protective film 21C is preferably less than 2 and more preferably 1.2 or less.

In the same column direction as the direction in which the complementary data lines (DL) 21 extend, Y formed of the same conductive layer (the same three-layer structure) is used.
The select signal line (YSL) 21 extends. As described above, the first electrode layer 13 of the information storage capacitor C having the stacked structure is drawn out until it is located below the Y select signal line 21.

Complementary data line 21 and Y select signal line 21 (wiring 21)
Are formed by a first-layer wiring forming step in the manufacturing process. The complementary data line 21 and the Y-select signal line 21 formed in the first-layer wiring forming step are formed on the upper layer wiring (23) in order to alleviate the step shape peculiar to the multilayer wiring structure.
It is configured with a thin film thickness as compared with.

As shown in FIGS. 2 and 3, the complementary data lines
A shunt word line (WL) 23 extends in the row direction above the layer 21 and the Y select signal line 21 with an interlayer insulating film 22 interposed therebetween. The shunt word line 23 is
Although not shown, in a predetermined region corresponding to every several tens to several hundreds of memory cells M, the intermediate conductive layer (not shown) is once formed through the same connection hole 22D as shown on the right side (peripheral circuit) of FIG. Debited and connected to it. The intermediate conductive layer is formed in the first-layer wiring forming step, and the connection hole 19C is formed.
Through to the word line 7. The shunt word line 23 is configured to reduce the resistance value of the word line 7. That is, the shunt word line 23 is configured to increase the selection speed of the memory cell M. The intermediate conductive layer reduces the step shape when connecting the shunt word line 23 and the word line 7, and reduces the shunt word line 23.
It is configured to prevent disconnection of 23.

As shown in FIG. 3, the interlayer insulating film 22 is made of plasma.
It has a three-layer structure in which a silicon oxide film 22A deposited by CVD, a silicon oxide film 22B coated and baked, and a silicon oxide film 22C deposited by plasma CVD are sequentially laminated. The intermediate silicon oxide film 22B of the interlayer insulating film 22 is configured to flatten the surface of the upper silicon oxide film 22C.

The connection hole 22D formed in the interlayer insulating film 22 has a stepped shape in cross section in which the upper opening size is large and the lower opening size is small. The connection hole 22D is configured so as to reduce the shape of the step at the time of connecting the shunt word line 23 and the intermediate conductive layer, thereby preventing the shunt word line 23 from breaking.

The shunt word line 23, as shown in FIG.
It has a two-layer structure in which a base film 23A and an aluminum film 23B are sequentially laminated.

The base film 23A is composed of MoSi _2. In MoSi ₂ , Mo enters the aluminum film 23B and can suppress the growth of crystal grains of the aluminum film 23B, so that stress migration can be reduced. The base film 23A may be formed of a refractory metal silicide film or a refractory metal film other than those described above.

The aluminum film 23B contains Si and Cu as in the case of the aluminum film 21B.

The shunt word line 23 is formed by a second-layer wiring forming process in the manufacturing process. A shunt word line formed by the second layer wiring forming process
Reference numeral 23 is formed to have a larger film thickness than the lower-layer wiring (21) formed in the first-layer wiring forming step, and is configured to reduce the resistance value.

The upper part of FIG. 2 and the center part of FIG. 3 show the end of the memory cell array, and a guard ring GL is provided in this part. The guard ring GL is configured to surround the periphery of the memory cell array, and is configured to mainly capture minority carriers emitted from a substrate bias generation circuit (not shown). The guard ring GL includes a semiconductor region 9 provided on the main surface of the well region 2 in a region defined by the element isolation insulating film 5 and the channel stopper region 4A. In the guard ring GL, the wiring 21 formed in the wiring forming step of the first layer has a connection hole.
Connected through 19C. The power supply voltage 1
/ 2V _cc is applied. The wiring 21 is connected to the second electrode layer 15 through the connection hole 19C, and is configured to apply a power supply voltage of 1/2 _Vcc to the second electrode layer 15.

As described above, in the DRAM, one set of complementary data lines (DL) 21 and one Y select signal line (YSL) 21 for selecting the set of complementary data lines 21 are formed of the same conductive layer. , And extend in the same column direction, and the complementary data lines 21
And the Y select signal line 21 are alternately arranged in the row direction. The complementary data line 21 has a MISFET Qs for selecting a memory cell and an information storage capacitor of a stacked structure connected in series to one of the semiconductor regions 9. And a first electrode layer 13 constituting the stacked information storage capacitance element C is connected to a Y-selection cell adjacent to the complementary data line 21 to which the memory cell M is connected. By extending to the position overlapping with the signal line 21, the area of the first electrode layer 13 of the information storage capacitor C having the stacked structure can be increased by using the space in which the Y select signal line 21 extends. Therefore, the information storage capacitive element C having a stacked structure
Can be increased. The first electrode layer 13 of the information storage capacitive element C having the stacked structure is not formed in a symmetrical shape with respect to the complementary data line 21 but in an asymmetrical shape drawn to a lower portion of the Y select signal line 21. I have. The fact that the amount of charge stored in the information storage capacitor C having the stacked structure can be increased can reduce soft errors in the memory cell mode of the DRAM. Further, the noise margin of the information read signal of the DRAM can be increased.

The CMOS constituting the peripheral circuit is configured as shown on the right side of FIG. The CMOS n-channel MISFET Qn is formed on the main surface of the well region 2 in a region surrounded by the element isolation insulating film 5 and the channel stopper region 4A. The MISFET Qn mainly includes a well region 2, a gate insulating film 6, a gate electrode 7, a pair of n-type semiconductor regions 9 serving as a source region and a drain region, and a pair of n ⁺ -type semiconductor regions 17.

Each of the well region 2, the gate insulating film 6, the gate electrode 7, and the semiconductor region 9 is provided with the MISFET Qs for selecting the memory cell.
And has the same function.
That is, the MISFETQn has an LDD structure.

The high impurity concentration semiconductor region 17 is configured to reduce the specific resistance of each of the source region and the drain region. The semiconductor region 17 is defined by a sidewall spacer 11 formed on the side wall of the gate electrode 7 by self-alignment, and is formed by self-alignment with the gate electrode 7.

A connection hole is formed in the semiconductor region 17 used as a source region.
Wires 21 reference voltage V _ss is applied are connected through 19C. An output signal wiring 21 is connected to the semiconductor region 17 used as a drain region through a connection hole 19C. A semiconductor region 20 for preventing a short circuit between the well region 2 and the wiring 21 is provided on a main surface portion of the well region 2 at a connection portion between the semiconductor region 17 and the wiring 21. These wirings 21 are formed in a first-layer wiring forming step.

CMOS p-channel MISFETQp is an insulating film 5 for element isolation.
Is formed on the main surface of the well region 3 in the region surrounded by. The MISFET Qp mainly includes a well region 3, a gate insulating film 6, a gate electrode 7, a pair of p-type semiconductor regions 10 as a source region and a drain region, and a pair of p ⁺ -type semiconductor regions 18.

Each of the well region 3, the gate insulating film 6, and the gate electrode 7 has substantially the same function as each of the MISFETs Qs and Qn.

The low impurity concentration p-type semiconductor region 10 is
The MISFET Qp having the LDD structure is provided between the p ⁺ type semiconductor region 18 and the channel formation region.

A connection hole is formed in the semiconductor region 18 used as a source region.
The wiring 21 to which the power supply voltage _Vcc is applied is connected through 19C. An output signal wiring 21 integrally formed with the output signal wiring 21 is connected to the semiconductor region 18 used as a drain region through a connection hole 19C. These wirings 21 are formed in a first-layer wiring forming step.

The output signal wiring 21 is connected to the second through a connection hole 22D.
The output signal wiring 23 formed in the wiring forming step of the layer is connected.

Next, a specific method of manufacturing the DRAM will be briefly described with reference to FIGS. 9 to 26 (cross-sectional views showing main parts in predetermined manufacturing steps).

First, a p ^- type semiconductor substrate 1 made of single crystal silicon is prepared. The semiconductor substrate 1 is configured to have a resistance value of, for example, about 8 to 12 [Ω-cm].

Next, a silicon oxide film 24 is formed on the main surface of the semiconductor substrate 1. The silicon oxide film 24 is formed by high-temperature steam oxidation of about 900 to 1000 [° C.], for example, 400 to 500 [Å].
It is formed with a film thickness of about.

Next, an oxidation resistant film 25 is formed on the silicon oxide film 24.
The oxidation resistant film 25 is formed using a silicon nitride film deposited by, for example, CVD, and has a thickness of, for example, about 400 to 600 [Å].

Next, the oxidation-resistant film 25 in the n-type well region formation region is selectively removed to form an impurity introduction mask and an oxidation-resistant mask. The selective removal of the oxidation-resistant film 25 is performed by, for example, a photolithography technique of etching using a photoresist film.

Next, as shown in FIG. 9, the oxidation-resistant film 25 and a photoresist film (not shown) for patterning the oxidation-resistant film 25 are used as a mask for impurity introduction, and are selected on the main surface of the semiconductor substrate 1 through the silicon oxide film 24. The n-type impurity 3n is introduced specifically. The n-type impurity 3n is introduced by ion implantation at an energy of about 120 to 130 [KeV] using, for example, P having an impurity concentration of about 10 ¹³ [atoms / cm ² ].

Next, the photoresist film on the oxidation-resistant film 25 is removed.
Thereafter, as shown in FIG. 10, the exposed silicon oxide film 24 is grown using the oxidation-resistant film 25 as an oxidation-resistant mask to form a silicon oxide film 24A. The silicon oxide film 24A is formed only in the n-type well region formation region. The silicon oxide film 24A has a thickness of about 9
It is formed by steam oxidation at a high temperature of 100 to 1000 [° C.], for example, so as to finally have a film thickness of about 1100 to 1200 [Å]. This silicon oxide film 24A is used as a mask for impurity introduction when forming a p-type well region. By the oxidation step of forming the silicon oxide film 24A,
The introduced n-type impurity 3n is slightly diffused to form an n-type semiconductor region (finally a well region) 3A.

Next, the oxidation resistant film 25 is selectively removed. Oxidation resistant film
25 is removed, for example, with hot phosphoric acid. Thereafter, as shown in FIG. 11, the silicon oxide film 24A is used as a mask for introducing impurities, and the p-type well region forming region through the silicon oxide film 24 is selectively formed on the main surface portion of the semiconductor substrate 1 by p-type. Impurity 2p is introduced. The p-type impurity 2p is, for example, 10 ¹² to 10 ¹³ [atoms / c
BF ₂ (or B) having an impurity concentration of about m ² ] and ion-implanted. This p-type impurity 2p is
Since A is formed, it is not introduced into the main surface of the semiconductor region 3A to be an n-type well region.

Next, as shown in FIG. 12, each of the n-type impurity 3n and the p-type impurity 2p is extended and diffused, and as shown in FIG. 12, the n-type well region 3 and the p-type well region 2 are formed. To form The well regions 2 and 3 are formed by performing heat treatment in a high temperature atmosphere of about 1100 to 1300 [° C.]. As a result, p-type well region 2 is formed in self-alignment with n-type well region 3.

Next, an oxidation resistant film 26 is formed on the entire surface of the substrate including the silicon oxide films 24 and 24A. The oxidation resistant film 26 is used as an impurity introduction mask and an oxidation resistant mask. The oxidation-resistant film 26 is, for example, a silicon nitride film deposited by CVD,
It is formed with a film thickness of about 1400 [Å].

Next, a photoresist film is applied on the oxidation-resistant film 26, the photoresist film is removed in a region where the element isolation insulating film (5) is formed, and an etching mask and an impurity introduction mask (not shown) are formed. . Using this mask, the exposed oxidation-resistant film 26 is selectively removed.

Next, a p-type impurity 4p is introduced into the main surface of the well region 2 through the exposed silicon oxide film 24 by using a mask made of the oxidation-resistant film 26 and a photoresist film formed by patterning the oxidation-resistant film 26 as an impurity introduction mask. . The p-type impurity 4p is not introduced into the main surface of the well region 3 because the silicon oxide film 24A having a larger thickness than the silicon oxide film 24 is formed on the main surface of the well region 3. That is, the p-type impurity 4p is selectively introduced into the main surface of the well region 2. p-type impurity 4p
Form a channel stopper region and a potential barrier layer. The p-type impurity 4p is 10 ¹³ [at
oms / cm ² ] and ion implantation using BF ₂ or B having an impurity concentration of about oms / cm ² ]. After introducing this p-type impurity 4p,
As shown in FIG. 13, the photoresist film on the oxidation resistant film 26 is removed.

Next, using the oxidation-resistant film 26 as an oxidation-resistant mask,
Each of the exposed silicon oxide films 24 and 24A is grown to form an element isolation insulating film (field insulating film) 5. The element isolation insulating film 5 is subjected to a heat treatment of about 110 to 130 [min] in a nitrogen gas atmosphere at a high temperature of, for example, about 1000 [° C.] and then to a steam oxidation of about 150 to 160 [min]. Formed. Alternatively, it is formed only in a steam oxidation atmosphere. The element isolation insulating film 5 is, for example, 6000 to 8000.
It is formed with a film thickness of about [Å].

The p-type impurity 4p introduced into the main surface portion of the well region 2 is extended and diffused by substantially the same manufacturing process as the process of forming the element isolation insulating film 5, thereby forming the p-type channel stopper region 4A. Is formed. When the channel stopper region 4A is formed, a relatively long heat treatment is performed as described above. Therefore, as shown in FIG. 27 (impurity concentration distribution diagram), lateral diffusion is large, and particularly in a memory cell array. Almost the entire surface of the memory cell M formation region is p-type impurity 4p
Is diffused to form a p-type potential barrier layer 4B.

FIG. 27 shows the depth [μ] from the surface of the well region 2 on the horizontal axis.
m], and the vertical axis indicates the concentration of p-type impurity (boron) 4p. As shown in FIG. 27, when the distribution (dotted line) at the time of introducing the p-type impurity 4p and the distribution (solid line) after the above-described heat treatment are compared, the impurity is diffused by about 0.4 to 0.6 [μm]. You can see that. A large-capacity DRAM uses a memory cell M
The gate width (channel width) of the MISFETQs for selecting a memory cell and the size of the semiconductor region 9 in that direction are 1.0
[Μm], the p-type impurity 4p forming the channel stopper region 4A is diffused to substantially the entire surface of the memory cell M formation region, and the potential barrier layer 4B is formed substantially over the entire surface of the memory cell M formation region as described above. It is formed.

In the n-channel MISFETQn formation region constituting the CMOS of the peripheral circuit, the size of the MISFETQn is larger than the size of the memory cell M, so that the p-type impurity 4p is diffused only in a part near the element isolation insulating film 5, Substantially no potential barrier layer 4B is formed. That is, the potential barrier layer 4B is not formed in the MISFETQn formation region of the peripheral circuit, but is selectively formed in the memory cell array formation region. Moreover, the potential barrier layer 4B can be formed in the same manufacturing process as the channel stopper region 4A.

The channel stopper region 4A, a potential barrier layer
After heat treatment, each of 4B has an impurity concentration of about 10 ¹⁶ to 10 ¹⁷ [atoms / cm ³ ]. The channel stopper region
After forming the potential barrier layer 4A and the potential barrier layer 4B, the oxidation-resistant film 26 is selectively removed as shown in FIG.

As described above, in the DRAM in which the memory cell M is surrounded by the element isolation insulating film 5 and the channel stopper region 4A, the main surface portion between the MISFETs of the memory cell M in the well region 2 has the same conductivity type as the well region 2. A p-type impurity 4p having a higher concentration than that is introduced, and the p-type impurity 4p is transferred to the well region until at least below the formation region of one semiconductor region 9 (the connection side with the information storage capacitor C) of the MISFETQs. 2 to form a channel stopper region 4A and a potential barrier layer 4B, and the MISF of the well region 2
By forming the element isolation insulating film 5 on the main surface between the ETs, the step of forming the potential barrier layer 4B can be shared with the step of forming the channel stopper region 4A. Can be reduced.
That is, the mask forming step and the impurity introducing step for forming the potential barrier layer 4B can be reduced.

Further, since the potential barrier layer 4B can be formed in a self-alignment manner with each of the inter-element isolation insulating film 5 and the channel stopper region 4A, it is possible to eliminate a mask alignment margin in a manufacturing process. Eliminating the size of the mask alignment margin can reduce the area of the memory cell M of the DRAM, so that the degree of integration can be improved.

Further, since the potential barrier layer 4B sufficiently diffuses the p-type impurity 4p introduced for forming the channel stopper region 4A by the heat treatment, the potential barrier layer 4B recovers the damage caused by the impurity introduction into the well region 2, and Defects can be reduced. Reducing the crystal defects can improve the refresh characteristics of the DRAM.

When the potential barrier layer 4B is formed on the entire surface of the memory cell M formation region, the well region 2 may not be provided in the memory cell array.

After the step of removing the oxidation-resistant film 26 shown in FIG. 14,
The silicon oxide film 24 on the main surface of the well region 2 and the silicon oxide film 24A on the main surface of the well region 3 are removed to expose the respective main surfaces of the well regions 2 and 3.

Next, a silicon oxide film 6A is formed on each main surface of the exposed well regions 2 and 3. The silicon oxide film 6A is a silicon nitride film, a so-called white ribbon, formed at the end of the inter-element isolation insulating film 5 by the oxidation-resistant film (silicon nitride film) 26 when the inter-element isolation insulating film 5 is formed. Performed to oxidize. The silicon oxide film 6A is formed by steam oxidation at a high temperature of about 900 to 1000 [° C.] and has a thickness of about 400 to 1000 [Å].

Next, an n-channel MISFET of an n-channel MISFET is formed in the element formation region defined by the element isolation insulating film 5 and in each of the main surfaces of the well regions 2 (potential barrier layer 4B in the memory cell array) 3 and the entire substrate. A p-type impurity 27p for adjusting the threshold voltage is introduced. The p-type impurity 27p is 10 ¹¹ [at
oms / cm ² ], and ion implantation with energy of about 30 [KeV].

Next, as shown in FIG. 15, the element formation region defined by the element isolation insulating film 5 and the main surface portion of the well region 3 are selectively used for adjusting the threshold voltage of the p-channel MISFET. Is introduced. The p-type impurity 28p is 10
Using B having an impurity concentration of about ¹² [atoms / cm ² ], 30 [Ke
[V]. The introduction of each of the p-type impurities 27p and 28p for adjusting the threshold voltage can be omitted depending on how the respective impurity concentrations of the well regions 2 and 3 are set.

Next, the silicon oxide film 6A is selectively removed to expose the main surfaces of the well regions 2 and 3, respectively. The silicon oxide film 6A is removed by wet etching.

Next, a gate insulating film 6 is formed on each main surface of the exposed well regions 2 and 3. The gate insulating film 6 has a thickness of 800 to 1
Formed by high temperature steam oxidation of about 000 [℃]
It is formed with a thickness of about 250 [Å].

Next, a polycrystalline silicon film is formed on the entire surface of the substrate including the gate insulating film 6 and the inter-element isolation insulating film 5. The polycrystalline silicon film is deposited by CVD and has a thickness of about 2000 to 3000 [Å]. This polycrystalline silicon film is formed by the first-layer gate wiring forming step in the manufacturing process. After this,
P is introduced into the polycrystalline silicon film by thermal diffusion to reduce the resistance value of the polycrystalline silicon film.

Next, an interlayer insulating film 8 is formed on the entire surface of the polycrystalline silicon film. The interlayer insulating film 8 is formed mainly for electrically separating the polycrystalline silicon film and the conductive layer thereabove. The interlayer insulating film 8 is formed with a thickness of about 3500 to 4500 [Å] using, for example, a silicon oxide film deposited by CVD.

Next, as shown in FIG. 16, the interlayer insulating film 8 and the polycrystalline silicon film are sequentially etched using an etching mask formed of a photoresist film (not shown) to form a gate insulating film 7 and a word line (WL). 7 is formed. Since the interlayer insulating film 8 and the polycrystalline silicon film are cut and overlapped, the interlayer insulating film 8 having the same shape is formed on the gate electrode 7 and the word line 7 respectively.
Remain. In the first-layer gate wiring forming step, the gate electrodes 7 of the MISFETs Qs and the word lines 7 are formed in the memory cell array, and the gate electrodes 7 of the MISFETs Qn and Qs of the peripheral circuit are formed. Although not shown, the first-layer gate wiring forming step is to form a wiring connecting elements and a resistance element. The etching is
Anisotropic etching such as RIE is used. Thereafter, the photoresist film is removed.

Next, in order to reduce contamination due to impurity introduction,
A silicon oxide film (not shown) is formed on each main surface of the exposed well regions 2 and 3 (including the side walls of the gate electrode 7 and the word line 7). The silicon oxide film is, for example, 850 to 950
Formed in an oxygen gas atmosphere at a high temperature of about
It is formed with a film thickness of about 0 to 800 [Å].

Next, an n-type impurity is selectively introduced into the main surface portion of the well region 2 in the memory cell array formation region and the n-channel MISFET Qn formation region using the element isolation insulating film 5 and the interlayer insulating film 8 as an impurity introduction mask. . By introducing the n-type impurity, a low-impurity-concentration n-type semiconductor region 9 that is self-aligned with each of the gate electrode 7 and the word line 7 is formed. The n-type impurity forming the semiconductor region 9 is 10 ¹³ [at
oms / cm ² ], using P (or As) with an impurity concentration of about 60
It is introduced by ion implantation at an energy of about 120 [KeV]. As described above, at least the semiconductor region 9 of the MISFET Qs for selecting the memory cell of the memory cell M which is connected to the information storage capacitance element C has a low impurity concentration of less than 10 ¹⁴ [atoms / cm ² ]. It is composed of Since the semiconductor region 9 is formed with a low impurity concentration, the MISFET Q
Each of s and Qn can be configured with an LDD structure. When the semiconductor region 9 is formed, the p-channel MISFET Qp formation region is covered with an impurity introduction mask formed of a photoresist film. As will be described later, the MISFETQn constituting the CMOS of the peripheral circuit is formed by the semiconductor regions 9 and 10 ¹⁴ [atoms / c.
The source region and the drain region are constituted by the semiconductor region 17 formed by ion implantation with a high impurity concentration of not less than m ² ]. In the step of forming the semiconductor region 9, MISFETs Qs for selecting a memory cell of the memory cell M are substantially completed.

As described above, the information storage capacitive element C having the stacked structure
In the DRAM in which the memory cell M is formed, the one semiconductor region 9 of the MISFETQs of the memory cell M is replaced with the high impurity concentration
As compared with the structure described above, the occurrence of crystal defects on the surface of the well region 2 due to the ion implantation forming the source region or the drain region is reduced by the ion implantation of a lower impurity concentration, and the ion implantation is performed in the information storage capacitor C. Since it is possible to reduce the leakage of electric charges serving as information, the refresh characteristics of the DRAM can be improved. The improvement of the refresh characteristic can increase the information writing operation and the information reading operation speed of the DRAM.

In the MISFETQs of the memory cell M, the channel formation region side is formed of the semiconductor region 9 having a low impurity concentration,
The short channel effect can be suppressed, and the area of the memory cell M can be reduced. That is, the semiconductor region 9 can improve the integration degree of the DRAM.

Moreover, the semiconductor region 9 of the MISFETQs of the memory cell M
By forming in the same manufacturing process as the semiconductor region 9 for forming the LDD structure of the MISFETQn of the CMOS of the peripheral circuit, the MI
Since the step of forming the semiconductor region 9 of the MISFETQn can be used without adding a separate step of implanting the SFETQs with a low impurity concentration, the manufacturing steps of the DRAM can be reduced.

Particularly, in the memory cell M formation region, the potential barrier layer 4B is formed by diffusion of the p-type impurity 4p in the channel stopper region 4A, and the impurity concentration of both is set to 10 ¹⁶ -10
Since it can be set within a low range of about ¹⁷ [atoms / cm ³ ], the pn junction breakdown voltage between the semiconductor region 9 of the MISFETQs and the potential barrier layer 4B or the channel stopper region 4A can be improved. That is, the memory cell M is surrounded by the element isolation insulating film 5 and the channel stopper region 4A.
In AM, at least one semiconductor region of the MISFETQs of the memory cell M (the side connected to the information storage capacitive element C)
9, a channel stopper region is formed on the main surface of the well region 2 below.
By providing the potential barrier layer 4B formed by diffusing the p-type impurity 4p of 4A, it is possible to reduce the trapping of minority carriers by the information storage capacitance element C in the potential barrier layer 4B. The soft error of the cell node can be prevented, and the impurity concentration of the channel stopper region 4A and the impurity concentration of the potential barrier layer 4B are made substantially the same. Since the breakdown voltage of the pn junction with the one semiconductor region 9 can be improved, the leakage of electric charges serving as information of the information storage capacitor C can be reduced, and the information retention characteristics can be improved. The improvement of the information retention characteristic can improve the refresh characteristic of the DRAM and increase the speed of the information writing operation and the information reading operation.

Further, in the DRAM, the potential barrier layer
4B is provided in the main surface portion of the well region 2 under one semiconductor region 9 of the MISFETQs of the memory cell M and under the other semiconductor region 9 (the side connected to the complementary data line 21).
In addition to the above effects, a soft error in the data line mode can be prevented, so that information retention characteristics can be further improved.

Next, after the step of forming the semiconductor region 9, the element isolation insulating film 5 and the interlayer insulating film 8 are used as a mask for introducing impurities, and are selectively formed on the main surface of the well region 3 in the p-channel MISFETQp formation region. A p-type impurity is introduced. This p
By the introduction of the type impurity, a low impurity concentration p-type semiconductor region 10 which is self-aligned with the gate electrode 7 is formed as shown in FIG. The p-type impurity forming the semiconductor region 10 is introduced by ion implantation at an energy of about 60 to 100 [KeV] using BF ₂ (or B) having an impurity concentration of about 10 ¹³ [atoms / cm ² ]. When forming the semiconductor region 10, the memory cell array formation region and the n-channel MISFET Qn formation region are covered with an impurity introduction mask formed of a photoresist film.

Next, although not shown, n which constitutes the input / output circuit of the DRAM
An n-type impurity is introduced at a high impurity concentration into at least a drain region formation region of a channel MISFET (electrostatic breakdown prevention circuit). In the MISFET constituting this input / output circuit, by introducing an additional n-type impurity, an excessive voltage which causes electrostatic breakdown input to the drain region can be easily released to the well region 2 side, and the electrostatic breakdown voltage can be improved. Can be.

Next, as shown in FIG. 18, sidewall spacers 11 are formed on the respective sidewalls of the gate electrode 7 and the word line 7. The sidewall spacer 11 can be formed by performing anisotropic etching such as RIE on a silicon oxide film deposited by CVD. The silicon oxide film is, for example, 3500 to 45
It is formed with a thickness of about 00 [Å]. The length of the side wall spacer 11 in the gate length direction (channel length direction) is 2500 or more.
It is formed at about 4000 [Å]. At this time, if necessary, the region may be limited by a photoresist film and formed by etching.

Next, an interlayer insulating film 12 is formed over the entire surface of the substrate including the interlayer insulating film 8 and the sidewall spacers 11 and the like. The interlayer insulating film 12 is used as an etching stopper when patterning each of the first electrode layer (13) and the second electrode layer (15) constituting the information storage capacitor C having a stacked structure. For this reason, the interlayer insulating film 12 is a film that allows for the amount of shaving due to over-etching during the etching of the first electrode layer and the second electrode layer, the amount of shaving in the cleaning process until the second electrode layer is formed, and the like. It is formed thick. Interlayer insulating film 12
In particular, when patterning the first electrode layer and the second electrode layer, the surface of the other semiconductor region (the side to which the complementary data line 21 is connected) 9 of the MISFETQs for selecting a memory cell is damaged by etching. It is formed so as not to cause it. The interlayer insulating film 12 is, for example, a silicon oxide film deposited at a high temperature of about 700 to 800 [° C.] and by CVD.
It is formed with a film thickness of about 2000 [Å].

Next, as shown in FIG. 19, the interlayer insulating film on one semiconductor region (the side to which the first electrode layer 13 of the information storage capacitor C is connected) 9 of the MISFETQs in the memory cell M formation region 12 is selectively removed to form a connection hole 12A. Connection hole 1
2A is at least a mask alignment margin in the manufacturing process in the column direction, as compared with the size defined by the side wall spacer 11 on the side wall of the gate electrode 7 of the MISFETQs and the side wall spacer 11 on the side wall of the word line 7 adjacent thereto. It is formed with a size corresponding to the size.
That is, the substantial size of the connection hole 12A at which the semiconductor region 9 is exposed by the sidewall spacer 11 is defined.

Next, as shown in FIG. 20, a part is connected to the semiconductor region 9 through the connection hole 12A, and the other part is extended on the gate electrode 7 and the word line 7 with the interlayer insulating films 8 and 12 interposed therebetween. The existing first electrode layer 13 is formed. The first electrode layer 13 forms the lower electrode layer of the information storage capacitance element C having a stacked structure. The first electrode layer 13 is formed larger than the size of the connection hole 12A formed in the interlayer insulating film 12 by at least a size corresponding to a mask alignment margin in a manufacturing process. If the size of the first electrode layer 13 is smaller than the above value compared to the size of the connection hole 12A, the first electrode layer 13
An end of the electrode layer 13 is dropped, and an unnecessary groove is generated between an inner wall of the connection hole 12A and an end side wall of the first electrode layer 13. The portion where the groove is formed is formed thicker than other regions when a photoresist film for patterning the first electrode layer 13 is applied, and causes halation at the time of the phenomenon of the photoresist film,
A shape defect of the first electrode layer 13 occurs.

The first electrode layer 13 is formed of polycrystalline silicon deposited by CVD, and has a thickness of about 800 to 3000 [Å]. In the polycrystalline silicon film, first, a silicon oxide film is formed on a surface, and an n-type impurity for reducing a resistance value is introduced through the silicon oxide film.
After the heat treatment, the silicon oxide film is formed by removing the silicon oxide film. The silicon oxide film is formed by steam oxidation of the surface of the polycrystalline silicon film and has a thickness of about 100 [約]. As the n-type impurity, As or P having an impurity concentration of about 10 ¹⁵ [atoms / cm ² ] is introduced by ion implantation at an energy of about 75 to 85 [KeV]. The patterning of the polycrystalline silicon film is performed by dry etching. When etching the polycrystalline silicon film, the interlayer insulating film 12 is used as an etching stopper layer. The first electrode layer 13 is formed by a second-layer gate wiring forming step.

The first electrode layer (polycrystalline) is formed on the main surface of the well region 2 (actually, the semiconductor region 9) where the first electrode layer 13 and one semiconductor region 9 are connected by the heat treatment after the introduction of the n-type impurity. The n-type impurity introduced into silicon film 13 is diffused. The n ⁺ type semiconductor region 13A having a high impurity concentration by the diffusion
Is formed. The semiconductor region 13A is formed integrally with the semiconductor region 9. The semiconductor region 13A has an MIS for selecting a memory cell.
One of the semiconductor regions of the FETQs is formed, and is mainly configured to improve the ohmic characteristics of the semiconductor region 9 and the first electrode layer 13 (reduction of contact resistance value).

The first electrode layer 13 in the connection hole 12A is
The gate electrode 7 and the word line 7 are electrically separated from each other with the sidewall spacer 11 interposed therebetween.

Next, as shown in FIG. 21, a dielectric film 14 is formed on the entire surface of the substrate including on the first electrode layer 13. As described above, the dielectric film 14 is basically formed in a two-layer structure in which the silicon nitride film 14A and the silicon oxide film 14B are sequentially stacked.

The silicon nitride film 14A is deposited on the first electrode layer (polycrystalline silicon film) 13 by CVD and has a thickness of about 50 to 100 [Å]. When forming the silicon nitride film 14A, entrapment of oxygen is suppressed as much as possible. When a silicon nitride film 14A is formed on a polycrystalline silicon film at a normal production level, a trace amount of oxygen is involved, so that a natural silicon oxide film is formed between the first electrode layer 13 and the silicon nitride film 14A. (Not shown) are formed. Therefore, the dielectric film 14 has a three-layer structure in which a natural silicon oxide film, a silicon nitride film 14A, and a silicon oxide film 14B are sequentially stacked. The natural silicon oxide film can be made thinner by reducing entrapment of oxygen. Although the number of manufacturing steps increases, the natural silicon oxide film may be nitrided, and the dielectric film 14 may be formed in a two-layer structure.

The silicon oxide film 14B is formed by oxidizing the lower silicon nitride film 14A at a high pressure to a thickness of about 10 to 60 [Å]. When the silicon oxide film 14B is formed, the silicon nitride film 14A is slightly consumed.
The silicon nitride film 14A is finally formed with a thickness of about 40 to 80 [Å]. The silicon oxide film 14B basically has a thickness of 1.5 to 10 [tol
l] and an oxygen gas atmosphere at a high temperature of about 800 to 1000 [° C.]. In this embodiment, the silicon oxide film 14B has a high pressure of 3 to 3.8 [toll] and an oxygen flow rate (source gas) of 2 [l / min] and a hydrogen flow rate (source gas) of 3 to 8 [tol] during oxidation. l / min]. As shown in FIG. 28 (a diagram showing the oxidation characteristics of the silicon nitride film), the silicon oxide film 14B formed by high-pressure oxidation has a normal pressure (1 [tol).
1) It can be formed to a desired film thickness in a shorter time than the silicon oxide film formed in the above. FIG. 28 shows the oxidation time [min] on the horizontal axis and the thickness of each oxide film [Å] on the silicon nitride film (Si ₃ N ₄ ) on the vertical axis. In other words, high-pressure oxidation can shorten the time of heat treatment at a high temperature and can form a high-quality dielectric film. The reduction of the oxidation time can reduce the depth of the pn junction of the source region and the drain region of the MISFETs Qs, Qn, and Qp, so that the MISFET can be miniaturized.

As described above, the information storage capacitive element C having the stacked structure
The first electrode layer 13 of the information storage capacitor C is formed of a polycrystalline silicon film into which an impurity for reducing the resistance value is introduced, and the dielectric film 14 is formed on the first electrode layer 13. By forming the silicon nitride film 14A deposited and the silicon oxide film 14B formed on the silicon nitride film 14A by subjecting the surface thereof to high-pressure oxidation, the crystal state of the surface of the underlying first electrode layer 13 is formed. Silicon nitride film 14A with a uniform thickness regardless of the shape and shape
And a high quality silicon oxide film 1 is formed on the silicon nitride film 14A.
Since 4B can be formed, the dielectric strength of the dielectric film 14 can be improved, the number of defects per unit area of the dielectric film 14 can be reduced, and the leakage current of the dielectric film 14 can be reduced. Since the time for forming the silicon oxide film 14B can be reduced, the element can be miniaturized and the degree of integration can be improved.

The dielectric film 14 of the information storage capacitor C having a stacked structure has a four-layer structure in which a natural silicon oxide film, a silicon nitride film 14A, a silicon oxide film 14B, and a silicon nitride film are sequentially stacked thereon. Is also good. When the upper electrode layer (15) is a negative electrode, a larger amount of current flows than in the case of a positive electrode, and thus the initial dielectric breakdown voltage of the three-layer dielectric film 14 is low. The dielectric film 14 having a four-layer structure is composed of a silicon oxide film 14B and an upper electrode layer (15).
And a silicon nitride film can be provided between them to improve the initial withstand voltage.

Next, a second electrode layer (15) is formed on the entire surface of the dielectric film 14.
Is formed. The polycrystalline silicon film
It is deposited by CVD and formed to a thickness of about 1500 to 2500 [Å]. This polycrystalline silicon film is formed by a third-layer gate wiring forming step in the manufacturing process.

Next, an n-type impurity for reducing the resistance value is introduced into the polycrystalline silicon film. The n-type impurity is introduced into the polycrystalline silicon film by thermal diffusion using phosphorus. The n-type impurity is introduced so that the specific resistance value of the polycrystalline silicon film becomes about 20 to 100 [Ω / □].

Next, a photoresist film is applied on the entire surface of the polycrystalline silicon film. After that, using photolithography technology,
The second electrode layer (1) of the information storage capacitive element C of the memory cell M
5) An etching mask 29 (shown by a dotted line) is formed while leaving the photoresist film on the formation region.

Next, the second electrode layer 15 is formed by etching the polycrystalline silicon film using the etching mask 29. This etching uses plasma etching. Thereafter, as shown in FIG. 22, the exposed dielectric film 14 and the underlying interlayer insulating film 12 are sequentially etched using the etching mask 29 (or the second electrode layer 15). This etching uses dry etching. The dielectric film 14 is formed so as to have substantially the same shape as the shape of the second electrode layer 15, and is formed so as to exist only under the second electrode layer 15. On the other semiconductor region 9 (the side to which the complementary data line 21 is connected) 9 of the MISFETQs of the memory cell M and the MISFETQn of the peripheral circuit,
The dielectric film 14 and the interlayer insulating film 12 on the respective Qp formation regions are removed by the etching.

Through the step of forming the second electrode layer 15, the information storage capacitance element C having the stacked structure of the memory cell M is substantially completed. At the same time, the memory cell M is substantially completed.

As described above, the information storage capacitive element C having the stacked structure
In the DRAM in which the memory cell M is formed, the information storage capacitor C having the stacked structure is connected to the first electrode layer 13 connected to one semiconductor region 9 of the MISFETQs, and the first electrode layer
A second electrode layer 15 provided on the first electrode layer 13 so as to cover the second electrode layer 13; and a second electrode layer 15 having substantially the same shape as the second electrode layer 15 provided between the first electrode layer 13 and the second electrode layer 15. By constituting with the dielectric film 14, the dielectric film 14 is covered with the second electrode layer 15, and the electric charge is stored in the dielectric film 14 in a step of patterning the second electrode layer 15 or a subsequent step. Since accumulation (charge-up) can be reduced, it is possible to prevent deterioration of the dielectric strength (characteristic) of the dielectric film 14 due to the accumulation of the charges. The prevention of deterioration of the dielectric strength of the dielectric film 14 can improve the electrical reliability of the DRAM.

In a DRAM in which a memory cell M is formed by a stacked information storage capacitor C, an MISFETQs for selecting a memory cell is formed, and an interlayer insulating film 12 covering the MISFETQs is formed.
Is selectively removed from the interlayer insulating film 12 on the one semiconductor region 9 of the MISFET Qs, a connection hole 12A exposing the one semiconductor region 9 is formed, and the one connection hole 12A is exposed through the connection hole 12A. First electrode layer 13 of information storage capacitor C having a stacked structure, connected to semiconductor region 9 and extending on gate electrode 7 of MISFETQs with insulating film 12 interposed therebetween.
Is formed, and a dielectric film 14 is formed on the first electrode layer 13;
A second electrode layer 15 covering the first electrode layer 13 is formed on the first electrode layer 13 with the dielectric film 14 interposed therebetween, and the second electrode layer 15
Alternatively, using a mask 29 for patterning the
By removing at least the interlayer insulating film 12 on the other semiconductor region 9 of the SFET Qs, the interlayer insulating film 12 on the other semiconductor region 9 connected to the complementary data line (21) of the MISFET is removed. The mask is the second electrode layer 12 or the mask
29 can also be used, so that a mask forming step for removing the interlayer insulating film 12 can be reduced.

Further, since the removal of the interlayer insulating film 12 on the other semiconductor region 9 of the MISFETQs can be performed by self-alignment with the second electrode layer 12 because the same mask is used, it corresponds to the mask alignment margin in the manufacturing process. Accordingly, the area of the memory cell M can be reduced. As a result, the degree of integration of the DRAM can be improved.

Next, an insulating film 16 is formed on the entire surface of the substrate. The insulating film 16
It is formed on at least the semiconductor regions 9 and 10 which are the CMOS formation region of the peripheral circuit and are on the source region and the drain region. The insulating film 16 is formed of, for example, a silicon oxide film deposited by CVD and has a thickness of about 300 [Å].

Next, an n-channel MISFETQn constituting the CMOS of the peripheral circuit
In the formation region, n is selectively added to the main surface of the well region 2.
Introduce type impurities. The introduction of the n-type impurity is mainly performed using the gate electrode 7 and the interlayer insulating film 8 as an impurity introduction mask in a state where the memory cell M formation region and the p-channel MISFET Qp formation region are covered with the photoresist film. The n-type impurity has an impurity concentration of, for example, about 10 ¹⁵ [atoms / cm ² ].
Using s, ions are implanted at an energy of about 70 to 90 [KeV].

Next, the p-channel MISFETQp
In the formation region, p is selectively added to the main surface of the well region 3.
Introduce type impurities.

The introduction of the p-type impurity is performed mainly using the gate electrode 7 and the interlayer insulating film 8 as an impurity introduction mask in a state where the memory cell M formation region and the n-channel MISFETQn formation region are covered with the photoresist film. The p-type impurity is, for example, 10 ¹⁵
Using BF ₂ having an impurity concentration of about [atoms / cm ² ],
It is introduced by ion implantation with energy of about [KeV].

Thereafter, the n-type impurity and the p-type impurity are extended and diffused, and as shown in FIG. 23, the n ⁺ -type semiconductor region 17 is formed on the main surface of the well region 2 and the p ⁺ Each of the type semiconductor regions 18 is formed. The stretch diffusion is 900
Perform at about 10 [min] at a high temperature of about 1000 [° C]. The MISFETQn is substantially completed by the process of forming the semiconductor region 17, and the MISFETQp is substantially completed by the process of forming the semiconductor region 18.

Next, an interlayer insulating film 19 is formed on the entire surface of the substrate. The interlayer insulating film 19 has a two-layer structure in which a silicon oxide film 19A deposited by CVD and a silicon oxide film (BPSG) 19B deposited by CVD capable of glass flow are sequentially laminated.

The lower silicon oxide film 19A prevents each of B and P contained in the silicon oxide film 19B from leaking to the lower element, and reduces the withstand voltage of the portion where the silicon oxide film 19B is thinned by glass flow. Formed to secure. Silicon oxide film 19A
Is formed with a thickness of, for example, about 500 to 2000 [Å].

The upper silicon oxide film 19B is formed in order to flatten the surface thereof and improve the step coverage of the upper wiring (21). The silicon oxide film 19B is formed with a thickness of, for example, about 3000 to 7000 [Å].

Next, a glass flow is applied to the upper silicon oxide film 19B of the interlayer insulating film 19 to flatten the surface. The glass flow is performed in a nitrogen gas atmosphere at a high temperature of, for example, about 900 to 1000 [° C.].

Next, the upper portions of the semiconductor regions 9, 17, and 18, the upper portions of the word lines 7 (not shown), and the upper portions (not shown) of the second electrode layers 15 (not shown) are selectively removed, and the connection is performed. A hole 19C is formed. The connection hole 19C is formed by performing wet etching on the upper part of the interlayer insulating film 19 and anisotropic etching such as RIE on the lower part. This connection hole 19C is
9 has a tapered shape in which the upper opening size is large and the lower opening size is small, so that disconnection of the upper layer wiring (21) can be prevented. Further, the connection hole 19C may be formed only by anisotropic etching.

Next, a silicon oxide film 30 is formed on the silicon surface such as the semiconductor region 9 exposed from the connection hole 19C. Silicon oxide film 30
Is that B or P of the silicon oxide film 19B of the interlayer insulating film 19 is introduced into the main surface portion of the semiconductor region 9 or the like through the connection hole 19C by a heat treatment (extension diffusion of impurities forming the semiconductor region 20) in a later step. It is formed to prevent that. When B is introduced into the n-type semiconductor regions 9 and 17 or P is introduced into the p-type semiconductor region 18, the effective impurity concentration decreases, and each semiconductor region and the wiring connected thereto become Contact resistance increases. The silicon oxide film 30 is formed as a thin film of about 120 to 300 [Å].

Next, the MISFETQs for memory cell selection and the n-channel MI
In the SFET Qn formation region, an n-type impurity is selectively introduced into the main surfaces of the semiconductor regions 9 and 17 through the connection holes 19C. The n-type impurities pass through the silicon oxide film 30. Then, the n-type impurity is stretched and diffused to form an n ⁺ -type semiconductor region 20 having a high impurity concentration, as shown in FIG. The semiconductor region 20 prevents a short circuit between the wiring (21) passed through the connection hole 19C and the well region 2 when the semiconductor region 9 or 17 is displaced from the connection hole 19C due to a mask misalignment in a manufacturing process. It is formed to be. The n-type impurity forming the semiconductor region 20 is, for example, 10 ¹⁵ [atoms /
cm ² ] and high impurity concentration of about 110 to 130 [KeV]
It is introduced by ion implantation of about energy. The semiconductor region 20 is formed integrally with the other semiconductor region 9 of the MISFETQs in the memory cell M, and forms a part of the source region or the drain region. Since the semiconductor region 20 is formed by ion implantation with a high impurity concentration, the contact resistance with the complementary data line (21) can be reduced.

Next, as shown in FIG. 25, a wiring 21 is formed which is connected to each of the semiconductor regions 9, 17, 18 and the like through the connection hole 19C and extends on the interlayer insulating film 19. The wiring 21 is formed by a first-layer wiring forming step, and forms the complementary data line 21, the Y select signal line 21, and the like as described above. Wiring 21 is
It has a three-layer structure in which a barrier metal film 21A, an aluminum film 21B, and a protective film 21C are sequentially laminated. This wiring 21
Is patterned using anisotropic etching such as RIE.

The barrier metal film 21A is formed to a thickness of about 100 to 200 [Å] using MoSi ₂ deposited by sputtering. The barrier metal film 21A is formed on the entire surface under the aluminum film 21B, and Mo can be introduced into the aluminum film 21B. Therefore, growth of aluminum crystal grains can be suppressed, and stress migration can be reduced.

The aluminum film 21B contains additives of Cu and Si. The aluminum film 21B is deposited by sputtering,
It is formed with a film thickness of about 0 to 6000 [Å].

The protective film 21C is made of MoSi _x (x = 0 <X <1.2),
It is formed with a thickness of about 1000 [Å]. This protective film 21C
As described above, is formed to protect the surface of the aluminum film 21B from the liquid used in the wet processing when forming the wiring 21.

Each layer of the wiring 21 is formed by a sputtering device 50 shown in FIG. 29 (schematic diagram of the sputtering device). As shown in FIG. 29, the sputter device 50 mainly includes a single loader chamber 51, a twin loader chamber 52, a cleaning chamber 53, and a sputter chamber.

The single loader chamber 51 is configured to sequentially supply a plurality of wafers 55A stored in a cassette 55 to a cleaning chamber 53 and a sputtering chamber 54 via a wafer transport belt 56. The cassette 55 is configured to hold a plurality of wafers 55A in an upright state. The cassette 55 is transported by the elevator device 51A to a supply position of the wafer 55A. At this position, the plane of the wafer 55A coincides with the transport direction and the wafer 55A
Is set up so that the supply of water can be performed smoothly. The single loader chamber 51 is used in combination with the twin loader chamber 52 when performing continuous processing.

The twin loader chamber 52 is configured to supply the wafer 55A to the cleaning chamber 53 and the sputtering chamber 54 and to store the processed wafer 55A. Although the cassette 55 is not shown, the cassette 55 accommodating the supply wafer 55A is configured to be transported by the elevator device 52A. Treated wafer 55
The cassette 55 in which A is stored is configured to be transported by the elevator device 52B.

The cleaning chamber 53 includes a twin loader chamber 52.
The wafer 55A transported by the wafer transport belt 56 from above is held by a quartz arm 53A, and is rotated in the direction of the arrow. Four quartz arms 53A are arranged every 90 degrees, and the four quartz arms 53A are configured to rotate on the same rotation axis. The surface of the wafer 55A held by the quartz arm 53A is cleaned in opposition to the sputter etching electrode 53B, or the wafer is preheated.
Heated by 53C. The quartz arm 53A is configured to hold the processed wafer 55A transported from the sputtering chamber 54 by the wafer transport belt 56 and transport the processed wafer 55A to the twin loader chamber 52.

The sputtering chamber 54 is provided with a wafer holder 54A that can hold the wafer 55A in an upright state. The four wafer holders 54A are arranged every 90 degrees similarly to the quartz arm 53A.
A is configured to rotate on the same rotation axis. Except for the wafer holder 54A located on the wafer transfer belt 56, the sputtering unit 54 is located at a position facing each surface (holding surface of the wafer 55A) of the other three wafer holders 54A.
Each of I, 54II, and 54III is provided. A heater 54B is arranged on the back side of each of the three wafer holders 54A.

Each sputtering unit 54I, 54II, 54III is a wafer holder 54
From the A side, a shield plate 54C, a shutter 54D, a target case 54E, a target 54F, a magnet 54G, and a target rotating device 54H are sequentially provided. Sputter part 5
4I target 54F is composed of MoSi _2. The target F of the sputtering unit 54II is made of Al-Cu-Si.
The target F of the sputtering unit 54III is made of MoSi _x . That is, in the sputtering chamber 54, in the same vacuum system (in the same chamber), the barrier metal film 21A, the aluminum film 21B, and the protective film 21C are sequentially and sequentially stacked on the wafer 55A, that is, on the interlayer insulating film 19 of the DRAM. be able to.

Aluminum film 21B of wiring 21 (lower metal wiring)
DRAM on which protective film 21C (upper metal wiring) is directly laminated
In the aluminum film by sputtering in a vacuum system
21B is formed, and then an aluminum film 2 is formed in the same vacuum system.
By continuously forming the protective film 21C by sputtering on 1B, the generation of aluminum oxide on the surface of the aluminum film 21B can be reduced,
The specific resistance of the wiring 21 formed by the aluminum film 21B and the protective film 21C can be reduced. Reducing the specific resistance value of the wiring 21 can increase the operating speed of the DRAM.

The wiring 21 mainly composed of the aluminum film 21B to which the element (Cu or the like) for reducing migration is added forms an aluminum film 21B to which the above-mentioned element is added, and the aluminum film 21B is wet-processed on the aluminum film 21B. Forming a protective film 21C to protect from the liquid used, this protective film 21C
An etching mask (not shown, an etching mask for the wiring 21) is formed thereon, and using the etching mask, the protective film 21C and the aluminum film 21B are etched into a predetermined shape. By performing the wet treatment for removal, it is possible to prevent a reaction of a battery composed of the aluminum film 21B and the intermetallic compound formed of aluminum and the element during the etching or the wet treatment. Therefore, it is possible to prevent the aluminum film 21 from being damaged due to the battery reaction. As a result, the wiring 21 can reduce shape defects, prevent disconnection, or reduce migration.

After the step of forming the wiring 21 shown in FIG.
An interlayer insulating film 22 is formed on the entire surface of the substrate including on the substrate 21. The interlayer insulating film 22 has a three-layer structure as described above.

The lower silicon oxide film 22A is formed with a thickness of about 1000 to 2000 [Å].

The silicon oxide film 22B of the intermediate layer is formed to flatten the surface. The silicon oxide film 22B is deposited several times (2 to 5 times).
Times) (apply with a film thickness of about 1000 to 2000 [Å])
And a baking process (about 450 [° C.]) and a dense film. Further, the silicon oxide film 22B may be formed with a high quality film by sequentially increasing the temperature of the baking process.

The upper silicon oxide film 22C is formed to increase the strength of the film as the whole interlayer insulating film 22. The silicon oxide film 22C has 4
It is formed with a thickness of about 000 to 7000 [Å].

Next, as shown in FIG. 26, a connection hole 22D is formed in the interlayer insulating film 22. The connection hole 22D is formed in a stepped cross section by a resist retreating method using a multilayer photoresist film (etching mask) and anisotropic etching such as RIE.
Thereafter, a heat treatment at about 400 ° C. is performed to recover damage due to etching.

Next, as shown in FIG. 2 and FIG.
A wiring 23 formed by a second-layer wiring forming step extending on the interlayer insulating film 22 is formed so as to be connected to the wiring 21 through D. The wiring 23 is, as described above,
A and an aluminum film 23B are sequentially laminated to form a two-layer structure.

The lower underlying film 23A is made of MoSi ₂ deposited by sputtering.
And formed with a film thickness of about 100 to 1000 [Å].

The upper aluminum film 23B is deposited by sputtering,
7000 to 120 thicker than the aluminum film 21B of the wiring 21
It is formed with a thickness of about 00 [Å]. Aluminum film 23B
As in the aluminum film 21B, Cu and Si are added in the same amounts, respectively.

Thus, elements that reduce migration (Cu)
Aluminum film 21B of wiring 21 to which is added, and aluminum film 21B through connection hole 22D formed in interlayer insulating film 22.
The content of silicon is greater than 0 and less than 2 (the optimal value is 0
By providing a protective film 21C (higher melting point metal silicide film, MoSi _x in the present embodiment) of greater than 1.2), particles of the aluminum film 21B of the wiring 21 pass through the protective film 21C and the protective film 21C and the aluminum film 23B. Can be prevented from forming at the interface with the aluminum film and forming an aluminum oxide, so that the contact resistance value between the aluminum film 21B and the aluminum film 23B can be reduced. As a result, the yield at the connection between the wirings 21 and 23 can be improved.

Further, since the contact resistance value between the wirings 21 and 23 can be reduced, the signal transmission speed can be increased, and the operation speed of the DRAM can be increased.

After the step of forming the wiring 23, heat treatment is performed to recover damage due to etching (anisotropic etching) for forming the wiring 23.

Next, a passivation film (not shown) is formed on the entire surface of the substrate including the wiring 23.

By performing these series of steps, the DRAM of this embodiment is
Is almost completed.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Of course.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

In a semiconductor integrated circuit device having a DRAM, the refresh characteristics can be improved, so that the operation speed can be increased.

[Brief description of the drawings]

1 is an equivalent circuit diagram of a main part of a DRAM according to an embodiment of the present invention. FIG. 2 is a plan view of a main part of a memory cell array of the DRAM. FIG. 3 is a memory cell array and peripheral circuits of the DRAM. FIGS. 4 and 5 are plan views of main parts in a predetermined manufacturing process of the memory cell array. FIGS. 6 to 8 are diagrams showing Auger electron spectroscopy of wiring compositions used in DRAM. 9 to 26 are cross-sectional views of a main part showing a memory cell array and a peripheral circuit of the DRAM in each manufacturing process, and FIG. 27 is a diagram showing a space between elements of the DRAM. FIG. 28 is a diagram showing an impurity concentration distribution of a channel stopper region for isolating the above, FIG. 28 is a diagram showing an oxidation characteristic of a silicon nitride film constituting a dielectric film of the information storage capacitor element of the DRAM, FIG. FIG. 2 is a schematic configuration diagram of a sputtering apparatus for forming a wiring used in a DRAM. In the figure, M: memory cell, Qs: MISFE for selecting memory cell
T, Qn, Qp: MISFET, C: Capacitance element for storing information, WL: Word line, DL: Complementary data line, YSL: Y select signal line, 4
A: channel stopper region, 4B: potential barrier layer, 7: gate electrode or word line, 9, 10, 13A, 17, 18, 20
... Semiconductor region, 12 ... Interlayer insulating film, 12A ... Connection hole, 13 ... First electrode layer, 14 ... Dielectric film, 14A ... Silicon nitride film, 14B ... Silicon oxide film, 15 ... Second electrode layer, 21,23 ... wiring, 21A ... barrier metal film, 21B, 23B ... aluminum film, 21C ... protective film, 23A
... Underlayer film, 50. Sputtering apparatus.

Claims (4)

(57) [Claims] 1. A method of manufacturing a semiconductor integrated circuit device comprising a memory cell including a memory cell selecting MISFET having an LDD structure and a capacitor connected in series to one semiconductor region of the memory cell selecting MISFET. Forming a gate electrode of the memory cell selecting MISFET on a semiconductor substrate via a gate insulating film; and performing ion implantation in a self-aligned manner with respect to the gate electrode of the memory cell selecting MISFET. Forming a semiconductor region having a low impurity concentration constituting the semiconductor region of the memory cell selecting MISFET, and connecting the polycrystalline silicon film doped with the impurity to the semiconductor region of the memory cell selecting MISFET. Forming one electrode of the capacitor by patterning the polycrystalline silicon film; and forming the capacitor of the memory cell selecting MISFET. Forming a semiconductor region having a high impurity concentration in a semiconductor region to which one electrode of the element is connected by thermal diffusion from one electrode of the capacitive element. Method. 2. The method according to claim 1, wherein the step of forming one electrode of the capacitive element is a step of forming an electrode below the capacitive element formed in a stacked structure. Of manufacturing a semiconductor integrated circuit device. 3. The method according to claim 1, further comprising the step of forming a semiconductor region having a high impurity concentration by performing ion implantation in a semiconductor region of the memory cell selection MISFET to which the capacitance element is not connected. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein 4. The semiconductor integrated circuit device further comprises a peripheral circuit MISFET constituting a peripheral circuit, and the peripheral circuit MISFET is formed by ion implantation for forming the low impurity concentration semiconductor region of the memory cell selecting MISFET. MISF
A low impurity concentration semiconductor region constituting a semiconductor region of the ET is formed, and ion implantation is performed in a self-aligned manner with respect to a sidewall spacer formed on a side surface of the gate electrode of the MISFET for the peripheral circuit, thereby forming the peripheral region. 4. The semiconductor device according to claim 1, wherein a semiconductor region having a high impurity concentration forming a semiconductor region of the circuit MISFET is formed.
13. A method for manufacturing a semiconductor integrated circuit device according to any one of the above items.