JP2614358B2 - Block read address generation system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Overview Industrial application field Conventional technology (FIGS. 4 to 6) Problems to be solved by the invention Means for solving the problem (FIG. 1) Embodiment (FIGS. 2 and 3) Effect of the Invention [Outline] Regarding a block read address generation system using a common address portion generation means in a write release stage, the number of counters required for block read and write For the purpose of releasing the association with the number of release stages and reducing the delay in the address part generation unit, when reading from the cache memory by the processor, one address buffer having a predetermined set order among a plurality of address buffers is used. A read address is set, and when there is a mishit in reading by the read address, the read address is set. In the information processing apparatus which sends out the address of the address buffer to the memory bus and performs block read, the separation of the address generation start address portion from the block read start address of the selected address buffer and the separation for outputting the block read start address An output circuit, an address portion generation circuit for generating and outputting a sequential address portion from the address portion, and outputting a block read start address, and replacing the address portion from the address portion generation means with the address generation start address portion. And an output circuit for outputting the output of the memory bus to the memory bus.

[Industrial applications]

The present invention relates to a block read address generation system that uses an address portion generation unit common to each write release stage for generating a block read access address in a system having a write release function.

In an information processing system, a write release processing is used for high-speed writing of data used for processing, and whether or not the system has the write release function in order to read data used for processing at high speed. Regardless, there is an information processing system using a cache memory.

[Conventional technology]

FIG. 4 shows an example of a block read control circuit that is required when a mishit occurs in a cache memory in an information processing system that also has a write release function in a conventional information processing system using a cache memory. . FIG. 4 shows the information processing system shown in FIG.
It mainly shows the overall configuration of the storage system. It is assumed that the address used in this system is 32 bits, the memory bus can be accessed by 4 bytes, one block of the cache memory is 16 bytes, the write-through method is used, and the number of write-through stages is 4.

In this information processing system, when the processor 20 wants to access the cache memory 22, it sends the access request to the access control unit 27, and if the access request is possible, the processor 20 gives the access permission to the processor 20.
Return to In the access permission, there is no hit information from the directory section 24 via the hit notification line 25, and the flip-flop circuit 38, the flip-flop circuit 40, the flip-flop circuit 42, and the flip-flop circuit 44 are all set (set state). (A set state notification signal is supplied to the access control unit 27 via the notification line 56, the set state notification line 58, the set state notification line 60, and the set state notification line 62.)
Occurs when. Access control unit 27, flip-flop circuit 38, flip-flop circuit 40, flip-flop circuit
42, flip-flop circuit 44, counter 46, counter 48,
The counter 50, the counter 52, and the multiplexer 54 are provided in the address control LSI 26 of FIG.

In the above access, a bus request may be required.The bus request is sent to a bus use permission circuit in another processor board 30 via a bus request line 29 of the memory bus 28, and a bus permission is issued therefrom. receive. This bus permission is determined, for example, based on the priority (priority) assigned to the bus request, and the bus request from the bus request unit having a higher priority than the bus request from the access control unit 27 already has the bus request. When the bus permission is issued to the permission circuit, the bus permission is not output. When the bus request issued to the bus use permission circuit is lower than the bus request from the access control unit 27, the bus permission is output.

In the processing in the processor 20, when it becomes necessary to read data from the cache memory 22, when the processor 20 issues a read access request to the cache memory 22, hit information is read from the directory unit 24 for the read address. If not output, a bus request is sent from the access control unit 27 to the bus request line of the memory bus 28.
When the access control section 27 receives the bus permission via the bus permission line 31 via the bus permission circuit via the bus 29 (return of the bus permission is as described above), the access control section. Under the control of 27, the process of reading the mishit block (a data group consisting of a fixed number of access data units (for example, 16 bytes as described above)) from the main memory 32 of the memory board to the cache memory 22 is performed. Can be FIG. 5 shows a circuit for generating an address necessary for performing the block read.

The flip-flop circuit 38, the flip-flop circuit 40, the flip-flop circuit 42, and the flip-flop circuit 44 shown in this drawing are used not only for the above-described write-throw processing, but also for reading from the cache memory.

In flip-flop processing, flip-flop circuit
38, flip-flop circuit 40, flip-flop circuit 42,
The processor 20 issues a write instruction to the flip-flop circuit 44.
When the write instruction is continuous on the program as shown in FIG.
Access requests are continuously transmitted to the access request line 27 via the access request line 21. When the access permission for those access requests is received via the access permission line 23, the address for each write instruction is stored in the flip-flop circuit 38, the flip-flop circuit 40, the flip-flop circuit 42, the flip-flop circuit 44, and the counter 46, Counter 48, counter 5
0, counter 52 [part of the address (address part for generating each of the addresses used in block read described later)]
Set only. ], While receiving the bus permission via the bus permission line 31 for the bus request transmitted via the bus request line 29 (obtaining the right to access the bus) in the same manner as described above, The address written to the flip-flop circuit 38, the flip-flop circuit 40, the flip-flop circuit 42, and the flip-flop circuit 44 via the multiplexer 54 and the address transferred from the address bus (or address time slot) of the memory bus 28. Are sequentially written to the storage locations of the main memory 32 of the memory board designated by. The same write completion notification processing as in the case where there is no write release processing for each write (refer to FIG. 6) to the main memory 32 of the memory board is executed by a program as shown in FIG. This is done later on. The buffer in FIG. 6 shows the flip-flop circuit 38, the flip-flop circuit 40, the flip-flop circuit 42, and the flip-flop circuit 44 in FIG.

The flip-flop circuit 38, the flip-flop circuit 40, the flip-flop circuit 42, the flip-flop circuit 44, and the counter 46, the counter 48, the counter 50, and the counter 52 which are used for such a write-throw processing are provided by the processor 20 as a cache memory. Also used for read access to 22. The read address is set in the flip-flop circuit 38, the flip-flop circuit 40, the flip-flop circuit 42, the flip-flop circuit 44, and one of the counters 46, 48, 50 and 52. For the next read, the flip-flop circuit 38 and the flip-flop circuit 4 are arranged in such an order that the next flip-flop circuit is used.
0, flip-flop circuit 42, flip-flop circuit 44,
One of the counters 46, 48, 50 and 52 is set by the FF set signal FFSET sequentially output from the access control unit 27. The address set in the flip-flop circuit is used to read data required by the processor 20 from the cache memory 22, and a hit indicating that data corresponding to the address to be read is stored. When information is being transferred from the directory section 24 to the access control section 27 via the hit notification line 25, the processor 20 sends the information to the internal address bus.
The read address sent to the cache memory 22 and applied to the address input of the cache memory 22 is used for reading from the cache memory 22. Cache memory 22
Is transferred to the processor 20 via the internal data bus 37.

However, when hit information indicating that data corresponding to the address to be read is stored has not been transferred from the directory unit 24 to the access control unit 27 via the hit notification line 25, the block containing the data is read. Reading is performed from the main memory 32 of the memory board to the cache memory 22 via the memory bus 28 and the data control LSI 34 under the control of the access control unit 27 as follows.

For example, if a mishit occurs for the read address set in the flip-flop circuit 38 and the counter 46, the head address for performing the block read for the mishit is the flip-flop circuit 38.
From the counter 46 to the main memory 32 of the memory board via the multiplexer 54 and the address bus of the memory bus 28 to the main memory 32 of the memory board. Is read, and the data is written to the read address set in the flip-flop circuit 38 and the counter 46 of the cache memory 22 under the control of the processor 20 via the data bus of the memory bus 28 and the data control LSI 34. . As for the next address for block read, the value counted up by the counter 46 by the count-up signal CNTUP is supplied to the main memory 32 of the memory board via the memory bus 28, and the relevant address is set in the same manner as described above. The next data in the block is read from the main memory 32 of the memory board, the memory bus 28, the data control LSI 3
4 through the cache memory 22 under the control of the processor 20
Is written next to the read address. Hereinafter, similarly, each data of the block is read from the main memory 32 of the memory board and sequentially written to the cache memory 22, so that the block read for the mishit can be performed.

Such a block read relationship is the same for each of the flip-flop circuit and counter sets.

[Problems to be solved by the invention]

As described above, it is necessary to provide a set of the flip-flop circuits and the counters for the number of processing stages for the write release processing. In this case, not only a counter for the number of stages is required, but also as described above. In the case of a cache miss, each time the counter is incremented, the incremented address portion passes through the multiplexer 54, so that an address generation delay occurs. If the number of increments is large, the access speed is reduced.

The present invention has been made in view of such a technical problem, and reduces the number of counters required for block read to a number smaller than the number of write-release stages irrespective of the number of write-release stages. It is an object of the present invention to provide a block read address generation system capable of reducing a delay generated at the output of each address generation part.

[Means for solving the problem]

FIG. 1 is a block diagram showing the principle of the first and second aspects of the present invention. As shown in FIG. 1A, when the processor 1 reads data from the cache memory 2, one of the plurality of address buffers 3 in a predetermined set order is read out from the cache memory 2. When the directory unit 4 indicates a mishit for reading by the read address, the selection circuit 6 selects the address buffer in which the read address is set under the control of the access control unit 5, Send to memory bus 8 for storage
An information processing apparatus that performs block reading from 10 is provided with the following components. The constituent elements include a separation output circuit 12 for separating an address generation start address portion for block reading from the block read start address of the selected address buffer and outputting the block read start address, and the separation output circuit. An address portion generation circuit 14 that generates and outputs a sequential address portion from an address generation start address portion separated from 12;
The output of the block read start address from the separation output circuit 12, and the output obtained by replacing the address part from the address part generation circuit 12 with the address generation start address part of the output block read start address. The output control circuit 5 is configured to control the separated output circuit 12, the address part generation circuit 14, and the output circuit 16 to the memory bus 8. The related invention consists.

As shown in FIG. 1B, when the processor 1 reads data from the cache memory 2, one address buffer in a predetermined set order among the plurality of address buffers 3 is used. When the directory unit 4 indicates a mishit for reading by the read address, the address buffer in which the read address is set is stored in the first selection circuit 6 under the control of the access control unit 5.
The information processing device which selects the data and sends the data to the memory bus 8 to perform block read from the storage device 10 is provided with the following components. The constituent elements are a transfer path 13 for transferring an address portion other than the address generation start address portion for block read from the address of the selected address buffer, a first input for receiving the address generation start address portion, A second selection circuit 15 for providing an alternative output to a second input for receiving the generated address portion
An output circuit 17 that combines the address portion from the transfer path 13 and the address portion from the second selection circuit 15 and outputs the combined address to the memory bus 8 as an address for the block read; An address portion generation circuit 14 that generates a sequential address portion from the address portion output from the second selection circuit 15 and outputs the generated address portion to the second input;
Among these components, a second selection circuit 15 and an output circuit
The invention according to claim 2 is constituted by configuring the access control unit 5 so as to control the address part generation circuit 14 and the address part generation circuit 14.

(Operation)

When the processor 1 reads from the cache memory 2 that the data corresponding to the read address is not stored in the cache memory 2 from the directory unit 4, the address output via the first selection circuit 6 is indicated. The transmission of the buffer address, that is, the head address of the block read, onto the memory bus 8 is performed according to the invention according to the first aspect, the separation output circuit 12 and the output circuit 16, and the second aspect. In
The data is sent out onto the memory bus 8 via the transfer path 13, the second selection circuit 15, and the output circuit 17, and the head data of the block is read from the storage device and the
Is stored in

The addresses of the sequential read data in the block are sequentially transmitted onto the memory bus 8 as follows.

The transmission of these addresses in the invention according to claim 1 is performed by the address part generation circuit 14 and the output circuit 16.
The transmission of those addresses in the invention according to claim 2 is performed by the address part generation circuit 14, the second
Is performed by the selection circuit 15 and the output circuit 17.

Address part generation circuit required for block read
14, one less than the number of address buffers is enough,
This simplifies the hardware. In addition, since the address portion having a small number of bits may be output by the second selection circuit 15 for transmitting the block read address, the second selection circuit 15
And the signal propagation time is short, which contributes to speeding up of block reading.

〔Example〕

FIG. 2 shows an embodiment of the first and second aspects of the present invention. The system configuration of this embodiment is the same as that shown in FIG. 2, a processor 20, a cache memory 22, a directory unit 24, a memory bus 28,
Internal address bus 36, flip-flop circuit 39, flip-flop circuit 41, flip-flop circuit 43, and flip-flop circuit 45, multiplexer 54, access request line 21, access permission line 23, bit notification line 25, bus request line 29, bus The permission line 31, and the set state notification lines 56 to 62 are the same components as those shown in FIG. 5, and the description thereof will not be repeated. The access control unit 70 includes an FF set line 72, an MPX1 control line 74, a counter control line 76, and an input line and an output line described with reference to FIG.
An MPX2 control line 78 and an address transmission instruction line 80 are provided, and these lines are lines for transferring an FF set signal, an MPX1 control signal, a counter control signal, an MPX2 control signal, and an address transmission instruction signal, respectively. is there. Details of these lines will be described later with reference to FIG. The FF set line 72 is connected to each set control input of the flip-flop circuit 39, the flip-flop circuit 41, the flip-flop circuit 43, and the flip-flop circuit 45. The MPX1 control line 74 is connected to the multiplexer control input of the multiplexer 54. Of the output bit line of the multiplexer 54, # 31 bit lines to fifth order bit lines, second bit lines, and the first order bit line (address part 2 ³¹ to 2 ^4, 2 ^1, 2 ^0, [challenge Means for addressing the address other than the address generation start address for the block read described in the section [1]) is directly connected to the corresponding input of the driver 82 via the transfer line 81. in contrast, fourth order bit lines, and the third order bit line (address part 2 ^3, 2 ^2, corresponding to the address generation start address portion for a block read is described in the section of [means for solving the problems] Is connected to the corresponding one of the bit inputs A ₃ and A ₂ of the multiplexer 84, and the other one of the bit inputs B ₃ and B ₂ is added to the +1 adding circuit 86.
Are connected. # 4 output bit line of the multiplexer 84, and a third of output bit lines (address 2 ^3, 2 ²⁾ is connected to a corresponding input of the driver 82 (address 2 ^3, 2 ^2), + 1 adder circuit Connected to 86 summing inputs. The flip-flop circuit 88 and the +1 adding circuit 86 constitute a counter 90. driver
The 82 32 output bit lines are connected to the address bus of the memory bus 28. An address transmission instruction line 80 is connected to an output control input of the driver 82. Multiplexer 84
The MPX2 control line 78 is connected to the multiplexer control input. A counter control line 76 is connected to the set control input of the +1 adding circuit 86.

As shown in FIG. 3, the access control unit 70 includes an access monitoring unit 92, an FF set signal generation unit 94, an MPX1 control unit 96, a memory bus monitoring unit 98, and a memory bus stage unit 100. The access monitoring unit 92 includes an access request line 21 from the processor 20, an access permission line 23, and a directory unit 24.
Hit notification line 25, and flip-flop circuit 3
9, a set state notification line 56 from the flip-flop circuit 41, the flip-flop circuit 43, and the flip-flop circuit 45,
The set state notification line 58, the set state notification line 60, and the set state notification line 62 are connected, and transmit a signal on the access permission line 93 indicating that access permission has been granted. The access permission line 93 is connected to the FF set signal generator 94, the MPX1 controller 96, the memory bus monitor 98, and the memory bus stage 100. The hit notification line 25 from the directory unit 24 is connected to the FF set signal generation unit 94 and the MPX1 control unit.
96, memory bus monitoring unit 98, and memory bus stage unit 10
Connected to 0. The FF set signal generation unit 94 that has received the signal via the hit notification line 25 and the access permission line 93
An FF set signal is transmitted on the set line 72. Hit notification line
25, and the MPX1 control unit 96 that has received the signal via the access permission line 93 sends out the MPX1 control signal on the MPX1 control line 74. The memory bus monitoring unit 98 is also connected to the hit notification line 25, and receives an access permission signal via the access permission line 93, but when the hit signal is not received via the hit notification line 25, the memory bus monitoring unit 98 A bus request is sent to a bus use permission circuit via a bus request line 29 of 28. When receiving a bus permission from the bus use permission circuit via the bus permission line 31, the memory bus monitoring unit 98 sends an address generation start signal on the address generation control line 99. After receiving the address generation start signal via the address generation control line 99, the memory bus stage unit 100 places a counter control signal, an MPX2 control signal, an MPX2 control signal on the counter control line 76, the MPX2 control line 78, and the address transmission instruction line 80, respectively. And an address transmission instruction signal.

2 and 3, the processor 20 corresponds to the processor 1 of FIG.
This corresponds to the cache memory 2 in the figure. The flip-flop circuits 39 to 45 correspond to the address buffer 3 in FIG. 1, and the directory section 24 corresponds to the directory section 4 in FIG. The access control unit 70 corresponds to the access control unit 5 in FIG. 1, and the multiplexer 54 corresponds to the first selection circuit 6 in FIG. The memory bus 28 corresponds to the memory bus 8 in FIG. 1, and the main memory 32 corresponds to the storage device 10 in FIG. The transfer line 81 corresponds to the transfer path 13 in FIG.
The 1-addition circuit 86 and the flip-flop circuit 88 correspond to the address portion generation circuit 14 in FIG. Multiplexer 84
Corresponds to the second selection circuit 15 in FIG.
Corresponds to the output circuits 16 and 17 in FIG.

The operation of the embodiment according to the first and second aspects of the present invention will be described below.

As described with reference to FIG. 5, when the access permission is returned to the processor 20 in response to the access request from the processor 20, the address is sent to the internal address bus 36, and the address of the corresponding data in the cache memory 22 in the directory unit 24 is At the same time as being subjected to the hit determination, the flip-flop circuit 39, the flip-flop circuit 41, the flip-flop circuit 43, and the flip-flop circuit 45 of the flip-flop circuit 45 are also set in the non-address-set flip-flop circuits (buffers).
This address setting is performed every time the processor 20 sends an address to the internal address bus 36. The flip-flop circuit to be set is the same as the set control in the above-described write-throw processing, and the next address-unset flip-flop is set. Circuit. This address set control is performed by the FF set signal generation unit 94 of the access control unit 70.
This is performed by an FF set signal output on the set line 72 in the same order as in the above-described write release processing. Further, any one of the flip-flop circuit 39, the flip-flop circuit 41, the flip-flop circuit 43, and the flip-flop circuit 45 is selected by the MPX1 control unit 96 of the access control unit 70 from the MPX1 control unit 96.
The operation is performed in the multiplexer 54 by the MPX1 control signal transmitted on the control line 74.

At the time of writing to the cache memory 22 (hereinafter, referred to as a write access mode), the MPX1 of the access control unit 70
The address of the flip-flop circuit selected by the multiplexer 54 based on the MPX1 control signal transmitted from the control unit 96 to the MPX1 control line 74 is transmitted to the multiplexer 84 and the driver.
It is supplied to the address bus of the memory bus 28 via 82 and used for the access. In this case, the MPX2 control signal transmitted from the memory bus stage unit 100 of the access control unit 70 onto the MPX2 control line 78 is a signal for selecting the multiplexer 54. In the case of a read from the cache memory 22 and a read in which the hit determination in the directory unit 24 is affirmative (hereinafter referred to as a first read access mode), the data is transmitted onto the internal address bus 36. Reading from the cache memory 32 is performed according to the read address, and the internal data bus 37 is read.
Is transferred to the processor 20 via

In reading from the cache memory 22, when the directory section 24 outputs information indicating a mishit to the access control section 70 via the hit notification line 25 (hereinafter, the second section).
Read access mode. ), Access control unit 70
Indicates a bus request line of the memory bus 28 from the memory bus monitor 98.
Send a bus request to 29. When the bus request is returned via the bus permission line 31 in the above-described manner in response to the bus request, the address of the flip-flop circuit corresponding to the mishit is transmitted from the MPX1 control unit 96 to the MPX1 control line 74. MP
It is output through the multiplexer 54 by the X1 control signal,
The address (the head address of the block read) is sent to the address bus of the memory bus 28 via the multiplexer 84 and the driver 82 as in the case of the write access mode. The address is stored in memory bus 28
Is transferred to the address input of the main memory 32 of the memory board via the address bus, and is used for reading from the head storage position in the block of the main memory 32 of the memory board which stores the data corresponding to the mishit. The data read in this manner is transferred to the memory bus in the same manner as described above.
Processor 20 via 28 data buses and data control LSI 34
After that, the data is written to the head address of the block read of the cache memory 22 applied to the address input of the cache memory 22 via the internal address bus 36.

The next data in the block in the second read access mode is the fourth output bit line and the third output bit line (address portion ²³ ,
2 ²⁾ to update the +1 address portion 2 ³ came supplied to the adding input of the adder 86, 2 ² the next data read address of the address part 2 ^3, 2 ² to the +1 adder circuit 86 via, This is set in the flip-flop circuit 88 by the counter control signal transmitted from the memory bus stage unit 100 onto the counter control line 76. The updated address part
2 ^3, 2 ² was passed through the multiplexer 84 by the MPX2 control signal transmitted from the memory bus stage section 100 on the MPX2 control line 78, and already among the Delivered address 2 ³¹ to 2 ⁰ in the driver 82, the address part 2 ^3, 2 ² and replaced by the next read address used to read out the next data in the block via the address bus of the memory bus 28 is supplied to the address input of the main memory 32 of the memory board. Further, for the next address and thereafter, the generation of each address is performed in accordance with the above.

As described above, the counter required in the address control system shared between the write-release processing and the block read is one.
Since the number is sufficient, the hardware can be reduced, and the delay generated by the multiplexer in the sequential address generation can be reduced to the delay generated by the 2-bit multiplexer.

Writing of the read data to the cache memory 22 is the same as that described above.

In the above-described embodiment, the generation system of the address portion for the block read (the multiplexer 84, the flip-flop circuit 88, and the +1 addition circuit 86) includes a separation portion of the address generation start portion from the head address of the block read; An addition portion that performs addition on the separated address generation start portion, and an output portion that combines the address generation start portion for block reading and the address portion generated by the addition portion in the start address. It may be configured.

〔The invention's effect〕

As described above, according to the present invention, by reducing the number of counters required in the address control system shared between the write release processing and the block read, the hardware is simultaneously reduced and sequentially generated in the block read and used for reading. And the propagation delay of the address signal generated in the address partial generation system can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the invention according to claims 1 and 2, FIG. 2 is a diagram showing an embodiment of the invention according to claims 1 and 2, and FIG. FIG. 4, FIG. 4 is an overall configuration diagram of a storage system of the information processing system, FIG. 5 is a diagram showing a block read control circuit of the storage system of FIG. 4, FIG. 6 is a diagram of FIG. It is a figure which shows the light release processing in the shown system configuration. 1 to 3, 1 is a processor (processor 20), 2 is a cache memory (cache memory 22), 3 is an address buffer (flip-flop circuits 39, 41, 4).
3, 45), 4 is a directory section (directory section 24), 5 is an access control section (access control section 70), 6 is a first selection circuit (multiplexer 54), 8 is a memory bus (memory bus 28), 10 Is a storage device (main memory 32), 12 is a separation output circuit (multiplexer 84), 13 is a transfer path (transfer line 81), 14 is an address part generation circuit (+1 addition circuit 86, flip-flop circuit 88), and 15 is 2 is a selection circuit (multiplexer 84), and 16 and 17 are output circuits (drivers 82).

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kenji Hoshi 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Eiji Kanaya 1015 Kamedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited ( 56) References JP-A-1-37641 (JP, A)

Claims (2)

(57) [Claims] When reading data from a cache memory by a processor, a read address is set in one address buffer of a predetermined set order among a plurality of address buffers, and a mishit is read in the directory section for reading by the read address. Indicates that the address buffer in which the read address is set is selected by the selection circuit under the control of the access control unit, and is sent to the memory bus to perform block read from the storage device. A separation output circuit for separating an address generation start address portion for block reading from a block read start address of the address buffer and outputting the block read start address, and an address generation start address section separated from the separation output circuit An address portion generation circuit for generating and outputting a sequential address portion from the output portion, an output of the block read start address from the separation output circuit, an address portion from the address portion generation circuit, and the output block read start An output circuit for replacing the address generation start address portion of the address with an output to the memory bus, and controlling the separated output circuit, the address portion generation circuit, and the output circuit. A block read address generation system comprising an access control unit. 2. When reading data from a cache memory by a processor, a read address is set in one address buffer having a predetermined set order among a plurality of address buffers, and a mishit is read in the directory section for reading by the read address. Indicates that the address buffer in which the read address is set is selected by the first selection circuit under the control of the access control unit, sent to the memory bus, and performs a block read from the storage device. A transfer path for transferring an address portion other than the address generation start address portion for block read from the address of the selected address buffer; a first input for receiving the address generation start address portion; With the second input received A second selection circuit that performs a uniform output; an address portion from the transfer path; and an address portion from the second selection circuit, and output to the memory bus as an address for the block read. An output circuit for generating an address portion sequentially from an address portion output from the second selection circuit, and an address portion generation circuit for outputting the address portion to the second input, the second selection circuit; The block read address generation system, wherein the access control unit is configured to control the output circuit and the address part generation circuit.