JP2600972B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor integrated circuit having a self-aligned silicide layer on source and drain surfaces.

[Conventional technology]

With the increase in the degree of integration of semiconductor integrated circuits, the miniaturization of element dimensions is abrupt. It is necessary to reduce the size of the element not only in the horizontal direction but also in the vertical direction. For this reason, the depth of the source and drain diffusion layers is decreasing year by year. In the conventional process, the wiring by the diffusion layer is formed at the same time as the source and the drain. Therefore, as the depth of the diffusion layer becomes shallower, the resistance of these layers increases and the operation speed of the circuit is significantly reduced.

In order to solve this problem, titanium (Ti), titanium (Ti),
A method of forming a metal silicide (silicide) such as cobalt (Co) or tantalum (Ta) has begun to be adopted. In this structure, for example, as shown in FIG. 3, a polycrystalline silicon gate electrode 4 is formed on a P-type silicon substrate 1 in an active region separated by a field oxide film 2 with a gate oxide film 3 interposed therebetween. On the side wall of the electrode 4, a side wall of the oxide film 6 is formed. For example, a titanium silicide layer 9 is formed on the source and the drain composed of the n ⁻ layer 7 and the n ⁺ layer 8, and at the same time, a titanium silicide layer 9 is formed on the polycrystalline silicon layer 4 of the gate electrode. Then, it has a structure in which a metal wiring layer 14 is connected via an interlayer insulating film 12. The method of forming the self-aligned silicide layer is described in, for example, IEEE Tr. Elec.
ev. Volume 32, p. 141 (1985), Alperin (M. Alpe)
rin) et al., "Development of Self-Aligned Titanium Silicide Process for VLSI". Since the layer resistance of the self-aligned silicide layer described above is as low as several Ω / □, it is possible to avoid an increase in diffusion layer resistance due to a shallow junction.

[Problems to be solved by the invention]

By the way, high integration of a semiconductor integrated circuit also requires fine wiring. For this purpose, it is necessary to minimize the unevenness of the substrate surface in the area where the wiring is formed. Conventionally, a heat-meltable insulating film such as PSG or BPSG is applied to the interlayer insulating film under the wiring, and this film is heated to 900 ° C. The surface of the substrate is flattened by heat treatment at a high temperature of about 1000 ° C. and reflow. However, in the above-described method of forming a self-aligned silicide layer on the source and drain surfaces, dopant impurities (for example, boron in a P-channel) in the source and drain diffusion layers are taken into the silicide layer by the high temperature reflow, and A decrease in the impurity concentration at the silicon interface causes a problem that parasitic resistance occurs and transistor characteristics deteriorate. Therefore, it is necessary to lower the reflow temperature of the interlayer film. However, lowering the temperature causes a decrease in reflow properties. On the other hand, even if the reflow temperature is lowered, it is more advantageous to use steam than nitrogen (N ₂ ) as an atmosphere gas in order to ensure reflow properties.
However, there is a problem that the silicide layer is deteriorated by oxidation.

[Means for solving the problem]

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode on one main surface of a silicon substrate via a gate insulating film, and a step of forming a sidewall in a self-aligned manner on a side surface of the gate electrode. A step of depositing a metal film on the surface of the silicon substrate, and reacting the metal film with the substrate silicon to form a source, drain and wiring layer region surface,
Forming a self-aligned metal silicide layer; removing an unreacted metal film; forming an oxidation-resistant insulating film layer on the formed self-aligned silicide layer; A step of depositing an interlayer insulating film and performing a heat treatment in an oxidizing atmosphere.

Example Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention. A field oxide film 2 for element isolation is formed on a P-type silicon substrate 1 by a selective oxidation method or the like, and a gate electrode composed of a two-layer film of polycrystalline silicon 4 and a tungsten silicide layer 5 is formed via a gate oxide film 3. Have been. An oxide film sidewall 6 is formed on the side surface of the gate electrode, and a source / drain diffusion layer composed of an n ⁻ layer 7 and an n ⁺ layer 8 in a self-aligned manner with respect to the gate electrode region, as well as titanium or the like. The self-aligned silicide layer 9 formed by the reaction with the substrate silicon is formed. Then, the oxide film layer 10, the nitride film layer 11, and the BPSG
The films 12 are sequentially deposited, and the metal wiring 14 is formed through the opening 16.

Hereinafter, the manufacturing method of the present invention will be described with reference to FIGS. 4 (a) to 4 (e).

First, as shown in FIG. 4 (a), a 3000-8000 [deg.] Field oxide film 2 is formed on a P-type silicon substrate 1 by a selective oxidation method or the like, and a polycrystalline silicon film 4 and a A tungsten silicide (WSix) film 5 is sequentially deposited, and a photoresist layer 15 is formed by photolithography or the like.

Then a fourth diagram WSix film as a mask above the photoresist layer, as shown in (b) 5 and the polycrystalline silicon film 4 to form a gate electrode is etched, self-aligned manner e.g. phosphorus 10 ¹³ cm ^{- About two} ions are implanted to form an n ⁻ layer 7. Thereafter, an oxide film is deposited on the substrate by a vapor deposition method of 1000 to 3000 degrees.

Next, as shown in FIG. 4C, etch back is performed so that the oxide film 6 remains only on the side surfaces of the gate electrode. Thereafter, for example, titanium is deposited on the surface of the substrate in a thickness of 500 to 1000 °, and is sintered in an inert atmosphere to react with the silicon of the substrate to form a silicide layer. On this occasion,
Since titanium in the region where silicon is not exposed remains unreacted, it is removed by wet etching, and titanium silicide (TiSi ₂ ) is selectively formed only on the source and drain surfaces.
Layer 9 is formed. And, for example, arsenic is 10 ¹⁵ -10 ¹⁶
The n ⁺ layer 8 is formed by ion implantation of cm ⁻² .

Next, as shown in FIG. 4 (d), an oxide film is formed on the substrate surface.
10 is deposited for about 200Å1500Å, and then nitride film 11 is deposited for 50Å.
Grow to a degree.

After that, a BPSG film is deposited in a thickness of about 2000 to 8000 mm. Then, by performing a heat treatment in a steam atmosphere at 800 to 850 ° C. to reflow the BPSG, the basic surface can be flattened as shown in FIG. 4 (e).

FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention. This embodiment has a so-called salicide structure in which a titanium silicide layer 9 is formed simultaneously on the surface of the gate electrode and on the surface of the source and drain, and furthermore, by applying the coating film 13 to the uppermost layer of the interlayer insulating film, the wiring is further improved. The resistance can be reduced and the substrate surface can be flattened.
The manufacturing method of this embodiment is almost the same as that of the first embodiment. The structure of the present invention is useful for the heat treatment after application of the coating film 13 because it is necessary to perform a heat treatment in an oxygen atmosphere for the purpose of improving the film quality. FIG. 5 shows a third embodiment of the present invention. . In this embodiment, the nitride film 11 is formed only on the surface of the titanium silicide layer 9. In this example, there is an advantage that the region other than the titanium silicide layer has no diffusion barrier due to the nitride film layer. FIGS. 6A to 6C show a manufacturing method according to this embodiment.
This will be described below. Until the process of forming the gate electrode and forming the titanium silicide layer on the source and drain surfaces,
This is the same as the first embodiment. As shown in FIG. 6A, a nitride film 11 is formed on the surface of the substrate including the surface of the titanium silicide layer 9.
Then, a spin-on glass (SOG) film 17 is applied. Using the difference in the thickness of the SOG film between the flat portion and the concave portion, etch back is performed so that the nitride film remains only on the source and drain surfaces as shown in FIG. Thereafter, as shown in FIG. 6 (c), for example, a PSG film 12 and a coating film 13 are formed on the surface of the substrate, and the same steps as in the above-described embodiment are performed.

〔The invention's effect〕

As described above, according to the present invention, in a semiconductor device having a self-aligned silicide layer formed by the reaction of titanium, cobalt, etc. with silicon on the surface of a source, a drain and a silicon wiring layer, an oxidation-resistant insulating film is formed on the silicide layer. By doing so, the reflow of the interlayer insulating film can be performed in an oxidizing atmosphere, whereby the reflow temperature can be lowered, and the redistribution of dopant impurities in the source and drain diffusion layers to the silicide layer can be prevented, and the device characteristics can be improved. There is an effect that a high-speed and high-density semiconductor device without deterioration of the semiconductor device can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a part of a semiconductor device showing a first embodiment of the present invention, FIG. 2 is a sectional view showing a semiconductor device showing a second embodiment of the present invention, and FIG. 4 (a) to 4 (e) are process cross-sectional views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 5 is a third embodiment of the present invention. 6 (a) to 6 (c) are cross-sectional views showing steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention. 1 ... silicon substrate, 2 ... field oxide film, 3 ...
Gate oxide film, 4 gate electrode, 6 sidewall, 7 n ^- layer, 8 n ⁺ layer, 9 titanium silicide layer, 11 nitride film, 10, 12, 13 ... Interlayer insulating film.

Claims (1)

(57) [Claims] A step of forming a gate electrode on one principal surface of a silicon substrate via a gate insulating film; a step of forming a spacer of the insulating film by self-alignment with a side wall of the gate electrode; A step of applying a metal film on the surface, and the reaction between the metal film and silicon, the silicon substrate and
A step of forming a metal silicide layer on a substrate surface serving as a source, drain and wiring region forming a PN junction, a step of removing an unreacted metal film, and a step of removing the surface of the silicon substrate on which the metal silicide layer is formed. A method for manufacturing a semiconductor device, comprising: a step of covering an oxidation-resistant insulating film; and a step of depositing an interlayer insulating film on the surface of the silicon substrate and performing a heat treatment in an oxidizing atmosphere.