JP2600866B2 - Phase comparison device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparison device used in a PAL color video camera or the like, and speeds up phase synchronization when synchronizing a subcarrier with a horizontal synchronization signal. The present invention relates to a phase comparison device.

2. Description of the Related Art A phase comparison device of this type used in a PLL device often employs a digital mixer system, and a conventional circuit configuration is shown in FIG.

The conventional device shown in FIG. 3 includes a D-type flip-flop (hereinafter, referred to as DFF) 1, a 1/2 frequency divider 8, and an edge comparison type phase comparator 7.

Then, the 1/2 frequency divider 8 divides the frequency of the horizontal synchronizing signal (f _H ) input from the terminal 11 by 1/2 and outputs a (f _H / 2) signal.

DFF1 is a signal (2) obtained by multiplying a subcarrier signal (f _SC ) generated by a subcarrier generator (not shown) by two.
f _SC ) is input to the data input terminal D via the input signal terminal 10, and the output signal (f _H /
2) is input, and the level of the double subcarrier signal (2f _SC ) is sampled at the cycle of the f _H / 2 signal, and the sampled output signal (f _Q ) is output to the output terminal Q.

The comparator 7, the output signal of the DFF1 (f _Q) and the output signal of the 1/2 frequency divider 8 (f _H / 2) and are input to compare the phase difference between the rising edges of the two signals input , Comparison error output
_EO is output from the output terminal 13.

Further, the output E _O of the comparator 7 output from the output terminal 13 to the outside is smoothed by a low-pass filter (not shown), and the smoothed output is fed back to a subcarrier generator (not shown). Then, the above circuit constitutes a feedback loop for detecting the error of the phase difference between the subcarrier and the vertical synchronization signal and finely adjusting the subcarrier frequency.

Here, the subcarrier frequency f _SC used in the PAL system
And each synchronization signal will be described.

In the PAL system, every second 25 sheets of number of screens, so to display an image of one screen by the number 625 lines, the horizontal scanning frequency f _H of the horizontal synchronizing signal is set by the following equation.

f _H = 625 × 25 = 15.625 [KHz] (1) The subcarrier frequency f _SC is set as in the following equation in order to improve dot interference.

f _SC = (1135/4 + 1/625) f _H (2) Further, because of using a 2: 1 interlaced scanning method, the vertical scanning frequency f _V of the vertical synchronizing signal is as follows.

f _V = f _H · 2/625 (3) Next, the operation of the circuit will be described with reference to the operation explanatory diagram shown in FIG. In FIG. 4, the horizontal axis indicates the frequency (2f _SC ) of the double subcarrier applied to DFF1, and the vertical axis indicates
The output frequency (f _Q ) of the output terminal Q of DFF1 is shown.

DFF1, the output signal of the 1/2 frequency divider 8 (f _H / 2) is input to the clock input CK, samples the level of the data input terminal D at the rising edge of the clock, an output terminal an output sampled Output to Q. Therefore, if the input signal of the data input terminal D at the time of sampling is at a high level, a high level is output to the output terminal Q and the high level output state is maintained until the next clock is input. Then, when the clock rises while the data input terminal is at the low level, the output terminal Q is switched to the low level at the rising edge, and the low-level output state is maintained until the next clock is input.

Therefore, when the input signal f _D (= 2f _SC ) of the data input terminal D changes, the frequency f _Q of the output terminal Q of DFF1 changes accordingly as shown in FIG. For example, when the frequency of the input signal f _D becomes an integral multiple of the frequency of f _H / 2 is changed, every time the clock (f _H / 2) is input to the clock input CK, corresponding to the clock position will be sampling the same phase of the f _D, since this time, does not change the level of the output terminal Q, the frequency f _Q output terminal Q becomes zero. The point at which f _Q becomes maximum is a point at which the phase of f _D to be sampled constantly changes, and the maximum value of f _Q is a frequency that is half the frequency of (f _H / 2).
That is, the frequency of the output terminal Q with respect to the input signal f _D (= 2f _SC )
Correlation f _Q is as shown in Figure 4, f _Q has a correlation characteristic as folded with respect to the input signal f _D, f _H from zero
By utilizing the slope including the point A in FIG. 4 which changes to / 4, the correlation characteristic between the subcarrier f _SC and the horizontal synchronization signal f _H is obtained. In order to specify the slope to be used, the oscillation frequency due to the free-running oscillation of the subcarrier generator (not shown) is selected by selecting a circuit constant set near the point A. Thus, to obtain an output frequency f _Q of the 2 Tei times subcarrier (2f _SC) were mixed down to an output terminal Q of the DFF1. As shown in FIG. 4, the output frequency f _{Q that} has been mixed down changes within a range where the minimum value is zero and the maximum value is f _H / 4.

The phase comparator 7 calculates the output frequency f _Q and the vertical synchronization signal f _V
And the desired subcarrier f _SC (4.433
Output frequency f _{Q at} point A corresponding to 619 MHz) (= 2f _H / 625)
And take the vertical synchronization signal f _V and synchronization. And subcarrier
f _SC frequency deviation is automatically set by the feedback loop.

Therefore, such a conventional phase comparator using a digital mixer, holds the following equation between the horizontal synchronizing signal f _H and the vertical synchronizing signal f _V subcarrier _{f SC, 2f SC = 1135 (} f H / 2) + f _V = 1135 (f _H / 2) + 2f _H / 625 (4) The following equation is established between the subcarrier f _SC and the horizontal synchronization signal f _H.

f _SC = (1135/4 + 1/625) f _H ... (5) Problems to be Solved by the Invention However, in the conventional device, in the transitional period at the time of power-on, the subcarrier generator (V _CXO ) When the oscillation frequency was not in the appropriate range, the oscillation frequency (f _SC ) sometimes locked at a lower order frequency. The phase comparison output of the vertical synchronizing signal f _V and the digital mixer frequencies f _Q, to draw the oscillation frequency of the subcarrier generator (V _CXO), the phase comparison is performed in repetition period of the vertical synchronizing signal f _V, to Yosu a long time to pull the oscillation frequency, is due to the above problems, it is difficult to make the sub-carrier generator operating in a stable oscillation frequency while the horizontal synchronization signal f _H and the phase synchronizing (V _CXO) There was a problem.

SUMMARY OF THE INVENTION The present invention solves the above-described problems, and speeds up the pull-in of the oscillation frequency of a subcarrier generator (V _CXO ),
An object of the present invention is to provide a phase comparison device that can expect stable operation.

Means for Solving the Problems In order to solve the above-mentioned problems, the phase comparison device of the present invention uses a subcarrier f _SC that is a half cycle (f _V /
Masking 2), said sub-carriers masked 1/1135 divides, f _H / 4 obtained by frequency 1/4 the horizontal synchronizing signal f _H
A phase is compared between the signal and the 1/1135 frequency-divided output, and a feedback loop is configured to control the subcarrier generator (V _CXO ) with the output of the LPF that filters the output of the comparison error.

Operation With the above configuration, the subcarrier f _SC is masked at a half cycle (f _V / 2) of the vertical synchronization signal, and
If the _SC (f _V / 2) amount corresponding to the frequency subtraction, the frequency subtraction outputs (f _SC -f _V / 2) a 1/1135 frequency-divided signal, obtained by frequency 1/4 the horizontal synchronizing signal f _H f _By phase comparison with _H / 4 signal,
It is possible to perform phase synchronization with the horizontal synchronization signal f _H and the subcarrier f _SC.

Then, the phase comparison operation of the present invention is performed by the horizontal synchronization signal f _H
Of the vertical synchronization signal, f
Compared with the phase comparison performed at _V , the phase comparison is performed at a much higher frequency, and the frequency of the subcarrier generator (V _CXO ) can be quickly _pulled .

Embodiment Hereinafter, an embodiment of a phase comparison device according to the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of one embodiment, and FIG. 2 is an explanatory diagram of its operation.

In FIG. 1, 1, 2 are DFFs, 3 is an inverting gate, 4 is NA
ND gate, 5 is an AND gate, 6 is a 1/1135 divider, 7 is a phase comparator, 8 is a 1/2 divider, 9 is a 1/4 divider, 10 is a subcarrier input terminal, 11 Is a terminal to which the horizontal synchronization signal is applied, 12 is a terminal to which the vertical synchronization signal is applied, and the phase comparator 7
Output terminal.

The inverting gate 3, subcarrier f _SC inputted from the input terminal 10 to the input terminal, and outputs the inverted signal of the subcarrier f _SC to the output terminal.

Vertical synchronizing signal f _V inputted from the terminal 12 is input to the input terminal of the 1/2-frequency divider 8, 1/2-frequency divider 8 is divided by 2. Then, 1 / output signal of the 1/2 frequency divider 8 f _V / 2 (see f _V in FIG. 2) is input to the data input terminal D of the DFF1, the output terminal Q of the DFF1 is data input of DFF2 D DFF1 and DFF2
Are both connected to the output of the inverting gate 3.

Therefore, DFF1 and DFF2 Since the output level of the data input terminal D when the output signal of the inverter 3 (the inverted signal of the subcarrier f _SC) rises to the output terminal Q, the output terminal Q of the DFF1, for example, After f _V / 2 goes high,
Signal at the output terminal Q at the first subcarrier f _SC falls timing rises, after a f _V / 2 is set to low level, the falling signal of the output terminal Q is the first subcarrier f _SC falls timing (See 1 (Q) in FIG. 2). The signal at the output terminal Q (not shown) of DFF2 is
DFF at falling edge of subcarrier f _SC delayed by one cycle
1 follows the signal level of the output terminal Q, and the inverted output terminal N of DFF2
The Q signal follows the inverted signal level of the output terminal Q of DFF1 at the falling edge of the sub-carrier f _SC delayed by one cycle (see 1 (Q), 2 (NQ) in FIG. 2).

The NAND gate 4 and the AND gate 5 that constitute the logic circuit have N
The input terminal of the AND gate 4 is connected to the output terminals of DFF1 and DFF2, and generates a masking pulse (4 in FIG. 2) at the output terminal of the NAND gate 4 according to the logic of the outputs of DFF1 and DFF2. As a result, one cycle of the subcarrier f _SC input to the input terminal of the AND gate 5 is masked at every (f _V / 2) repetition period, and the output signal fs masked at the output terminal of the AND gate 5 is output. (See 5 (fs) in FIG. 2).

The 1/1135 frequency divider 6 has an output terminal f
Since s is input and divided by 1/1135, the output signal fx is given by the following equation.

fx = Substituting _{(f SC -f V / 2)} / 1135 Equation 3 ... (6) (6), fx = (f SC -f H / 625) / 1135 ...... (7) Next, 1/4 frequency divider 9, a horizontal synchronizing signal f _H supplied from the terminal 11 and 1/4 frequency-divides a signal (f _H / 4) to the output end. Then, the phase comparator 7, 1 / a 1/4 frequency divider 9 of the output signal (f _H / 4), compares the phases of the output signal fx 1/1135 frequency divider 6, an error signal to the output terminal 13 Outputs Eo. Further, similarly to the conventional example, the error signal Eo is smoothed by a low-pass filter (not shown) connected to the output terminal 13, and the smoothed signal is fed back to a subcarrier generator (not shown). With this feedback loop, the input signal of the phase comparator 7 (f _H / 4
And fx) control the oscillation frequency of the subcarrier generator so that the phases of the subcarrier generators coincide with each other. Therefore, control is performed so that the following equation is satisfied.

(F _SC −f _H / 625) / 1135 = f _H / 4 (8) By deriving the equation (8) into the equation of f _SC equal, f _SC = (1135 / 4−1 / 625) f _H. (9), and the same expression (9) as the above-described desired expression (2)
And the phase synchronization between the subcarrier frequency f _SC and the frequency f _H of the horizontal synchronization signal is performed.

This embodiment performs the frequency control in much the same accuracy as the conventional example, the phase comparison operation by the phase comparator 7 performs were circumferential 1/4 horizontal synchronizing signal f _H (f _H /4=3.9KHz performed at a frequency of), that in comparison with the frequency of the phase comparison operation of the conventional example (f _V = 50 Hz), carried out at much higher frequencies, a faster pull-in frequency, stably operated subcarrier generator Can be.

Phase comparison device of the present invention as described above the effect of the invention, the operation of the phase comparison is performed in 1/4 of the frequency of the horizontal synchronization signal f _H, the phase comparison frequency f _V of the vertical synchronizing signal which has been conventionally performed It operates at a much higher frequency (f _H / 4), and the frequency of the subcarrier generator is pulled faster. In addition, there is a special effect that the frequency of the subcarrier generator in the PAL color video device is stabilized.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an embodiment relating to a phase comparison device of the present invention, FIG. 2 is a diagram for explaining the circuit operation of FIG. 1, FIG. 3 is a circuit configuration diagram of a conventional device, FIG. The figure is an operation waveform diagram of the conventional device. 1,2 ... D-type flip-flop, 3 ... Inverting gate, 4
… NAND gate, 5… AND gate, 6… 1/1135 divider, 7… Phase comparator, 8… 1/2 divider, 9… 1/4 divider, 10… ... an input signal terminal for inputting a subcarrier signal, 11 ... a terminal for inputting a vertical synchronization signal, 12 ... a terminal for inputting a horizontal synchronization signal, 13 ... an output terminal.

Claims (1)

(57) [Claims] A phase comparison between a subcarrier generated by a subcarrier generator and a horizontal synchronizing signal is performed, a comparison error output is smoothed by a low-pass filter, and the smoothed output is fed back to the subcarrier generator. In a phase comparison device used for a feedback loop for controlling a carrier frequency, a 1/2 frequency divider for dividing an input vertical synchronization signal by 1/2, and an output signal of the 1/2 frequency divider is applied to a data input terminal. Entered,
A first D-type flip-flop that outputs its data input in synchronization with the inverted signal of the subcarrier in clock, and an output signal of the first D-type flip-flop is input to a data input terminal, and the data input is A second D-type flip-flop that outputs the inverted signal of the subcarrier in synchronization with the clock, and the logic of the output of the first and second D-type flip-flops, for each half frequency of the vertical synchronization signal A logic circuit for masking the subcarrier; and an input signal for dividing the output signal of the logic circuit by 1/1135.
A 1135 divider, a 1/4 divider that divides the input horizontal synchronization signal by 1/4, an output signal of the 1/1135 divider, and an output signal of the 1/4 divider. And a phase comparator that outputs the comparison error output from an output terminal.