JP2697679B2 - Dither image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dither image display device, and more particularly, to an image display device having improved display quality by using a dither method.

[0002]

2. Description of the Related Art Conventionally, there is a dither method as a method for displaying a high-quality image with a frame buffer having a smaller capacity than the amount of information of an image to be displayed. The dither method is roughly classified into two methods, an ordered dither method shown in FIG. 3 and an error diffusion method shown in FIG. In these dithering methods, a method is used in which an image is processed and an image from which false contours have been removed is stored in a frame buffer.

In the ordered dither method, a value obtained by adding a predetermined value to a pixel value of an original image is used as a pixel value. The predetermined value added to the pixel value is a constant depending on the coordinate value of the pixel, and is usually obtained from a matrix having a size of M × N. For example, the value of the matrix (X mod M, Y mod N) is added to the pixel having the coordinate value (X, Y). The ordered dither method has a feature that the amount of hardware is small.

In the other error diffusion method, low-order bits that cannot be stored in a frame buffer among pixel information of an original image are accumulated, and the low-order bits are added before processing an adjacent pixel, thereby obtaining pixel information. Is updated and then stored in the frame buffer. As the direction in which the lower bits of the pixel information are propagated, there are usually two directions, upper and lower, or
Four directions are taken: lower, lower right, lower left. This error diffusion method
It has the feature of high image quality.

As a conventional example similar to the technical field of the present invention, Japanese Patent Application Laid-Open No. 1-267 discloses a technique of compressing input image data by using multi-value dither processing and storing the compressed image data in an image memory.
Japanese Patent Application Laid-Open No. Sho 63-213084 discloses a technique for converting a digital image signal into a dithered image signal using a dither matrix.

[0006]

However, in the ordered dithering method, since the size of the matrix is very small compared to the size of the image, a specific pattern appears over the entire image and the image quality is low. With problems. Further, the other error diffusion method requires a buffer for storing lower-order bits for at least one line of an image, and involves a problem that the amount of hardware is increased.

The above-mentioned prior art is disclosed in Japanese Patent Laid-Open No. 26778/1990.
No. 2 relates to the application of dither processing, whereas JP-A-63-213084 differs from the present invention in the configuration of the present invention.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a dither image display device capable of obtaining high image quality with a small amount of hardware and low cost.

[0009]

In order to achieve the above object, a dither image display apparatus according to the present invention comprises an adding means for adding input image data and fed-back image data and outputting the added image data; The data is divided into upper bit and lower bit image data, and the divided lower bit image data is set to 1/1 and 1/2.
A first and a second for selecting and outputting any one of these;
Selecting means, first and second buffer means for respectively holding image data output from the two selecting means,
Third selecting means for selecting and outputting one of the two image data of the two buffer means, wherein the image data output from the third selecting means is used as feedback image data to the adding means, and It is characterized in that image data is used as output image data.

Further, the first, second and third selecting means are arranged so that each of the first, second and third selecting means can select a value based on the coordinate value of the image data input to each of them.
One of the two inputs may be selected and output.

[0011]

Therefore, according to the dither image display device of the present invention, the input image data and the fed-back image data are added and output, and the added image data is converted into upper bit and lower bit image data. The image data of the lower-order bit is divided into 1/1 and 1
/ 2, and either one of them is selected and output. There are two selection outputs, each output image data is held, and the held image data is selected and output. The output image data is fed back to be the above-described added image data. The upper bit image data of the added image data is set as output image data. According to this procedure, a processing procedure of high-quality dither processing with a smaller buffer capacity is secured.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a dither image display device according to the present invention will be described in detail with reference to the accompanying drawings. 1 to 3 show an embodiment of a dither image display device to which the dither image display device of the present invention is applied. FIG. 1 is a circuit configuration block diagram of a dither image processing unit of the present embodiment,
FIG. 2 is a circuit configuration block diagram of a dither image display device including a dither processing unit. FIG. 3 is a time chart showing the data flow in the main part of FIG. 1 in a tabular form.

The dither image display device of this embodiment will be described below. The dither processing unit 1 includes an adder 11, buffers A14 and B15, selectors A12, B13, and C1.
6.

The adder 11 is a circuit for adding pixel data. In this embodiment, an adder having two inputs and one output is used. Pixel data to the present device is input to one of the two input terminals. The output data of the selector C16 is fed back and input to the other input terminal.

The buffers A14 and B15 are temporary storages for storing pixel data. Each buffer A14, B15
Then, the output data selected by the selectors A12 and B13 is held. Since the input is held at the falling edge of the synchronization signal (not shown), the input is delayed by one clock.

The selectors A12, B13 and C16 are two-input / one-output line selectors. Selector A12, B
The data of 1/2 and 1/1 of the lower bits of the data output from the adder are input to 13, and any one of the data is output. This selection is determined by the X coordinate value and the Y coordinate value of the input data. That is, the selector A1
2 and B13 select a value of 1/2 of the lower bit when the X coordinate of the pixel is 0, and otherwise select 1/1 of the lower bit according to the output signal from the X coordinate determiner (not shown). Select a value. In the selector C16, the value of the buffer A14 is selected when the Y coordinate of the pixel is an even value, and the value of the buffer B15 is selected when the Y coordinate of the pixel is an odd value.

FIG. 3 shows a data flow in the main part of the embodiment constituted by the above-mentioned respective parts. In FIG. 3, circled numbers in the uppermost column indicate the order of timing, and vertical columns indicate identification names of data and the like. That is, a is an X coordinate value, b is a Y coordinate value, c is an input pixel, d is an adder input, and e is a buffer A1.
4, the data held in buffer B15, g
Is output data of the selector C16, and h is output data of the dither image display device. In FIG. 3, H (X) represents the upper bits of the adder output data, and L (X) represents the lower bits of the adder output data.

The operation of the dither image display device of this embodiment will be described below with reference to FIG. Selectors A12, B13
When the X-coordinate value of a pixel is 0 by an X-coordinate determiner (not shown), the value is 下 位 of the lower bit of the adder output data; L
(Pn + An) / 2 and L (Pn + An) / 2, and select X
When the coordinate value is other than 0, the lower bit value itself; L
(Pn + An).

The buffer A14 inputs the output value of the selector A12 when the X coordinate value of the pixel data by the X coordinate determiner and the Y coordinate determiner is 0 or the Y coordinate value of the pixel data is an even number. Rewrite the contents of The buffer B15 receives the output value of the selector B13 when the X coordinate value of the pixel data by the X coordinate determiner and the Y coordinate determiner is 0 or when the Y coordinate value of the pixel data is an odd number. Rewrite the contents of The buffers A14 and B15
If each does not satisfy the above condition, the current held data is held continuously.

There is a delay of one clock between the value selected by the selectors A12 and B13 and the data determined and held in the buffers A14 and B15. In these relations in FIG. 3, the respective data shown in the buffer A14 of e and the buffer B15 of f are determined data in the buffers A14 and B15. Therefore, for example, the value of 1/2 of the lower bit selected by the selector A12 at the coordinates (0, 0); L (P0 + A0) / 2 is determined and held in the buffer A14 at the coordinates (1, 0). Similarly, at the coordinates (0, 0), the value of 1/2 of the lower bit selected by the selector B13; L (P0 + A0) / 2
Is determined and held in the buffer B15 at the coordinates (1, 0).

When the X coordinate value is 0, the selector A12 selects 1/2 of the lower bit. Therefore, the data selected in the column and in FIG. 3 is held in the buffer A14 in the column and in the column. When the X coordinate value is other than 0, 1/1 of the lower bit is selected. Therefore, the data selected in the column of FIG. 3 is held in the buffer A14 in the column.

The selector B13 selects the lower bits under the same condition of the X coordinate value as the selector A. When the Y coordinate value is other than an odd number, the selector B13 continuously holds the current held data. Thus, for example, the value selected in the column of FIG.
Are stored in the buffer B15.
The value selected in the column is held in the column, and the value selected in the column is held in the buffer B15 in the column.

In the selector C16, when the Y coordinate value of the pixel is an even value, the output data of the buffer A is selected, 0 at the timing, L (P0 + A0) / 2 at the timing,
At the timing, L (P1 + A1) is output. Also,
When the Y coordinate value of the pixel is an odd value, the output data of the buffer B15 is selected, and L (P2 + B2) is output at the timing and L (P3 + B3) / 2 is output at the timing.

The output data of the selector C16 is added to the adder 11
And is added to the input pixel data of c. The output data of the adder 11 is h in FIG.

According to the above configuration, high-quality dither processing can be realized with a smaller amount of hardware, and a high-quality image can be displayed at low cost.

Although the above embodiment is one preferred embodiment of the present invention, the present invention is not limited to this embodiment, and various modifications can be made without departing from the spirit of the present invention.

[0027]

As is clear from the above description, the dither image display device of the present invention adds the input image data and the fed-back image data, and adds the added image data to the upper bit and lower bit image data. 2 minutes. The image data of the lower-order bit divided into two is 1/1 and 1
/ 2, and either one of them is selected and output. There are two selection outputs, and each output image data is held. One of the held image data is selected and output. The selected and output image data is fed back to be the above-described added image data. The higher-order bit image data of the added image data is used as output image data of the present dither image display device. According to this procedure, a processing procedure of high-quality dither processing with a smaller buffer capacity is secured. Therefore, it is possible to display a high-quality image at low cost.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a dither processing unit of a dither image display device of the present invention.

FIG. 2 is a block diagram illustrating an overall configuration example of a dither image display device according to the present invention.

FIG. 3 is a time chart showing the operation of the dither processing unit in FIG. 1 in a tabular form.

FIG. 4 is a block diagram of a configuration example of an image display device using a conventional ordered dither method.

FIG. 5 is a block diagram of a configuration example of an image display device using a conventional error diffusion method.

[Explanation of symbols]

 Reference Signs List 1 dither processing unit 2 frame buffer 11 adder 12 selector A 13 selector B 14 buffer A 15 buffer B 16 selector C

Claims (2)

(57) [Claims] An adding means for adding the input image data and the fed-back image data and outputting the added image data; and dividing the added added image data into upper bit data and lower bit image data. The first and second selecting means for selecting and outputting one of the lower-order bit image data, and the image data output from the two selecting means. First and second buffer means for holding each of them; and third selecting means for selecting and outputting one of the two image data of the two buffer means. A dither image display device, wherein the image data obtained as feedback image data to the adding means and the image data of the upper bits are output image data. 2. The apparatus according to claim 1, wherein said first, second, and third selecting means selects and outputs one of two inputs according to the coordinate values of the image data input to each. 2. The dither image display device according to 1.