JP2697345B2 - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JP2697345B2 JP2697345B2 JP3085631A JP8563191A JP2697345B2 JP 2697345 B2 JP2697345 B2 JP 2697345B2 JP 3085631 A JP3085631 A JP 3085631A JP 8563191 A JP8563191 A JP 8563191A JP 2697345 B2 JP2697345 B2 JP 2697345B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- mounting
- wiring
- electrodes
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4635—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating flexible circuit boards using additional insulating adhesive materials between the boards
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、混成集積回路に関す
る。This invention relates to hybrid integrated circuits.
【０００２】[0002]
【従来の技術】従来の混成集積回路は、回路を形成した
回路基板上に、半田ペーストを、実装する半導体装置の
電極に合せて形成された半田ランド上に塗布し、半導体
装置の電極を半田ランドに合せて半田を溶かし回路基板
と半導体装置を接続していた。2. Description of the Related Art In a conventional hybrid integrated circuit, a solder paste is applied on a circuit board on which a circuit is formed, on a solder land formed in accordance with an electrode of a semiconductor device to be mounted, and the electrode of the semiconductor device is soldered. The circuit board and the semiconductor device were connected by melting the solder according to the land.
【０００３】[0003]
【発明が解決しようとする課題】従来の混成集積回路
は、搭載する半導体装置の電極及びピッチに合せて半導
体装置を実装する回路基板上に接続用のランドを形成す
る必要があり、回路基板のサイズに制約がある場合、回
路基板上の配線は、形成されたランドの間に配線する
為、回路基板上に配線を収容しきれなくなるという問題
点があった。配線密度を上げる対策として回路基板の多
層化があるが、各層の接続電極の面積が必要になり、高
密度実装が進む中では、限界がある。In the conventional hybrid integrated circuit, it is necessary to form connection lands on a circuit board on which the semiconductor device is mounted in accordance with the electrodes and pitches of the semiconductor device to be mounted. When the size is restricted, the wiring on the circuit board is wired between the formed lands, so that there is a problem that the wiring cannot be accommodated on the circuit board. As a countermeasure to increase the wiring density, there is a multi-layer circuit board. However, the area of the connection electrodes in each layer is required, and there is a limit in the progress of high-density mounting.
【０００４】又、半導体ベアチップと表面実装用半導体
装置を同一回路基板上に実装する場合、半導体ベアチッ
プの電極が多いと、回路基板に設ける電極及び電極から
の配線導体も多くなり、半田ランドを形成するのに必要
なスペースを確保するには、回路基板を多層にするか、
回路基板のサイズを大きくしなければならないという問
題点があった。When a semiconductor bare chip and a semiconductor device for surface mounting are mounted on the same circuit board, if the number of electrodes of the semiconductor bare chip is large, the number of electrodes provided on the circuit board and the number of wiring conductors from the electrodes are increased, and solder lands are formed. To get the space needed to do this, make the circuit board multilayer or
There was a problem that the size of the circuit board had to be increased.
【０００５】[0005]
【課題を解決するための手段】本発明の混成集積回路の
構成は、複数の絶縁フィルムの層間に配線を設けてこれ
ら配線に接続され上面に回路素子搭載用の電極および下
面に回路基板接続用の電極を設けた実装用補助フィルム
と、前記回路基板接続用の電極と接続するランドおよび
配線が上面に設けられ前記実装用補助フィルムを搭載し
実装する回路基板とを有することを特徴とする。SUMMARY OF THE INVENTION The present invention relates to a hybrid integrated circuit .
Configuration, which is provided with wiring layers of the plurality of insulating films
A mounting assisting film provided with electrodes for a circuit board connected to the electrodes and the lower surface of the circuit element mounting connected to the upper surface to the al wiring, land connected to the electrode for the circuit board connection and
Wiring mounting the mounting assisting film provided on the upper surface
And having a circuit board for mounting.
【０００６】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【０００７】図１（ａ）は本発明の一実施例を示す分解
斜視図、図１（ｂ）は図１（ａ）の実装用補助フイルム
の分解斜視図である。FIG. 1 (a) is an exploded perspective view showing an embodiment of the present invention, and FIG. 1 (b) is an exploded perspective view of the mounting auxiliary film of FIG. 1 (a).
【０００８】図１（ａ）に示すように、上面に設けた電
極１０，１１に接続してフラットパッケージ型半導体装
置４を搭載し、下面に回路基板接続用の電極１２を設
け、電極１０，１１と電極１２間を接続した実装用補助
フイルム５を回路基板５の上に載せ、回路基板５の上に
設けた配線９に接続して設けたランド６と電極１２とを
接続して実装する。As shown in FIG. 1A, a flat package type semiconductor device 4 is mounted by connecting to electrodes 10 and 11 provided on an upper surface, and an electrode 12 for connecting a circuit board is provided on a lower surface. The mounting auxiliary film 5 connecting the electrode 11 and the electrode 12 is mounted on the circuit board 5, and the land 6 connected to the wiring 9 provided on the circuit board 5 and the electrode 12 are connected and mounted. .
【０００９】図１（ｂ）に示すように、実装用補助フイ
ルム５は２枚の絶縁フイルム２の間に電極１０，１１，
１２及びこれらを接続する配線１を挟んで積層し、半導
体装置４を接続する電極１０の上面と、半導体装置４を
接続し且つランド６に接続する上面の夫々の絶縁フイル
ム２に開孔部を設けると共に電極１２の下面及び直接回
路基板７上に素子を搭載するための開孔部１３を設けて
いる。なお、位置合わせマーク３は実装用補助フイルム
５と回路基板７との位置合わせを行なうためのものであ
る。なお、実装用補助フイルム５は配線１を絶縁フイル
ム２を介して多層に形成しても良い。As shown in FIG. 1B, an auxiliary mounting film 5 has electrodes 10, 11, and 10 between two insulating films 2.
Openings are formed in the upper surface of the electrode 10 connecting the semiconductor device 4 and the insulating film 2 on the upper surface connecting the semiconductor device 4 and connecting to the land 6. In addition, an opening 13 for mounting an element on the lower surface of the electrode 12 and directly on the circuit board 7 is provided. The alignment mark 3 is used to align the mounting auxiliary film 5 with the circuit board 7. Note that the mounting auxiliary film 5 may be formed by forming the wiring 1 into a multilayer through the insulating film 2.
【００１０】[0010]
【発明の効果】以上説明したように本発明は、実装用補
助フイルムを半導体装置と回路基板の間に介在させるこ
とにより回路基板のサイズに制約が有る場合でも回路基
板の配線数を増やす事が出来、集積度が高くなるという
効果を有する。As described above, according to the present invention, the number of wirings on the circuit board can be increased even if the size of the circuit board is restricted by interposing the mounting auxiliary film between the semiconductor device and the circuit board. This has the effect of increasing the degree of integration.
【００１１】又、半導体ベアチップとフラットパッケー
ジ型半導体装置を同一基板上に実装する場合等の半導体
を同一基板上に実装する場合等の半導体装置の電極から
の引き出し本数が多い場合でも、回路配線上の制約が多
い回路基板上の配線の一部を実装用補助フイルム上に設
けることにより、配線の密集度を緩和できる。Further, even when a semiconductor bare chip and a flat package type semiconductor device are mounted on the same substrate, or when a semiconductor is mounted on the same substrate, or when the number of lead-outs from the electrodes of the semiconductor device is large, the circuit wiring can be reduced. By providing a part of the wiring on the circuit board which has many restrictions on the mounting auxiliary film, the density of the wiring can be reduced.
【図１】本発明の一実施例を示す分解斜視図及び一実施
例に使用する実装用補助フイルムの分解斜視図である。FIG. 1 is an exploded perspective view showing an embodiment of the present invention and an exploded perspective view of a mounting auxiliary film used in the embodiment.
１，９ 配線 ２ 絶縁フイルム ３ 位置合わせマーク ４ 半導体装置 ５ 実装用補助フイルム ６ ランド ７ 回路基板 １０，１１，１２ 電極 １３ 開孔部 DESCRIPTION OF SYMBOLS 1, 9 Wiring 2 Insulating film 3 Alignment mark 4 Semiconductor device 5 Auxiliary film for mounting 6 Land 7 Circuit board 10, 11, 12 Electrode 13 Opening
Claims (1)
てこれら配線に接続され上面に回路素子搭載用の電極お
よび下面に回路基板接続用の電極を設けた実装用補助フ
ィルムと、前記回路基板接続用の電極と接続するランド
および配線が上面に設けられ前記実装用補助フィルムを
搭載し実装する回路基板とを有することを特徴とする混
成集積回路。1. A wiring is provided between layers of a plurality of insulating films and connected to these wirings, and electrodes and electrodes for mounting circuit elements are provided on the upper surface .
A mounting assisting film provided with electrodes for a circuit board connected to the lower surface and the land to be connected to the electrode for the circuit board connection
And hybrid integrated circuit wiring and having a circuit board you mounting the mounting assisting film provided on the upper surface mounting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3085631A JP2697345B2 (en) | 1991-04-18 | 1991-04-18 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3085631A JP2697345B2 (en) | 1991-04-18 | 1991-04-18 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04318998A JPH04318998A (en) | 1992-11-10 |
| JP2697345B2 true JP2697345B2 (en) | 1998-01-14 |
Family
ID=13864186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3085631A Expired - Lifetime JP2697345B2 (en) | 1991-04-18 | 1991-04-18 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2697345B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6371579U (en) * | 1986-10-30 | 1988-05-13 |
-
1991
- 1991-04-18 JP JP3085631A patent/JP2697345B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04318998A (en) | 1992-11-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970819 |