JP2687349B2 - Digital PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a digital PLL circuit that digitally performs a PLL (Phase Locked Loop) operation. The present invention relates to a digital PLL circuit that can maintain high accuracy even when the frequency is low. B. Summary of the Invention The present invention obtains pulse period data based on the phase error detection data between the final output clock and the input signal and the output clock period detection data, and uses this pulse period data as a master of a constant frequency. In a digital PLL circuit that counts with a clock and generates an output clock pulse,
By detecting N cycles of the output clock pulse (N is an integer of 2 or more) and 1 / N the cycle of the N pulses to obtain the above output clock cycle data, the lock range of the PLL is widened. This is tolerant to jitter, which is substantially the same as the effect of increasing the frequency of the master clock. C. Prior art When reading data from a signal (input signal) obtained by transmitting or recording / reproducing a digital signal, it is necessary to synchronize a clock for extracting bits (so-called bit clock). It In order to obtain a clock signal with a cycle for such an input signal,
A PLL (Phase Locked Loop) circuit is used. In recent years, a digital PLL circuit has been proposed that digitally performs the operation inside the PLL circuit. Here, in general, a digital PLL circuit counts and detects a time difference between an edge (transient) of an input signal and an output clock generated inside the circuit, or a so-called phase error, by detecting it with the accuracy of a high-speed master clock. The phase of the output clock from the inside of the circuit is controlled to synchronize with the clock (bit clock) of the input signal. In this case, the master clock is generally required to have an accuracy higher than that of the bit clock by one digit or more. That is, generally, the PLL circuit detects the phase error between the input signal and the output clock and controls the frequency of the output clock signal according to the detected phase error. In this case, the phase error is detected and the output clock frequency is controlled based on the master clock. For example, corresponding to an analog phase comparator, the time between the edge of the input signal and the output clock pulse is counted by the master clock to obtain quantized phase error data. Corresponding to the VCO (voltage controlled oscillator) of, by dividing the master clock and changing the division ratio with the phase error data,
An output clock whose period is controlled in units of the master clock period is obtained. Therefore, if the master clock frequency is sufficiently higher than the frequency of the clock component of the input signal, the phase error detection accuracy and the output clock cycle change accuracy can be obtained. D. Problems to be Solved by the Invention However, the master clock frequency f _MS is also limited due to the limitation of the operation speed of the elements of the PLL circuit, and the clock frequency f _IN of the input signal is, for example, about several MHz or more. When it is high, the frequency f _MS may be only a few times higher than the frequency f _IN . In this case, the change width of the frequency f _OUT of the output clock with respect to the master clock is coarse, and there is a possibility that the above-mentioned time difference or so-called phase error cannot be detected normally. In particular, there is a problem in clock interpolation of a waveform having a long interval between edges (transients) of the input signal. This will be specifically described with reference to FIG. Third
The figure shows some examples of output clocks from the digital PLL circuit when the frequency f _MS of the high speed master clock CK _MS is set to 5 times the frequency f _BT of the bit clock CK _BT of the input signal. First, the output clock CK _{OUTO of} FIG.
Is the PL in an ideal state where the input signal does not include jitter, etc.
L output is shown, and the frequency f _OUTO of the output clock CK _OUTO at this time is the frequency f _MS of the master clock CK _MS.
It is 1/5. On the other hand, during the actual PLL operation, the output clock frequency f _OUT is controlled according to the phase error between the clock component in the input signal and the output clock. The output clock frequency f _OUT is controlled by the master clock CK above.
_Since it is performed by changing the division ratio of _MS ,
When the frequency division is the reference, the output clock CK _OUT may change to, for example, 1/4 frequency division output or 1/6 frequency division output of the master clock CK _MS during the actual PLL operation. In the example of FIG. 3, the output clock CK _OUT1 is the master clock CK _MS.
Output clock CK
_OUT2 indicates the one obtained by _dividing the master clock CK _MS by 1/6. Here, the signal (edge detection signal) S _ED obtained by edge detection of the input signal in FIG.
When there is a pulse interval (edge interval of the input signal) that is four times the cycle T _OUTO of the output clock CK _OUTO , the output clock CK _OUT1 obtained by dividing the master clock CK _MS by 1/4. In some cases, it is erroneously determined to be 5 times the cycle T _OUT1 , and the master clock CK _{MS is set} to 1/6.
Depending on the _divided output clock CK _OUT2 , its cycle T
It will be erroneously judged to be about 3 times that of _OUT2 . That is,
Not only is it vulnerable to fluctuations in the bit clock frequency due to input signal jitter, etc., but it is also vulnerable to noise, resulting in a PLL with a narrow lock range and capture range. The present invention has been made in view of such circumstances, and it is possible to obtain the same operation accuracy as that when the master clock frequency is substantially increased, and it is stable even at a master clock frequency of several times the bit clock frequency. The purpose of the present invention is to provide a digital PLL circuit that can have a wide lock range. E. Means for Solving the Problems In order to solve the above-mentioned problems, the PLL circuit according to the present invention is a phase error correction indicating a phase error between the output clock pulse from the output clock generating means and the input signal. The phase error detecting means for outputting data and the master clock are counted within a period in which N (N is an integer of 2 or more) pulses of the output clock pulses generated by the output clock generating means are output, and the count value is counted. Is a digital PLL circuit provided with an output clock cycle detecting means for detecting output clock cycle data by multiplying by 1 / N, wherein the output clock generating means is the phase error correction data output from the phase error detecting means. And the output clock cycle data detected by the output clock cycle detecting means and the addition output result for performing cumulative addition are input. The adding means for calculating the data, and the comparing means for comparing the variable cycle accumulated data from the adding means with the count value of the master clock having a constant frequency, the comparing means include the variable cycle from the adding means. Each time the accumulated data and the count value of the master clock having a constant frequency substantially match, the matched count value is output to the output clock cycle detecting means as an output clock pulse. Here, there is provided one-cycle computing means for computing the variable cycle cumulative data from the adding means and the output clock cycle data from the output clock cycle detecting means, and the calculation result in the one-cycle computing means and the master. It is preferable to determine the phase shift detection range based on the clock count value. F. Action Since the period in which N of the output clock pulses are output is counted by the master clock, the count value is multiplied by 1 / N to obtain the output clock cycle data. Therefore, calculation for PLL operation is performed. The accuracy is substantially increased to N times. G. Embodiment Hereinafter, an embodiment of the digital PLL circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a block circuit diagram showing an embodiment of the present invention. In FIG. 1, an input terminal 1 of the phase error detection circuit unit 10 is supplied with a signal S _{IN which} is reproduced from a recording medium and whose waveform is equalized. This input signal S _IN has a bit clock frequency f _BT of, for example, 9.4 MHz,
The signal S at an interval that is an integer multiple of the period T _BT of this bit clock.
_IN edge (transient) is obtained. This input signal _SIN is sent to the edge detection circuit 11, where the edge of the signal waveform is detected. The output from the edge detection circuit 11 is sent to the shift register 21 and converted into parallel data, and the phase error is caused by passing through the latch circuit 13, the area select circuits 14a and 14b, the position / numerical value conversion circuit 15 and the filter 16. Is detected. The input terminal 2, an integral multiple of the frequency of the frequency f _BT
f _MS , for example 56.4 MHz (= 6f _BT ) high-speed master clock C
K _MS is supplied. This master clock CK _MS is sent to the edge detection circuit 11 and shift register 12 of the phase error detection circuit section 10 and at the same time the final output clock
Counter 2 of output clock generation circuit section 20 that generates CK _OUT
Sent to one. The count output from this counter 21 is
It is sent to the comparator 22, and is compared with the variable cycle accumulated data from the adder 23 in the comparator 22. This adder 23
The three inputs are added, and the addition output is returned to one input via the latch circuit 24 to perform cumulative addition. The phase error correction data from the phase error detection circuit section 10 and the detection cycle data from the cycle data detection circuit section 30 are supplied to the other two inputs of the 3-input adder 23. The cycle data detection circuit unit 30 detects the cycle T _OUT of the output clock CK _OUT , and conventionally counts the number of pulses of the master clock CK _MS between the pulses of the output clock CK _OUT (within one cycle). The cycle T
_{Although OUT} is detected, in the embodiment of the present invention, a cycle of a predetermined number N (N is a natural number of 2 or more) of the pulses of the output clock CK _OUT. The cycle detection accuracy (or resolution) is substantially increased to N times by counting (using N · T _OUT for simplification of description) with the master clock CK _MS and multiplying the count value by 1 / N. ing. That is, the output clock CK _OUT (frequency f _OUT ) from the output clock generation circuit unit 20 is
To the N-ary counter (or 1 / N divider) 31 of the frequency f _OUT (the cycle is N · T
_OUT ), and the count output is sent to the zero clear terminal (reset terminal) of the counter 32.
This is the counter 32 and the master clock CK _MS is supplied, so that the number of pulses of the master clock CK _MS during the period N · T _OUT of the count output is counted.
The count output from the counter 32 is based on the period T of the output clock CK _OUT in units of the master clock CK _MS.
The output clock cycle data can be obtained by measuring a period N times _OUT and multiplying this count output value by 1 / N. Here, N of the N-ary counter 31 is 2 ⁿ (n is a natural number)
By setting the value to the power of 2 as shown in the above, the operation of 1 / N times the count output value from the counter 32 is performed as a bit.
All that is required is a shift operation or a change in the position of the decimal point for parallel output data. For example, the decimal number N of the counter 31 is 16
When (= 2 ⁴ ) is set, the lower 4 bits may be regarded as a value after the decimal point in order to multiply the count output value from the counter 32 by 1/16. The output clock cycle data (1/16 of the count output value) from the counter 32 thus obtained is sent to the adder 23 of the output clock generation circuit section 20 via the latch circuit 33. Regarding the data handled by the adder 23, for example, the above-mentioned 4 bits of 8-bit parallel data are regarded as the integer part and the lower 4 bits are regarded as the decimal part, and the comparator 22 receives the data of the upper 4-bit integer part. I am trying to send only. The area select circuits 14a and 14b in the phase error detection circuit section 10 correspond to a range of one cycle of a clock as a range in which a phase error is to be detected, of the parallel data obtained from the latch circuit 13. The data from the area select circuits 14a and 14b are ORed.
It is sent to the JK flip-flop 18 via the circuit 17. The clock input terminal of the JK flip-flop 18 is supplied with the output clock CK _OUT , and the JK flip-flop 1
The Q output of 8 becomes the reproduction data output. Here, the area select circuits 14a and 14b are supplied with the one-cycle range data from the one-cycle arithmetic circuit 19. The one-cycle arithmetic circuit 19 calculates the one-cycle range data by adding or subtracting 1/2 of the output clock cycle data from the latch circuit 33 to the output of the adder 23. There is. That is, the output clock generation circuit section 20 cumulatively adds the output clock cycle data from the cycle data detection circuit section 30 by the 3-input adder 23 and the latch circuit 24,
The cumulative value of the output clock cycle data is obtained, and an output clock pulse is output from the comparator 22 every time the count output from the counter 21 matches the above cumulative value, and the phase error correction data from the phase error detection circuit unit 10 is used. The cumulative value of the output clock cycle data is corrected. With respect to the cycle data at this time, the detection accuracy is increased N times by counting the period in which N output clock pulses are output by 1 / N after counting by the master clock. Next, an example of a specific operation of the digital PLL circuit having the above configuration will be described with reference to FIG. In the concrete example of FIG. 2, the output clock cycle data from the counter 32 is displayed in hexadecimal decimal point notation.
"5.D (h)", that is, the integer part is "5 (h)", and the decimal part is "D (h)" (decimal number 13, that is, 13/16). Here, (h) indicates that it is a hexadecimal display value. First, when the output of the adder 23 is "B.4 (h)",
The comparator 22 is supplied with the integer part data “B (h)” and compared with the output of the counter 21. Therefore, the counter
A coincidence output is obtained from the comparator 22 at the timing t _{1 when} the output from 21 becomes “B (h)”, and this coincidence output causes the accumulation latch at the timing t ₂ at the trailing edge of the master clock cycle.
Since 24 operates and the addition output “B.4 (h)” is supplied to the adder 23, this “B.4 (h)” and the output clock cycle data “5.D (h)” are Is added. In this case B.4
(H) + 5.D (h) = 11.1 (h) and 9-bit data, but because it is 8-bit digital addition,
The lower 8 bits "1.1 (h)" are the addition output. The higher-order 4-bit integer part data “1 (h)” of the addition output is sent to the comparator 22 and compared with the output of the counter 21, so that the output from the counter 21 is “1 (h)”. At timing t _{4, a} coincident output is obtained from the comparator 22, and at the next timing t ₅ , the current addition output “1.1 (h)” becomes the output clock cycle data “5.D (h)”. Addition (8
The bits are digitally added), and the addition output of "6.E (h)" is obtained. Similarly, every time the addition output from the adder 23 and the output from the counter 21 match, a coincidence output is obtained from the comparator 22, which becomes the output clock CK _OUT . On the other hand, the center output S of the shift register 12 is
_{When MD} is obtained as shown in Fig. 2, this output S
_In order to detect the amount of deviation (so-called phase error) between _MD and each pulse of the output clock CK _OUT , it is necessary to determine the range in which this deviation is detected. This is because each pulse of the output clock CK _OUT (for example, the pulses P _OUT1 , P _{OUT2 of} FIG. 2) is detected when the phase error of the pulse of the output S _MD (for example, the pulse P _{MD of} FIG. 2) is detected. This is equivalent to determining which of the pulses from which the amount of deviation should be detected. Therefore, for each pulse P _OUT1 , P _OUT2, etc. The phase shift of the pulse of the output S _MD existing in each detection range is detected. That is, in the example of FIG. 2, the one-cycle range data from the one-cycle arithmetic circuit 19 indicates the phase shift detection range (for example, the end) determined corresponding to the pulse of the output clock CK _{OUT as} the counter. It is expressed by the count number of the above master clock according to 21. Above adder
When the output of 23 is "B.4 (h)", the range data for one cycle is "E.2 (h)", and the counter 21
Detects the phase shift between the pulse of the signal S _MD obtained within the range up to the timing t _{3 at} which the output from the above becomes “E (h)” and the output clock pulse obtained at the time t _1. In this way, the phase shift of the pulse of the signal S _MD obtained after the time t ₃ from the output clock pulse obtained at the next time t ₄ is detected. In this manner, the second diagram the time t ₃ of, t _6, t _9, ‥‥ is determined, the detection range of the phase shift corresponding to each pulse of the output clock CK _OUT is t ₃ ~t _6, t ₆ ~ T ₉ and so on. In the circuit configuration of FIG. 1, since the time series data is converted into parallel data by the shift register 12,
Each time range _{t 3 ~t 6, t 6 ~t} 9, the corresponding bit line areas select circuit 14a to ‥‥, so that selecting the phase shift detection range by selecting at 14b. The OR output of the outputs from the area select circuits 14a and 14b and the central bit line output S _MD , that is, the OR circuit 1
The output from 7 indicates whether or not the pulse of the signal S _MD exists within the detection range of the phase shift corresponding to each pulse of the output clock CK _OUT , and the output S _{OR of} FIG. Become. By sending this output S _OR to the JK flip-flop 18, the input signal supplied to the input terminal 1
The data output signal D _OUT obtained by reading the contents of S _IN can be obtained from the output terminal 4. According to the digital PLL circuit as described above, when the period of the output clock CK _OUT is detected, N pulses are counted by the master clock CK _MS , and the count value is 1 / N, thereby substantially Master clock frequency f _MS is N
It is possible to obtain the same cycle detection accuracy as when it is doubled to N · f _MS . Output clock detected with this high accuracy
The cycle T _{OUT of} CK _OUT has a fractional part, and by performing the calculation in the adder 23 including the part after the decimal point, the precision calculation can be increased to N times that of the conventional one. That is,
The output clock generation circuit unit 10 and the period data generation circuit unit 30 correspond to the VCO (voltage controlled oscillator) of the analog PLL, and the period from the period data generation circuit unit 30 that determines the oscillation frequency of this portion. Count the master clock for N periods of output clock pulse
By 1 / N, the detection accuracy of the frequency of the output clock is substantially increased N times. Therefore, even with a relatively low master clock, it is possible to provide a PLL circuit that has a wide lock range and a wide capture range, and is resistant to fluctuations in the bit clock frequency due to jitter of input data. It should be noted that the present invention is not limited to the above-described embodiments, and it goes without saying that the clock frequencies and the like are limited to the above-mentioned examples. In addition, various changes can be made without departing from the spirit of the present invention. H. Effect of the Invention According to the digital PLL circuit of the present invention, it is possible to obtain substantially the same accuracy as when the master clock frequency is increased, and a master clock having a frequency about several times the clock frequency of the input signal is used. Even in this case, a PLL circuit with a wide lock range and strong jitter can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block circuit diagram showing an embodiment of a digital PLL circuit according to the present invention, FIG. 2 is a flow chart for explaining the operation of the embodiment, and FIG. 5 is a flowchart for explaining a PLL operation. 10 ...... Phase error detection circuit section 11 ...... Edge detection circuit 12 ...... Shift register 14a, 14b ...... Area select circuit 20 ...... Output clock generation circuit section 21 ...... Counter 22 …… Comparator 23 …… 3 input addition Unit 30 …… Cycle data detection circuit 31, 32 …… Counter

Claims (1)

(57) [Claims] Phase error detection means for outputting phase error correction data indicating a phase error between the output clock pulse from the output clock generation means and the input signal, and N output clock pulses generated by the output clock generation means (where N is N A digital PL including an output clock cycle detecting means for counting the master clock within a period in which a pulse of 2 or more) is output and multiplying the count value by 1 / N to detect output clock cycle data.
In the L circuit, the output clock generation means includes phase error correction data output from the phase error detection means, output clock cycle data detected by the output clock cycle detection means, and addition for performing cumulative addition. The comparing means for comparing the variable cycle cumulative data from the adding means with the count value of the master clock having a constant frequency; Each time the variable cycle accumulated data from the adding means and the count value of the master clock having a constant frequency substantially match, the matched count value is output to the output clock cycle detecting means as an output clock pulse. And digital PLL circuit. 2. There is provided one-cycle arithmetic means for adding the variable cycle accumulated data from the adding means and the output clock cycle data from the output clock cycle detecting means, and the calculation result in the one-cycle arithmetic means and the master clock count. The digital PLL circuit according to claim 1, wherein the phase shift detection range is determined based on the value.