JP2684815B2 - Digital multiplex transmission system - Google Patents

Description

TECHNICAL FIELD The present invention relates to a digital multiplex transmission system.

[Prior Art] With the widespread use of optical communication in recent years, many applications such as multi-channel multiplex transmission systems for digital moving images, which make full use of its wide band property, have begun to be developed.

The transmission speed of digital moving images is 10 per channel.
It is about 0 Mbps, and if this is multiplexed for four channels for optical transmission, a 400 Mbps optical transmission system is required.

Generally, in order to optically transmit digital data, it is necessary to perform code conversion of digital data into a form suitable for optical transmission, and one of such code conversion systems is nBmB code conversion.

In this code conversion, according to a predetermined rule, an encoder (code conversion device) converts n bits into m bits (m>
It is converted to n) so that 1s and 0s do not continue.

When the above 4-channel digital image transmission is performed using 8B10B code conversion, the transmission rate after encoding becomes 500 Mbps. However, 8B10B that performs signal processing at 500 Mbps
Encoders are currently difficult to obtain.

Therefore, using two 8B10B encoders that can operate at 250 Mbps, code conversion is performed at 250 Mbps, and the resulting 2
500 Mb by multiplexing two serial 8B10B code strings
A transmission method that secures the ps transmission rate is conceivable.

As a conventional example, FIGS. 2 to 4 show a digital multiplex transmission system using such a transmission method.

FIG. 2 shows an example of a multiplexing circuit on the transmission side. Reference numerals 15 and 16 in the figure are logical processing units for generating an original data string (transmission data), and 21 and 22 are 8B10B code conversions. It is an encoder to perform. Reference numeral 26 is a multiplexer that time-division multiplexes two code strings (serial data strings) and outputs one serial data string.

The logic processing units 15 and 16 output original data strings 17 and 18 (each of which is a multiplexed digital image signal of 2 channels) using clocks 19 and 20 input from encoders 21 and 22, respectively. To do. This is encoded by the encoders 21 and 22, and two 8B10B code strings 23 and 24 are output.

The signal line 25 is a basic clock for operating the encoders 21 and 22 and is set to 250 MHz when the finally desired transmission speed is 500 Mbps. As a result, the processing speed in the encoders 21 and 22 can be set to 250 Mbps, and
The 8B10B code string of the book is multiplexed in the multiplexer 26 to obtain a serial data string of 500 Mbps, and the serial data string is transmitted from the output terminal 27.

FIG. 3 shows the format of the serial data string (serial signal string) 28 thus multiplexed.

This is based on the so-called bit multiplexing method, and the code strings DO _n , DO _{n + 1} , DO _{n + 2} , ... By the encoder 21 and the code strings DI _n , DI _{n + 1} , DI _{n +} by the encoder 22. ₂ , ... Are alternately multiplexed for each bit.

This serial data string 28 is transmitted to a remote receiving place via a transmission line such as an optical fiber.

At the receiving side, the multiplexed serial data string 28 is separated / decoded by the demodulation circuit shown in FIG.

In FIG. 4, reference numeral 1 is an input terminal for receiving the serial data stream 28 described above, 2 is a demultiplexer for demultiplexing the serial data stream 28, and 6 and 7 are based on the data converted by the nBmB encoder. It is an 8B10B decoder that performs code conversion to return to. Reference numeral 14 is a logical processing unit that processes the decoded original data string.

500 Mbps serial data string 2 that entered the input end 1 from the transmission line
Demultiplexer 2 separates 8 into two 8B10B code strings 4 and 5 having a transmission speed of 250 Mbps.

Reference numeral 3 is a 250 MHz clock indicating the change point of this 8B10B code string. The decoders 6 and 7 decode the 8B10B code and output decoded data sequences 10 and 11 (each of which is a multiplexed digital image signal of two channels and corresponds to an original data sequence on the transmission side). .

Reference numerals 8 and 9 are clocks indicating the change points of the decoded data strings 10 and 11.

The logic processing unit 14 uses the clocks 8 and 9 to perform data processing such as separation of multiplexed digital image signals.

[Problems to be Solved by the Invention] In the digital multiplex transmission system configured as described above, 8B1 of 250 Mbps which is easily available at a low price
It seems that by using two 0B encoders, high-speed transmission of 500 Mbps can be realized economically. However, in reality, it could not be realized because of the following reasons.

The encoders 21 and 22 on the transmission side have respective logical processing units 15 and 16 respectively.
The header pattern is sent according to the header pattern transmission instruction (for transmission synchronization) output by the
Each of 6 and 7 detects the header pattern sent by the encoders 21 and 22, and adjusts the timing of serial / parallel conversion at the time of detection to synchronize transmission and reception.

That is, the decoded data string input to the logical processing unit 14 on the receiving side
The phases of 10 and 11 are determined by the header pattern transmission instruction output from the logical processing units 15 and 16 on the transmission side.

However, since the logical processing units 15 and 16 on the transmission side operate independently of each other and output the header pattern transmission instruction at arbitrary timings, the output of the header pattern transmission instruction from these logical processing units 15 and 16 is performed. It is possible that the timings do not match.

And in such a case, inevitably the decoders 6,7
The timing adjustment of the serial / parallel conversion in is also performed at different timings, and as a result, the phases of the two types of decoded data strings 10 and 11 input to the logical processing unit 14 on the receiving side are different, This is because a problem occurs that normal logical processing cannot be performed on two types of data strings.

FIG. 5 illustrates a case where such a problem occurs.

In FIG. 5, (a) is the parallel decoded data 10 output from the decoder 6, (b) is the clock 8 indicating the change point of the decoded data 10, and (c) is the parallel output from the decoder 7. Decoded data 11 and (d) are clocks 9 indicating the change points of the decoded data 11. This illustrated example shows that the timings of serial / parallel conversion after detecting the header pattern are different between the decoders 6 and 7.

When the two types of data strings have different phases from each other as described above, normal logical processing may not be performed on the two types of data strings.

The present invention has been made in view of the above circumstances, and an object thereof is to make it possible to realize a digital multiplex transmission system of a format in which outputs of a plurality of nBmB encoders are multiplexed and transmitted, that is, Since a plurality of nBmB encoders on the transmission side in the system output header patterns independently of each other, even if a phase shift occurs between the decoded data strings on the receiving side, those decoded data strings are logically processed normally. In order to enable economical high-speed multiplex transmission.

[Means for Solving the Problems] In the digital multiplex transmission system according to the present invention, on the transmission side, a logical processing unit for outputting an original data string and n-bit data for the original data string are converted into m-bit data. Multiple nBmB encoders for conversion are provided, and multiple nBmB encoders
A plurality of code strings obtained by the encoder are time division multiplexed by a multiplexer and output as one serial data string.

On the other hand, on the receiving side, a received serial data string is demultiplexed into a plurality of code strings by a demultiplexer, and each separated code string is a code conversion that restores the data converted by the nBmB encoder. Are individually decoded by a plurality of nBmB decoders, and processed by a common logic processing unit.

However, on the receiving side, one of the nBmB decoders is used as a master, and the output data of the master nBmB decoder is directly input to the logic processing unit, but the output data of each nBmB decoder other than the master is input. Are to be input to the logic processing unit via buffer means capable of asynchronous writing and reading.

Then, the writing of the output data of the nBmB decoder other than the master to each buffer means is performed by the clock indicating the change point of each output data, and the reading from each buffer means changes the change point of the output data of the master nBmB decoder. It is performed by the clock shown.

[Operation] In the digital multiplex transmission system according to the present invention, one of a plurality of receiving side nBmB decoders is selected as a master,
The output data of the master nBmB decoder is directly input to the logic processing unit at the clock indicating its own change point, but the output data of all non-master nBmB decoders is once written to the buffer at the clock indicating its own change point. , Read from the buffer at the clock of the master nBmB decoder and input to the logic processing unit.

Therefore, the output data of all nBmB decoders that are not the master B are synchronized with the output data of the master nBmB decoder at the clock of the master nBmB decoder, and as a result, all the decoded signals separated at the receiving side are synchronized. The data strings are phase-compensated and input to the logic processing unit in a state of being synchronized with each other.

Therefore, even if a plurality of nBmB encoders on the transmission side send header patterns independently of each other, and even if a phase difference occurs between the decoded data strings on the receiving side, those decoded data strings are logically processed normally. It is possible to use multiple nB
It became possible to realize a digital multiplex transmission system in which the output of the mB encoder is multiplexed and transmitted, and economical high-speed multiplex transmission has become possible.

[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

In the digital multiplex transmission system of this embodiment, part of the device configuration on the receiving side is improved as compared with the conventional system, and the device configuration on the transmitting side is the same as the conventional one.

Therefore, the transmitting side is provided with a plurality of sets of a logical processing unit that outputs an original data sequence and an nBmB encoder that converts n-bit data into m-bit data for the original data sequence. The device configuration is such that a plurality of code strings obtained by the nBmB encoder are time-division multiplexed by a multiplexer and are output as one serial data string.

Specifically, as shown in FIG. 2, when two logical processing units 15 and 16 are provided, two nBmB encoders 21 and 22 paired with the respective logical processing units, An original data string 17, which is output from the logic processing units 15 and 16, has a device configuration including a multiplexer 26 that multiplexes the outputs of these two encoders.
18 is code-converted by each nBmB encoder 21 and 22, and the result is 2
The code strings 23 and 24 of the book are multiplexed by the multiplexer 26,
It is output as the serial data string 28 shown in FIG.

On the other hand, on the receiving side, a received serial data string is demultiplexed into a plurality of code strings by a demultiplexer, and each separated code string is a code conversion that restores the data converted by the nBmB encoder. Although the device configuration is such that it is individually decoded by a plurality of nBmB decoders that perform the above, and is processed by a common logic processing unit, improvements have been made between the plurality of nBmB decoders and the logic processing unit.

A specific description will be given based on FIG. The device configuration in FIG. 1 corresponds to the device configuration on the transmission side in FIG. 2, and the same parts as those in FIG. 4 are denoted by the same reference numerals.

On the receiving side, when one received serial data string 28 enters the input terminal 1, the demultiplexer 2 demultiplexes it into two code strings 4,5, and each separated code string 4,5 is two units. NBmB decoders 6 and 7 are individually decoded. In addition, 3 is a code string 4,5
It is a clock of 250MHz that shows the change point of.

Here, of the two nBmB decoders 6 and 7, one nBmB decoder 7 is set as a master and the nBmB of this master is
The decoded data string 11 which is the output data of the mB decoder 7 is directly input to the logic processing unit 14 together with the clock 9 which indicates the change point, but the decoded data string 10 which is the output data of the other nB mB decoder 6 has its change. Once with the clock 8 showing points
Input to FIFO (First In First Out) memory 12.

The FIFO memory 12 is a buffer means of a type capable of asynchronous writing and reading. The decoded data string 10 output from the nBmB decoder 6 is temporarily held in the FIFO memory 12 and then the decoded data string 13 is stored. Is input to the logic processing unit 14.

In this case, the decoded data string 10 output by the decoder 6
Writing to the FIFO memory 12 is performed by the clock 8 indicating the change point of the decoded data string 10, while the FIFO memory 12
Reading of the decoded data string 13 from 12 is performed by the clock indicating the change point of the decoded data string 11 of the master decoder 7.

In the system having the above configuration, the logical processing units 15 and 1 on the transmitting side are
6 independently issues a header pattern transmission instruction at different timings. Therefore, the two encoders 21 and 22 send the header patterns at different timings, and the decoded data strings 10 and 11 on the receiving side are mutually transmitted. Even if there is a phase shift in, the decoded data strings 11 and 13 that are input to the logical processing unit 14 on the receiving side are synchronized in phase by the clock 9, so that the decoded data strings 11 and 13 are normally processed. It can be processed logically.

In other words, in the above embodiment, the output data of the master decoder 7 is directly input to the logic processing unit 14, but the output data of the non-master decoder 6 is a buffer means capable of asynchronous writing / reading. It is assumed that the data is input to the logic processing unit 14 via the FIFO memory 12, and in this case, the output data of the decoder 6 which is not the master is read from the FIFO memory 12 by the clock indicating the change point of the output data of the master decoder 7. By doing two decoders
It is designed to execute phase compensation between output data from 6 and 7, and by this phase compensation, logical processing can be normally performed, and the outputs of multiple nBmB encoders are multiplexed and transmitted. It has become possible to realize a digital multiplex transmission system of the type described above, and economical high-speed multiplex transmission has become possible.

In the above-described embodiment, the FIFO memory 12 is used as a buffer means of a type capable of asynchronous writing and reading in order to hold the output data of the non-master decoder, but instead of the FIFO memory 12, A RAM (Random Access Memory) having an address generating means may be used.

The number of encoders and decoders installed in the system is
The number of encoders and decoders may be three or more, without being limited to the illustrated embodiment.

In addition, when the number of encoders and decoders is three or more, on the receiving side, any one decoder is used as a master,
The output data of the master decoder is directly input to the logic processing unit 14, but the output data of each decoder other than the master is input to the logic processing unit 14 via asynchronous write / read buffer means. And Then, the output data of the decoder other than the master is written to each buffer means by the clock indicating the change point of each output data, and the reading from each buffer means indicates the change point of the output data of the master decoder. It should be done with a clock.

[Effects of the Invention] As is clear from the above description, in the digital multiplex transmission system according to the present invention, one of a plurality of receiving side nBmB decoders is selected as the master, and the nBmB decoder serving as the master is selected. The output data of each is directly input to the logic processing unit at the clock indicating the change point of itself, but all the output data of the non-master nBmB decoders are once written in the buffer at the clock indicating the change point of each and then nBmB decoding as the master. The clock is read from the buffer and input to the logic processing unit.

Therefore, the output data of all non-master nBmB decoders is synchronized with the output data of the master nBmB decoder at the clock of the master nBmB decoder, and as a result, all the decoded data separated at the receiving side The columns are phase-compensated and input to the logic processing unit in a state of being synchronized with each other.

Therefore, even if a plurality of nBmB encoders on the transmission side send header patterns independently of each other, and even if a phase difference occurs between the decoded data strings on the receiving side, those decoded data strings are logically processed normally. It is possible to use multiple nB
It became possible to realize a digital multiplex transmission system in which the output of the mB encoder is multiplexed and transmitted, and economical high-speed multiplex transmission has become possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of the receiving side in one embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the transmitting side in the one embodiment and the conventional example, and FIG. 3 is two code strings. FIG. 4 is a format diagram of a serial data string in which data is multiplexed, FIG.
The figure is an explanatory view showing the difference in phase between the decoded data strings in the conventional example. 1 …… Input end, 2 …… Demultiplexer, 3,25 …… 250M
Hz clock, 4,5,23,24 …… code string, 6,7 …… nBmB decoder, 8,9,19,20 …… 20MHz clock, 10,11,13,17,18 ……
Raw data, 12 ... Buffer means, 14-16 ... Logic processing unit, 21, 22 ... nBmB encoder, 26 ... Multiplexer, 27
...... Output end, 28 …… Multiplexed serial data string.

Claims (1)

(57) [Claims] 1. A transmission side is provided with a plurality of sets of a logical processing unit for outputting an original data string and an nBmB encoder for converting n-bit data into m-bit data for the original data string, Multiple code strings obtained by multiple nBmB encoders are time-division multiplexed by a multiplexer and output as one serial data string. On the other hand, on the receiving side, one received serial data string is demultiplexed. Demultiplexed into a plurality of code strings, each separated code string is individually decoded by a plurality of nBmB decoders that perform code conversion to restore the data converted by the nBmB encoder to a common logic. In the digital multiplex transmission system processed by the processing unit, one of the plurality of nBmB decoders on the receiving side serves as a master, and the output data of the master nBmB decoder is directly input to the logical processing unit. The output data of each nBmB decoder other than the master is input to the logic processing unit via the asynchronous write / read buffer means, and the output data of the nBmB decoder other than the master is written to each buffer means. The digital multiplex transmission system is characterized in that a clock indicating the change point of each output data is used, and the reading from each buffer means is performed by a clock indicating the change point of the output data of the master nBmB decoder.