JP2679265B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bipolar transistor and an insulated gate field effect transistor (MOSFET) as one element.

[Conventional technology]

Conventionally, as shown in FIG. 3, a vertical npn bipolar transistor has a P-type base region 2 formed by diffusion on a low-concentration n-type semiconductor layer 1 as a collector region, and a P-type base region 2 in the P-type base region 2. High-concentration n diffused and formed like islands
A type emitter region 3 and an n-type region collector contact portion 4 formed by diffusion in a region separated from the P-type base region 2 are provided.

On the other hand, as shown in FIG. 4, the double-diffused n-channel MOSFET (DMOSFET) has a polysilicon gate 6 formed on the low-concentration n-type semiconductor layer 1 as a drain region with an insulating film 5 interposed therebetween. A P-type channel diffusion region 7 and a high-concentration n-type source region 8 formed by double diffusion by impurity implantation using the polysilicon gate 6 as a mask;
The drain contact portion 9 of the n-type region is formed so as to be diffused at a position separated from the type channel diffusion layer 7.

However, the bipolar transistor and MOSFET having the above structure have the following problems.

In the former bipolar transistor, the current mainly flows through the periphery of the bottom corner of the n-type emitter region 3, as shown by the arrow in FIG. 3, but the current hardly flows near the surface. Therefore, the laterally expanded portion of the n-type emitter region 3 does not substantially contribute as a current path and occupies a useless element area. In other words, in order to increase the current capacity, it is indispensable to increase the occupied area (scale) of the emitter region 3, resulting in an increase in element area and an increase in manufacturing cost. In addition, an effective current does not flow near the surface, but on the contrary, a reactive current called surface recombination current easily flows, and this reactive current causes a reduction in the current amplification factor (h _FE ).

In the latter DMOSFET, as shown by the arrow in FIG. 4, when a gate voltage is applied, a current is sourced through the channel inversion layer 10 formed directly under the polysilicon gate 6, that is, on the surface of the P-type channel diffusion region 7. The current flows between the region 8 and the drain contact portion 9, but no current flows on the lower surface of the P-type channel diffusion region 7. In order to increase the current capacity, it is necessary to increase the effective channel width, but with the increase in the effective channel width, the bottom area of the source region 8 that does not necessarily contribute as a current path is also increased. However, this leads to a wasteful increase in element area and an increase in manufacturing cost.

By the way, Japanese Patent Application Laid-Open No. 57-133665 discloses an insulating bipolar transistor that uses a parasitic bipolar transistor of a DMOSFET and functions as a DMOSFET for a low control voltage and as a bipolar transistor for a high control voltage. A gated field effect transistor is disclosed.

In this insulated gate field effect transistor,
When the gate voltage becomes high, the Zener diode formed on the main surface of the P-type well-shaped channel diffusion layer becomes conductive and the bipolar transistor also turns on. When the Zener diode becomes conductive, the on-current is changed. To enable as the base current of
An independent electrode short-circuited to the source electrode is provided on the channel diffusion layer at the well end on the side opposite to the well end on the DMOS section side so as to increase the base-emitter resistance of the bipolar transistor.

[Problems to be Solved by the Invention] However, the semiconductor structure disclosed in JP-A-57-133665 has the following problems.

That is, in the P-type channel diffusion layer, a majority carrier current (channel current) by the insulated gate field effect transistor flows laterally along the main surface (upper part) of the well end on the DMOS portion side, and the well-shaped source is formed. Since the minority carrier current (base current) of the bipolar transistor flows laterally in the shallow portion of the well end on the DMOS portion side corresponding to the bottom level of the region, the DM of the P-type channel diffusion layer is substantially formed.
Current flows only through one well end on the OS section side. Therefore, in order to increase the current capacity, one well end on the DMOS section side must be lengthened, resulting in a wasteful increase in element area and an increase in manufacturing cost.

Therefore, the present invention is to solve the above problems,
By forming a current path not only on the well end of the well-shaped channel diffusion layer but also on the bottom surface of the well, it is possible to effectively utilize all of the built-in area and increase the current capacity without increasing the useless element area. It is to provide a semiconductor device to be realized.

[Means for solving the problem]

In order to solve the above problems, the present invention provides a well-shaped second conductivity type region formed on the main surface side of a first conductivity type semiconductor layer and a main surface side in the second conductivity type region. A well-shaped first-conductivity-type source / emitter region, and a main surface of the second-conductivity-type region sandwiched between the first-conductivity-type semiconductor layer and the first-conductivity-type region, with a gate insulating film interposed therebetween. In a semiconductor device having a gate electrode formed as described above, and a resistor connected between the gate electrode and the second conductivity type region, the first conductivity type semiconductor layer is directly under the second conductivity type region. A high-concentration first-conductivity-type buried layer lying on the substrate, and a wall-shaped high-concentration first-conductivity-type drain extending from the main surface of the first-conductivity-type semiconductor layer on the side of the gate electrode to the first-conductivity-type buried layer. And a collector region. A polycrystalline silicon mask as a field plate can be used as the resistor.

[Action]

In the present invention, for example, when the first conductivity type semiconductor layer is an n-type layer, first, a voltage is applied to the gate electrode,
The applied voltage is the first conductivity type source / emitter region-second
When the forward operating voltage (about 0.6 V) of the pn junction in the conductivity type region is reached, a current flows through the resistor between the gate electrode and the second conductivity type region to the second conductivity type region, at which time the first If the pn junction between the conductive type semiconductor layer and the second conductive type region is in the reverse bias state, it operates as a bipolar transistor, and a current mainly flows through the bottom surface of the second conductive type region.
Even if the gate voltage is increased, the potential of the second conductivity type region is at most about the forward operating voltage than that of the first conductivity type region, and therefore the difference between the gate potential and the potential of the second conductivity type region is MOS.
The threshold voltage (V _th ) of the effect is exceeded. As a result, the channel inversion layer is formed on the surface of the second conductivity type region directly below the gate electrode, and the first inversion layer is formed through the vicinity of the surface of the second conductivity type region.
A current starts to flow to the conductive type semiconductor layer, and the operation as the DMOSFET is superimposed on the operation of the bipolar transistor.

Thus, the operation of the bipolar transistor and the DMOSFE
Since the operation of T coexists, a current flows through the entire region of the second conductivity type. In particular, in the first conductive type semiconductor layer, the high-concentration first conductive type buried layer lying directly under the second conductive type region and the first conductive type semiconductor layer from the main surface on the gate electrode side of the first conductive type semiconductor layer. Since the wall-shaped high-concentration first-conductivity-type drain / collector region reaching the type-buried layer is formed, the current path of the bipolar transistor has a well bottom of the second-conductivity-type region, the first-conductivity-type buried layer, and the wall. -Like current path through the high-concentration first-conductivity-type drain / collector region, and current through the well-bottom well and end of the second-conductivity-type region through the wall-shaped high-concentration first-conductivity-type drain-collector region Become a route. Further, the drain drift current path from the channel of the DMOSFET is not only a direct path to the wall-shaped high-concentration first conductivity type drain / collector region, but also an indirect path via the first conductivity type buried layer. Is also included. For this reason, the current of the element flows not only through the well end of the second conductivity type region but also through the bottom surface of the well. Therefore, even if the element area of the conventional scale is used, a large current can be dissolved without increasing the useless element area. Will be realized.

If the threshold voltage (V _th ) of the MOS effect is lower than the forward operating voltage between the first conductivity type region and the second conductivity type region,
The channel layer is formed first and begins to operate as a DMOSFET.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1A is a perspective view showing the structure of an embodiment in which the present invention is applied to a semiconductor integrated circuit.

In the figure, 21 is a P-type semiconductor substrate on which a high-concentration n-type buried layer 22 is buried. P-type semiconductor substrate
Low concentration n-type isolation island epitaxially grown on 23
(About 8 Ω · cm) is defined by a P-type isolation region 24 reaching the P-type semiconductor substrate 21. Reference numeral 25 is a high-concentration n-type wall layer (drain / collector region) reaching the buried layer 24, to which the collector terminal C is connected. A silicon oxide film 2 with a thickness of about 0.1 μm is formed on the isolation island 23.
A polysilicon gate 27 as a stripe-shaped gate electrode is formed via 6 and a gate terminal G is connected thereto. This polysilicon gate 27 functions as a mask for ion implantation, and a P-type base region (channel diffusion layer) 28 of boron (B) 10 ¹⁷ atm / cm ³ is formed on the surface side of the isolation island 23 by double diffusion. Further, a high concentration n-type source / emitter region 29 of about phosphorus (P) 10 ²⁰ atm / cm ³ is formed in the P-type base region 28. On the silicon oxide film 26 near the P-type isolation region 24, there is a polysilicon resistance film 30 formed at the same time as the formation of the polysilicon gate 27. One end of the polysilicon resistance film 30 is connected to the gate terminal G connected to the polysilicon gate 27, and the other end is connected to the base terminal B connected to the P-type base region 28. The source / emitter region 29 is connected to the source / emitter terminal E. In FIG. 1, the electrodes of the emitter and collector are omitted.

FIG. 1 (B) shows an equivalent circuit to the above embodiment. The wall layer and the buried layer 22 function as an n-type collector region, and the P-type base region 28 and the n-type emitter region 29 form an npn bipolar transistor Tr. On the other hand, the isolation island 23 functions as a drain / drift region,
The n-type base / emitter region 29 functions as a source region (the P-type base region 28 functions as a P-type channel diffusion region), and the polysilicon gate 27, the n-type emitter region 29 and the isolation island 23 are double layers. It constitutes a diffused insulated gate field effect transistor MOSFET. And bipolar transistor Tr and insulated gate field effect transistor
It is connected in parallel with the MOSFET.

Next, the operation and effect of the above embodiment will be described with reference to FIG.
This will be described with reference to FIG. First, a voltage higher than that of the emitter terminal E is applied to the gate terminal G, and when it reaches about 0.6 V, which is the forward operating voltage between the emitter and the base, a current flows to the P-type base region 28 through the polysilicon resistance film 30. Flows. At this time, if the base-collector is in a reverse bias state, as shown in FIG. 2A, a current starts to flow through the bottom surface of the source / emitter layer 29, and the bipolar transistor operates.

Furthermore, if the gate voltage is increased, the difference between the gate potential and the base potential exceeds the threshold voltage (V _th ) of the MOS effect.
As shown in FIG. 2B, a channel inversion layer 31 is formed on the surface portion of the P-type base region 28 directly under the polysilicon gate 27, and the channel inversion layer 31 is provided from near the surface of the source / emitter layer 29. Current begins to flow, which causes the DMOS
The operation as a FET is superimposed on the operation of the bipolar transistor. Therefore, the current flows not only from the bottom surface side of the emitter region 29 but also from the vicinity of the surface thereof, so that the current flows out from the entire region without expanding the occupied area of the emitter region 29 itself, resulting in an increase in the current capacity. . By the way, in this embodiment, the current capacity was increased by about 1.5 times although the scale was the same as that of the conventional bipolar transistor. It was also confirmed that the breakdown voltage was high. Also conventional
Compared with DMOSFET, the breakdown voltage was about the same, but the current capacity was more than three times.

When the threshold voltage (V _th ) is lower than the forward operating voltage between the emitter and the base, the channel inversion layer
30 is formed first, and the bipolar transistor operation is started after the operation of the DMOSFET is started.

[Effects of the Invention] As described above, in the semiconductor device according to the present invention, in the first-conductivity-type semiconductor layer, a high-concentration second-conductivity-type buried layer lying directly under the second-conductivity-type region, A wall-shaped high-concentration first-conductivity-type drain that reaches the first-conductivity-type buried layer from the main surface of the first-conductivity-type semiconductor layer on the gate electrode side.
Since the collector region is formed, the current path of the bipolar transistor is the current flowing through the well bottom surface of the second conductivity type region, the first conductivity type buried layer, and the wall-shaped high-concentration first conductivity type drain / collector region. The current path is a path or a current path from the well bottom surface and the well end of the second conductivity type region through the wall-shaped high-concentration first conductivity type drain / collector region. Further, the drain drift current path from the channel of the DMOSFET is not only a direct path to the wall-shaped high-concentration first conductivity type drain / collector region, but also an indirect path via the first conductivity type buried layer. Is also included. For this reason, the current of the element flows not only through the well end of the second conductivity type region but also through the bottom surface of the well, so that a large current capacity can be achieved even if the element area is of a conventional scale without expanding the useless element area. Is realized.

[Explanation of symbols]

 21 …… P-type semiconductor layer 22 …… Buried layer 23 …… Separation island 24 …… P-type isolation region 25 …… Wall layer 26 …… Silicon oxide film 27 …… Polysilicon gate 28 …… P-type base region (Channel diffusion region) 29 ... n-type source / emitter region 30 ... Polysilicon resistance film 31 ... Channel inversion layer.

Claims (1)

(57) [Claims] 1. A well-shaped second conductivity type region formed on the main surface side of a first conductivity type semiconductor layer, and a well-shaped first conductivity formed on the main surface side in the second conductivity type region. Type source / emitter region, and a gate electrode formed across a main surface of the first conductivity type semiconductor layer and the second conductivity type region sandwiched by the first conductivity type region via a gate insulating film. A resistor connected between the gate electrode and the second-conductivity-type region, a high-concentration first layer lying directly under the second-conductivity-type region in the first-conductivity-type semiconductor layer. And a wall-shaped high-concentration first conductivity type drain / collector region extending from the main surface of the first conductivity type semiconductor layer on the gate electrode side to the first conductivity type buried layer. A semiconductor device characterized by being formed.