JP2671312B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device having a trench capacitor, and more particularly to a method for improving a trench shape. SUMMARY OF THE INVENTION The present invention, when manufacturing a semiconductor device having a trench capacitor, after forming a trench in the semiconductor substrate,
It is an object of the present invention to provide a method of manufacturing a semiconductor device which can improve the trench shape by a short-time heat treatment and has a high withstand voltage of a trench capacitor and a high reliability by performing a wet oxidation to form a wet oxide film. Further, according to the present invention, the formation of the wet oxide film by the wet oxidation and the annealing treatment in the inert gas atmosphere are used together to improve the shape of the trench and adjust the impurity concentration on the surface of the inner wall of the trench. . [Prior Art] Conventionally, a capacitor that forms a capacitance of a DRAM (dynamic RAM) is composed of an interlayer insulating film (capacitor insulating film) having an area such that a predetermined capacitance is obtained on a substrate and an electrode film sandwiching the interlayer insulating film. Was laminated to form a so-called laminated structure. However, the above-mentioned multilayer structure capacitor has a high occupation rate of the area occupied on the substrate due to its structure, and is not preferable in order to miniaturize the semiconductor device. Therefore, there has been proposed a technique in which a trench is formed in a substrate and a capacitor is formed in the trench to reduce the occupied area of the capacitor on the substrate and to form a capacitor having a larger capacitance. In the so-called trench capacitor technology of forming a capacitor in the trench, the formation of a capacitor insulating film having excellent pressure resistance has been an important theme. That is, when an insulating film is formed in the trench, due to the shape of the opening edge at the entrance of the trench, the insulating film may be thinned or the electric field may be concentrated at the corner when an electric field is applied. It was supposed to cause a decline. Generally, when a trench is formed by a method such as dry etching, the opening edge of the trench entrance is formed as a shape having an acute edge portion, and the above-mentioned problems are caused by the acute edge portion. It was happening. As a method of improving the shape of the opening edge of the trench so as to have a predetermined curvature so as not to cause the above problems, there are a reactive ion etching (RIE) method and an oxidation method. The oxidation method is said to be suitable from the viewpoint of controllability. Then, conventionally, in order to improve the shape of the corner portion of the trench hole so as to have a predetermined curvature, for example, the oxidation is performed at a high temperature of 1000 ° C. or higher and under a condition that a low oxidation rate of 10 Å / min or less is satisfied. It is preferable that the stress generated in the oxide film formed by oxidation can be sufficiently relaxed. [Problems to be Solved by the Invention] However, the oxidation method at a high temperature and a low oxidation rate for performing uniform oxidation may adversely affect other portions formed on the silicon substrate, and thus the semiconductor device manufacturing It goes against the desire to reduce the temperature applied during the process as much as possible and to shorten the processing time, and there is a problem such as lack of practicality. That is, when the oxidation method for improving the trench shape is at a high temperature, redistribution of the diffusion layer is caused, and the oxidation time becomes extremely long by performing the oxidation at a lower oxidation rate. It is not preferable from the aspect. Further, when the shape of the trench is improved at a high temperature and a low oxidation rate as described above, the diffusion time for impurities introduced into the inner wall surface of the trench becomes long, and the high-concentration N ⁺ layer is well controlled. It is also very difficult to form. Therefore, the present invention has been proposed in order to solve the above-mentioned problems, and improves the trench shape by heat treatment for a short time and minimizes the redistribution of the N ⁺ layer to improve the breakdown voltage of the trench capacitor. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can be manufactured. Another object of the present invention is to make it possible to adjust the surface concentration of the N ⁺ layer, and to provide a highly reliable method for manufacturing a semiconductor device. [Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention provides a method of manufacturing a semiconductor device having a trench capacitor, including a step of forming a trench in the semiconductor device, and at least a surface of the inner wall of the trench. From the step of introducing impurities of × 10 ²¹ cm ^-3 or less, the step of forming a wet oxide film by performing wet oxidation, the step of removing the wet oxide film, and the step of forming an oxide film in the trench The impurity concentration in the trench becomes 0.
The feature is that it is 8 to 2 × 10 ¹⁹ cm ^-3 . Further, a second invention of the present invention is, in a method of manufacturing a semiconductor device having a trench capacitor, comprising a step of forming a trench in a semiconductor substrate and introducing impurities of 1 × 10 ²¹ cm ⁻³ or less into at least a trench inner wall surface. The step of forming a wet oxide film by performing wet oxidation, the step of annealing in an inert gas atmosphere, the step of removing the wet oxide film, and the step of forming an oxide film in the trench. And the impurity concentration in the trench is 0.8 to 2 × 10 ¹⁹ c
It is characterized by setting to m ^-3 . Here, the heat treatment temperature when performing wet oxidation is 900 ° C to 100 ° C.
The temperature is 0 ° C, and the oxidation rate is 10Å / min to 100Å / min. Further, examples of impurities introduced into the surface of the inner wall of the trench include arsenic, phosphorus and antimony. As a method of introducing, for example, a solid phase diffusion method in which a thin film of arsenic glass is formed and then heated and diffused is applied. To be done. The impurity concentration on the inner wall surface of the trench is 0.8 × 10 ¹⁹ to 2 × 1.
It is preferable that the concentration is within the range of ^{19 19} cm ^-3 , and therefore, the concentration of impurities previously introduced prior to wet oxidation is 1
It is preferably × 10 ²¹ pieces cm ^-3 or less. This impurity concentration is set according to the device requirements. If the impurity concentration on the inner wall surface of the trench is 0.8 × 10 ¹⁹ cm ^-3 or less, a depletion layer will be formed and the capacitance will decrease, and it will function as a capacitor. I will not be able to. When the impurity concentration on the inner wall surface of the trench is 2 × 10 ¹⁹ cm ⁻³ or more,
The withstand voltage of the capacitor is significantly lowered, and it becomes very difficult to control the film thickness of the capacitor insulating film. In order to set the impurity concentration on the inner wall surface of the trench within the above range, the impurity concentration introduced in advance is set to a predetermined value in consideration of the final impurity concentration so that the target impurity concentration is obtained during wet oxidation. Alternatively, after the wet oxidation, annealing treatment in an inert gas atmosphere may be performed to finely adjust the impurity concentration, and the impurity concentration introduced in advance may have a degree of freedom. The practical heat treatment concentration when performing this annealing treatment is 900 ℃ ~ 100
0 ° C. When the heat treatment temperature is 900 ° C or lower, diffusion of the N ⁺ layer does not occur very well. The annealing treatment may be performed immediately after the wet oxidation, or may be performed at the final stage of the manufacturing process after removing the wet oxide film or after forming the capacitor insulating film. [Operation] In the present invention, since the wet oxidation method is performed after the trench is formed, the edge portion of the opening edge of the trench is removed, and the shape of the opening edge is improved so as to have a curvature. Therefore, when the capacitor insulating film is formed on this, thinning by the edge portion does not occur,
Further, electric field concentration does not occur at the edge portion, so that the withstand voltage of the capacitor is secured. Furthermore, since the wet oxidation has a high oxidation rate, the heat treatment time can be shortened and the redistribution of the N ⁺ layer can be minimized. Breakdown voltage of the trench capacitor, since it depends on the surface temperature of the N ⁺ layer, after wet oxidation, by annealing treatment, if necessary, it is possible to finely adjust the surface concentration of the N ⁺ layer, The capacity and breakdown voltage of the trench capacitor can be improved. [Examples] Hereinafter, a method for manufacturing a semiconductor device to which the present invention is applied will be described with reference to the drawings. Example 1 First, as shown in FIG. 1, an Si substrate (1) having a predetermined thickness was prepared, and a fine hole to be a trench hole (2) for forming a capacitor was formed in the Si substrate (1) by an etching method. Formed. The trench hole (2) is formed as a fine hole having a capacity such that a predetermined capacitor can be obtained, and the corner portion (3) near the entrance of the trench hole (2) and the trench hole bottom portion (4) are both acute-angled. It is formed with an angle. Then, as shown in FIG. 2, 1 × 10 ²¹ cm against the inner wall surface (5) of the trench hole formed as described above.
A high-concentration impurity of ^-3 or less was introduced by the solid phase diffusion method to form the N ⁺ layer (6). In the present invention, a solid phase diffusion method using arsenic glass is used as a method for introducing the above impurities. . Next, as shown in FIG. 3, wet oxidation was performed in an oxygen + hydrogen atmosphere to form a SiO ₂ film (7) having a film thickness of 500 Å.
The temperature condition of the wet oxidation is 900 ° C to 1000 ° C. By the wet oxidation process, the surface concentration of the N ⁺ layer (6) was adjusted to 0.8.
It was adjusted to a predetermined value of × 10 ^{19 to} 2 × 10 ¹⁹ pieces cm ^-3 . After performing the sacrificial oxidation by the wet oxidation method as described above,
As shown in FIG. 4, the oxide film was removed. Then, as shown in FIG. 5, a capacitor oxide film (8) is formed on the inner wall surface (5) of the trench hole, and polysilicon (10) is filled in the trench hole (2) to form a trench capacitor. The manufactured semiconductor device was manufactured. Example 2 Similar to Example 1, first, as shown in FIG. 1, an Si substrate (1) having a predetermined thickness was prepared, and a fine hole to be a trench hole (2) for forming a capacitor therein was prepared. The holes were formed using an etching method. The corner portion (3) near the entrance of the trench hole (2) and the trench hole bottom portion (4) are both formed with an acute angle. Then, as shown in FIG. 2, 1 × 10 ²¹ cm against the inner wall surface (5) of the trench hole formed as described above.
A high-concentration impurity of ^-3 or less was introduced by a solid phase diffusion method using arsenic glass to form an N ⁺ layer (6). Next, as shown in FIG.
Wet oxidation is performed under the temperature condition of 0 ℃ ~ 1000 ℃, and the film thickness of 500 Å
A SiO ₂ film (7) was formed. After performing the sacrificial oxidation by the wet oxidation method as described above,
Annealing treatment was applied to the inner wall surface (5) of the trench hole in an inert gas atmosphere. The inert gas used in the above annealing is nitrogen gas, and the annealing temperature is 900 ° C.
~ 1000 ° C, annealing time is 25 minutes. By performing the above-mentioned annealing treatment, the surface concentration of the N ₊ layer (6) can be increased.
It was possible to make fine adjustments to a predetermined value of 0.8 × 10 ^{19 to} 2 × 10 ¹⁹ pieces cm ^-3 . After performing the annealing treatment as described above, the oxide film was removed as shown in FIG. Then, as shown in FIG. 5, an insulating oxide film (8) is formed on the inner wall surface (5) of the trench hole, and further polysilicon (10) is filled in the trench hole (2) to form a trench capacitor. Was manufactured. By manufacturing the semiconductor device having the trench capacitor in this manner, the shape of the corner portion of the trench hole can be improved to have a curvature, and the redistribution of the N ⁺ layer can be suppressed to the minimum. Furthermore, by performing an annealing treatment after wet oxidation, fine adjustment of the surface temperature of the N ⁺ layer can be favorably performed. Comparative Example 1 A trench hole and an N ⁺ layer were formed in a substrate by the same manufacturing method as in Example 1. Then, in an oxygen atmosphere, 900
Only dry oxidation is performed under the temperature condition of ℃ to 1000 ℃, and 500 Å S
An iO ₂ film was formed. In this way, an insulating film for forming a capacitor is formed in the trench hole thus oxidized, and then polysilicon is filled in the trench hole to manufacture a semiconductor device having a trench capacitor. Comparative Example 2 A trench hole and an N ⁺ layer were formed in a substrate by the same manufacturing method as in Example 1. Then, an insulating film for forming a capacitor was formed without performing any oxidation treatment or heat treatment in the trench hole, and then polysilicon was filled in the trench hole to manufacture a semiconductor device having a trench capacitor. Using each of the semiconductor devices formed as described above, the relationship between the surface concentration of the N ⁺ layer and the breakdown voltage was examined. The results are shown in FIG. In the figure, the Δ mark corresponds to Example 1, the ▲ mark corresponds to Example 2, the O mark corresponds to Comparative Example 1, and the ● mark corresponds to Comparative Example 2. As is clear from FIG. 6, the breakdown voltage and the breakdown voltage of the trench capacitor of Comparative Example 1 produced by the dry oxidation method, which is a conventional trench capacitor forming method,
The concentration of the N ⁺ layer and the breakdown voltage and N ⁺ of the trench capacitors of Example 1 and Example 2 manufactured by using the method of the present invention.
When compared with the layer concentration, the breakdown voltage and the N ⁺ layer concentration show almost the same value. This means that the shape of the trench capacitor obtained by the dry oxidation method and the shape of the trench capacitor obtained by the wet oxidation method were substantially the same, that is, the shape of the trench capacitor obtained by the wet oxidation method was This shows that the shape of the trench capacitor obtained by the dry oxidation method is improved to be substantially equal to that of the trench capacitor. Therefore, although the wet oxidation method can be performed in a very short time of 1/2 to 1/10 when performing oxidation as compared with the dry oxidation method, it is almost equivalent to the dry oxidation method as described above. It can be said that the wet oxidation method is an excellent treatment method than the dry oxidation method because the above effect can be obtained. Further, as compared with Example 1 and Example 2, N ⁺ was obtained by performing an annealing treatment after performing wet oxidation.
The density of the layers can be fine-tuned. On the other hand, in Comparative Example 2 in which no oxidation treatment was performed, the breakdown voltage was low and the N ⁺ layer concentration was high because the shape of the trench capacitor was not improved at all. [Advantages of the Invention] As is clear from the above description, since the present invention employs the wet oxidation method, the heat treatment for improving the trench shape can be performed in a short time, and the trench shape is equal to or more than that of the dry oxidation method. Can be improved. Therefore, the redistribution of the N ⁺ layer can be suppressed to the minimum, and the adverse effect on other parts on the substrate can be suppressed. Further, in the second invention of the present invention, since the annealing treatment step for adjusting the surface concentration of the N ⁺ layer of the trench capacitor is added during the step, the surface concentration of the N ⁺ layer can be easily adjusted. Therefore, the capacitance and breakdown voltage of the trench capacitor can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 5 are enlarged cross-sectional views of essential parts showing a method of manufacturing a semiconductor device to which the present invention is applied in the order of steps thereof,
1 is a trench hole forming process, FIG. 2 is an N ⁺ layer forming process,
FIG. 3 shows a wet oxidation process, FIG. 4 shows an oxide film removing process, and FIG.
The figures respectively show the capacitor insulating film forming step. FIG. 6 is a characteristic diagram showing the relationship between the surface concentration of the N ⁺ layer and the breakdown voltage. 1 ... Substrate 2 ... Trench hole 3 ... Corner 6 ... N ⁺ layer 7 ... SiO ₂ film 8 ... Capacitor insulating film

Claims (1)

(57) [Claims] In a method of manufacturing a semiconductor device having a trench capacitor, a step of forming a trench in a semiconductor substrate, a step of introducing impurities of 1 × 10 ²¹ cm ^-3 or less into at least the inner wall surface of the trench, and a wet oxide film by performing wet oxidation. And the step of removing the wet oxide film and the step of forming an oxide film in the trench, and the impurity concentration in the trench is 0.8 to 2 × 10 ¹⁹ cm ^-3. And a method for manufacturing a semiconductor device. 2. In a method of manufacturing a semiconductor device having a trench capacitor, a step of forming a trench in a semiconductor substrate, a step of introducing impurities of 1 × 10 ²¹ cm ^-3 or less into at least the inner wall surface of the trench, and a wet oxide film by performing wet oxidation. The step of forming an oxide film in the trench, the step of annealing in an inert gas atmosphere, the step of removing the wet oxide film, and the step of forming an oxide film in the trench are performed. A method for manufacturing a semiconductor device, characterized in that the number is × 10 ¹⁹ cm ^-3 .