JP2663833B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a wiring and a method of forming the same.

[0002]

2. Description of the Related Art Fine wirings formed on a semiconductor chip are often arranged close to and parallel to each other, and a conventional wiring forming method uses a semiconductor substrate (not shown) as shown in FIG. After a 30 nm-thick titanium film 3 and a 50 nm-thick titanium nitride film 4 serving as barrier metal layers are sequentially deposited on the silicon oxide film 1 provided thereon by sputtering,
300 sputtered aluminum alloy film 5
Deposit to a thickness of nm. Next, a positive photoresist film is applied on the aluminum alloy film 5 by a spin coating method, exposed and developed to form a parallel wiring pattern having a width of about 0.6 μm. The aluminum alloy film 5, the titanium nitride film 4, and the titanium film 3 are sequentially removed by plasma etching using a system gas to form a wiring having an angle between a side surface and a horizontal plane of 60 to 95 ° C. Next, a silicon oxide film 7 is deposited on the surface including these wirings by a plasma CVD method at a deposition temperature of about 400 ° C. to form an interlayer insulating film.

[0003]

This conventional wiring is formed by arranging wirings having a trapezoidal or inverted trapezoidal cross section in parallel on the same plane, so that an interlayer insulating film deposited at a high temperature is formed. As shown in FIG. 5, when the temperature is lowered to room temperature, the horizontal component of the thermal stress due to the difference in the coefficient of thermal expansion between the wiring and the interlayer insulating film in the narrowest part between the adjacent wirings is formed in a common plane. Therefore, there is a problem that a tensile stress is applied to the wiring in this plane to cause disconnection in this plane.

[0004]

According to a first semiconductor device of the present invention, a groove having an inverted trapezoidal cross section provided in parallel with the upper surface of a lower insulating film provided on a semiconductor substrate; It has a wiring provided along the side wall and having inclinations in directions different from those of the side surfaces adjacent to each other, and an upper insulating film provided on a surface including the wiring.

[0005] A first method of manufacturing a semiconductor device according to the present invention comprises:
A step of forming in parallel a groove having an inverted trapezoidal cross section on the upper surface of a lower insulating film provided on a semiconductor substrate; and depositing a conductive film for wiring formation on the surface including the groove and etching back the groove. Removing the conductive film on the top and bottom surfaces of the groove while leaving only the side wall of the trench to form a wiring having an inclination in a direction different from that of the side surface adjacent to each other, and insulating the upper layer on the surface including the wiring Forming a film.

A second semiconductor device according to the present invention is characterized in that a groove provided in parallel with the upper surface of a lower insulating film provided on a semiconductor substrate is provided on each of the upper surface and the bottom surface of the groove so that the upper and lower surfaces are alternately different from each other. A wiring provided at the position; and an upper insulating film provided on a surface including the wiring.

According to a second method of manufacturing a semiconductor device of the present invention,
Forming a groove in parallel on the upper surface of the lower insulating film provided on the semiconductor substrate, depositing a conductive film for forming a wiring on the surface including the groove, and selectively etching the conductive film. The method includes the steps of forming wirings provided on the upper surface and the bottom surface of the groove and alternately arranged at different upper and lower positions, and forming an upper insulating film on the surface including the wirings.

[0008]

Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1D are sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to a first embodiment of the present invention.

First, as shown in FIG. 1A, the upper surface of a silicon oxide film 1 provided on a semiconductor substrate (not shown) is selectively etched to obtain a desired wiring width of about 0.25 .mu.m.
A groove 2 having a width of 0.7 μm, which is twice as large, and an inverted trapezoidal cross section having an inner wall inclined at about 80 degrees is formed in parallel.

Next, as shown in FIG. 1 (b), a barrier metal film having a thickness of 30 n
After sequentially depositing a titanium film 3 of thickness m and a titanium nitride film 4 of thickness 50 nm, an aluminum alloy film 5 containing 1 wt% of silicon and 0.5 wt% of copper as a wiring material is formed thereon by sputtering to a thickness of 300 nm. Deposited on

Next, as shown in FIG. 1C, the aluminum alloy film 5, the titanium nitride film 4, and the titanium film 3 are sequentially etched back by anisotropic etching by an ion milling method, so that a horizontal surface of the silicon oxide film 1 is formed. Is exposed, and a wiring in which a barrier metal film and an aluminum alloy film 5 are deposited on the inner side wall of the groove is formed.

Next, as shown in FIG. 1D, a silicon oxide film 6 is deposited by a plasma CVD method, and the whole surface is etched back to form an interlayer insulating film whose surface is flattened.

By adopting such a structure, FIG.
As shown in FIG. 3A, the horizontal component 10 of the thermal stress that the wiring 8 receives from the surrounding insulating film 9 is distributed to the upper and lower parts of the wiring 8, and the maximum stress value decreases by about 1.3%.

FIGS. 2A to 2D are sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to a second embodiment of the present invention.

As shown in FIG. 2A, an upper surface of a silicon oxide film 1 provided on a semiconductor substrate (not shown) has a width of 0.4 mm.
Grooves 2 having a side wall of about 5 degrees and a slope of about 60 degrees are formed in parallel.

Next, as shown in FIG. 2B, a barrier metal film comprising a 30 nm thick titanium film 3 and a 50 nm thick titanium nitride film 4 is formed by sputtering in the same manner as in the first embodiment. An aluminum alloy film 5 containing silicon and copper having a thickness of 300 nm is sequentially deposited.

Next, as shown in FIG. 2C, a positive photoresist film 7 is applied on the aluminum alloy film 5 by a spin method and patterned, and wirings are formed on the upper and lower surfaces of the groove, respectively. Is formed with a width of 0.25 μm and an interval of 0.2 μm.

Next, as shown in FIG. 2D, the aluminum alloy film 5 is formed using the positive photoresist film 7 as a mask.
Then, the barrier metal film is sequentially anisotropically etched to form wirings alternately arranged on the top and bottom surfaces of the groove. next,
A silicon oxide film 6 is deposited as an interlayer insulating film by a plasma CVD method, and the entire surface is etched back to flatten the surface.

Here, since the adjacent wirings are alternately arranged on the upper surface and the bottom surface of the groove, as shown in FIG. 3B, the horizontal component of the thermal stress received from the insulating film 9 around the wiring 8 is obtained. 10 is distributed on two different planes, upper and lower.
% Of the maximum stress value is obtained. Further, in this embodiment, since the wirings are positioned vertically, there is an advantage that the interlayer insulating film is easily filled between the wirings.

[0021]

As described above, according to the present invention, the wiring is provided along the side wall of the groove provided in the insulating film, the inclination of the sectional shape of the adjacent wiring is changed, or the wiring is alternately arranged on the upper surface and the bottom surface of the groove. Thereby, the horizontal component of the thermal stress of the adjacent wiring can be dispersed on different planes, and there is an effect that generation of voids and disconnection of the wiring are reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip shown in the order of steps for describing a manufacturing method according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor chip shown in a process order for describing a manufacturing method according to a second embodiment of the present invention.

FIG. 3 is a schematic sectional view showing a horizontal component of a thermal stress applied to a wiring according to the first and second embodiments of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor chip showing a conventional wiring.

FIG. 5 is a schematic cross-sectional view showing a horizontal component of thermal stress applied to a conventional wiring.

[Explanation of symbols]

 1,6 silicon oxide film 2 groove 3 titanium film 4 titanium nitride film 5 aluminum alloy film 7 positive photoresist film 8 horizontal component of stress 9 wiring

Claims (4)

(57) [Claims] 1. A groove having an inverted trapezoidal cross section provided in parallel with the upper surface of a lower insulating film provided on a semiconductor substrate, and a groove provided along each side wall of the groove and having side surfaces adjacent to each other. A semiconductor device comprising: wirings having inclinations different from each other; and an upper insulating film provided on a surface including the wirings. 2. An upper surface of a lower insulating film provided on a semiconductor substrate.
A groove having an inverted trapezoidal cross-section provided in parallel to the
Provided along each side wall and each side is adjacent
Including wiring having inclinations in directions different from each other and the wiring
And an upper insulating film provided on the surface.
A method for manufacturing a semiconductor device , comprising: a step of forming in parallel a groove having an inverted trapezoidal cross section on the upper surface of a lower insulating film provided on a semiconductor substrate; and a conductive film for forming a wiring on a surface including the groove. Depositing and etching back, removing the conductive film on the top and bottom surfaces of the groove, leaving only the side walls of the groove, and forming a wiring having an inclination in a direction different from that of the adjacent side surface, Forming an upper insulating film on the surface including the wiring. 3. A groove provided in parallel with the upper surface of a lower insulating film provided on the semiconductor substrate, and a wiring provided on each of the upper surface and the bottom surface of the groove and alternately arranged at different upper and lower positions;
A semiconductor device comprising an upper insulating film provided on a surface including the wiring. 4. A step of forming a groove in parallel on an upper surface of a lower insulating film provided on a semiconductor substrate, a step of depositing a conductive film for forming a wiring on a surface including the groove, and selecting the conductive film. Forming a wiring provided on each of the upper surface and the bottom surface of the groove by alternately etching, and alternately disposed at different upper and lower positions, and a step of forming an upper insulating film on a surface including the wiring. A method for manufacturing a semiconductor device.