JP2663892B2 - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art As one of nonvolatile semiconductor memory devices, there is a memory device having a floating gate electrode and a control gate electrode and capable of electronically writing or erasing electric charges.

FIGS. 4A to 4E are sectional views of a semiconductor chip shown in the order of steps for explaining a method of manufacturing a conventional nonvolatile semiconductor memory device.

First, as shown in FIG. 4A, a first gate insulating film 2 formed by thermally oxidizing the surface of a p-type silicon substrate 1, a floating gate electrode made of a polysilicon film, and a silicon oxide film. A second gate insulating film 4 and a control gate electrode 5 made of a polysilicon film are sequentially laminated to form a patterned gate electrode structure.

[0005] Next, as shown in FIG. 4 (b), a photoresist film 21 is applied to the surface including the multilayer gate electrode structure and patterned, and a hole is formed on the source region forming side of the multilayer gate electrode structure. Using the photoresist film 21 covering the drain region forming side as a mask, phosphorus ions are ion-implanted from obliquely above the silicon substrate, and a high electric field is applied to the source region to perform an n ⁻ -type diffusion for facilitating the erase operation. Forming Layer 7 (IEEE Technical)
Digest of International E
Electron Device Meeting. 19
1987, Vol. 25, No. 8, pages 560-563).

Next, as shown in FIG. 4C, after removing the photoresist film 21, a photoresist film 23 is applied to the surface including the multilayer gate electrode structure and patterned to form a drain of the multilayer gate electrode structure. A photoresist film 23 having an opening on the region forming side and covering the source region forming side
Is implanted obliquely from above into the silicon substrate with the mask as a mask to increase the hot carrier generation efficiency on the drain region side and facilitate the writing operation.
^{The +} type diffusion layer 8 is formed.

Next, as shown in FIG. 4D, after removing the photoresist film 23, a silicon oxide film is deposited on the surface including the multilayer gate electrode structure by the CVD method and etched back to form a multilayer gate electrode structure. Side wall spacers 9 are formed on the side surfaces of. Here, the silicon oxide film forming the side wall spacer 9 is HTO (High Temperature O).
xide), the film is formed at a temperature of about 800 ° C., but the surface of the silicon film is thermally oxidized by air entrainment when the semiconductor substrate is inserted into or discharged from the CVD furnace.

[0008] Next, as shown in FIG. 4 (e), arsenic ions are heat treated activated by ion implantation in a direction perpendicular to the silicon substrate a multilayer gate electrode structure and the sidewall spacer as a mask, n ⁺ -type A source region 10 and a drain region 11 are formed.

In the write operation of the nonvolatile semiconductor memory device formed as described above, a positive high voltage is applied between the control gate electrode 5 and the silicon substrate 1 to induce electrons in the channel region, and at the same time, the source region 10 Hot carriers are generated by applying a high voltage to the control gate electrode 5 to inject electrons into the floating gate electrode 3. The erasing operation is performed by applying a negative high voltage of about 10 to 12 MV / cm to the first gate insulating film 2 by lowering the potential of the control gate electrode 5 and setting the potential of the source region 10 to a high potential, thereby applying Fowler-Nordheim. (Fowler-Nor
This is obtained by emitting electrons from the floating gate electrode 3 to the source region 10 by flowing a tunnel current of a (dheim) type.

As described above, in the nonvolatile semiconductor memory device, the charge in the floating gate electrode is controlled by the writing operation and the erasing operation, and the storage state is set by changing the threshold voltage. In a nonvolatile semiconductor memory device having such a floating gate transistor, the quality and thickness of the insulating film covering the floating gate electrode are important, and the insulating film is not easily broken by passing a tunnel current. Is required.

[0011]

In this conventional non-volatile semiconductor memory device, in order to facilitate an erasing operation and a writing operation, n ^- type diffusion is performed by oblique ion implantation in regions adjacent to a source region and a drain region. And a p ⁺ -type diffusion layer. Since these n ⁻ -type diffusion layers and p ⁺ -type diffusion layers need to be formed inside the source region and the drain region, the oblique implantation method is used, but the first gate insulating film and the second gate insulating film Since the side portions are exposed, ion species are passed or implanted, and Si-O
There is a problem that defects such as bond dissociation occur and the dielectric breakdown life is shortened.

In addition, a heat treatment in an oxidizing atmosphere is effectively applied at the time of growing an oxide film for forming a sidewall spacer and at the time of a heat treatment in an inert gas atmosphere for forming a source / drain region. The side edges of the gate electrode and the control gate electrode and the vicinity thereof are oxidized, and the thickness of the edge portions of the first gate insulating film and the second gate insulating film locally increases. The influence of the electric field increases, and the probability of failure due to a defect in the gate insulating film in that portion increases. Further, internal stress is generated due to volume expansion of the gate insulating film due to oxidation of the end of the gate electrode, and Si—O
There was a disadvantage that the bond was distorted and the dielectric breakdown life was shortened.

An object of the present invention is to provide a nonvolatile semiconductor memory device in which deterioration of a gate insulating film is prevented and reliability is improved, and a method of manufacturing the same.

[0014]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising a first gate insulating film made of a silicon oxide film, a floating gate electrode made of a polysilicon film, and a second gate insulating film formed on a semiconductor substrate. A gate electrode structure formed by sequentially laminating control gate electrodes, and the semiconductor substrate on both sides of the multilayer gate electrode structure.
A source / drain region and
Memory erase characteristics formed between the source and drain regions
A first impurity diffusion region controlling the drain region and the drain region
Formed between the source / drain regions adjacent to
In a nonvolatile semiconductor memory device having a second impurity diffusion region for controlling a memory write characteristic, a surface of the interface between the floating gate electrode and the first and second gate insulating films is formed on the source / drain region . Part near the end face
And near an end face of the interface between the control gate electrode and the second gate insulating film facing the source / drain region.
A silicon nitride oxide layer is provided on a part of the side .

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, a first gate insulating film made of a silicon oxide film, a floating gate electrode made of a polysilicon film,
Forming a patterned multi-layer gate electrode structure by sequentially laminating a control gate electrode comprising a second gate insulating film and a polysilicon film; and thermally nitriding the surface of the multi-layer gate electrode structure to form the floating gate electrode and the control gate electrode. said end surface and its vicinity of the side facing the diffusion layer formation region of the gate electrode
A floating gate electrode, a control gate electrode, and the first and second gate electrodes;
Forming a silicon nitride oxide film at each interface with the gate insulating film; and ion-implanting impurities from obliquely above the semiconductor substrate to control writing and erasing operations in a region including a lower portion of the multilayer gate electrode structure . 1, forming a second impurity diffusion layer, the side on the side face of the multilayer gate electrode structure
Forming a wall spacer, and the multilayer gate electrode structure
And ion implantation using the sidewall spacers as a mask.
And forming a source / drain region .

[0016]

Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1E are sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to a first embodiment of the present invention.

First, as shown in FIG. 1A, the p-type silicon substrate 1 is selectively oxidized on one main surface to form a p-type silicon substrate 1 in a device forming region partitioned by a field oxide film (not shown).
A first gate insulating film 2 made of a silicon oxide film having a thickness of about 10 nm is formed by thermally oxidizing the surface of the mold silicon substrate. Next, a first polysilicon film having a thickness of about 150 nm is deposited on the first gate insulating
Heat treatment is performed in an OCl ₃ gas atmosphere, and phosphorus serving as an n-type impurity is diffused into the first polysilicon film by about 1 × 10 ²⁰ cm ⁻² and then patterned to form a floating gate electrode 3. Next, the surface of the floating gate electrode 3 is thermally oxidized to form a silicon oxide film having a thickness of about 10 nm, and a silicon nitride film having a thickness of 10 nm is formed on the silicon oxide film by a CVD method.
And a surface thereof is thermally oxidized to form a second gate insulating film 4 having a three-layer structure of a silicon oxide film / silicon nitride film / silicon oxide film having a silicon oxide film having a thickness of about 3 nm. I do. Next, a second polysilicon film having a thickness of about 200 nm is deposited on the second gate insulating film 4 by a CVD method, and heat-treated in a POCl ₃ gas atmosphere,
Phosphor which is a mold impurity is added to this second polysilicon film by 1 ×
Diffuse by about 10 ²⁰ cm ^-2 . Next, the second polysilicon film, the second gate insulating film 4, the floating gate electrode 3, and the first gate insulating film 2 are selectively and sequentially etched by an anisotropic dry etching method to form the first gate insulating film 2 Then, a multilayer gate electrode structure including the floating gate electrode 3, the second gate insulating film 4, and the control gate electrode 5 is formed.

Next, as shown in FIG. 1B, the surface including the multilayer gate electrode structure in an NH ₃ gas atmosphere is subjected to lamp annealing at about 900 ° C. using a halogen lamp as a light source for about 60 seconds or N 2. 105 in ₂ O gas atmosphere
A thermal nitridation process is performed at a temperature of 0 to 1150 ° C. for about 60 seconds to form a nitride film (not shown in the drawing) of several nm on the surface of the multilayer gate electrode structure, and at the same time, end surfaces of the floating gate electrode 3 and the control gate electrode 5. The silicon nitride oxide film 6 is formed on the interface between the first and second gate insulating films 2 and 4 in a region limited to the vicinity thereof.

Next, as shown in FIG. 1C, phosphorus ions are accelerated obliquely upward at an angle of 30 ° to 60 ° with respect to the silicon substrate by masking the drain region side in the same manner as in the conventional example. Energy 100keV, dose 1 ×
N ⁻ -type diffusion layer (first impurity diffusion layer) for controlling characteristics at the time of erase operation by ion implantation under the condition of 10 ¹⁴ cm ⁻² 7
Is formed on the source region side, and similarly, while masking the source region side, boron ions are accelerated obliquely from above at an angle of 30 ° to 60 ° with respect to the silicon substrate at an acceleration energy of 60 keV,
Ion implantation under the condition of a dose of 1 × 10 ¹⁴ cm ^-2 and ap ⁺ -type diffusion layer (second non-
(Pure substance diffusion layer) 8 is formed on the drain region side, and the temperature is 850.
Activation is performed in an inert gas atmosphere at 30 ° C. for 30 minutes.

Next, as shown in FIG. 1D, a silicon oxide film is deposited to a thickness of 200 nm on the surface including the multilayer gate electrode structure by the CVD method and etched back by anisotropic dry etching to form a multilayer. A side wall spacer 9 is formed on a side surface of the gate electrode structure. Next, arsenic ions are accelerated from the direction perpendicular to the silicon substrate at an energy of 70 ke.
V, ions were implanted at a dose of 5 × 10 ¹⁵ cm ^-2 and a temperature of 8
Activation is performed by a heat treatment for 10 to 60 minutes in an inert gas atmosphere at 00 to 900 ° C. to form an n + -type source region 10 and a drain region 11.

Next, as shown in FIG. 1E, an interlayer insulating film 12 is deposited on the entire surface to form a contact hole, and the source region 10 and the drain region 11 exposed in the contact hole are respectively formed. Electrode 1 to be electrically connected
Form 3

FIG. 2 is a graph showing the relationship between the amount of injected charges at which the first gate insulating film of the present invention and the conventional example are destroyed and the cumulative failure rate. The horizontal axis represents the time required for each test sample to reach the dielectric breakdown. The amount of injected charge Q _BD is shown, and the vertical axis shows the relative frequency.

As shown in FIG. 2, in the present invention, the rate of occurrence of random defects that break before reaching the intrinsic region can be significantly reduced as compared with the conventional example. This increases the electric field by partially increasing the dielectric constant of the gate insulating film in the region where electrons flow during operation, and reduces the electric field in the inactive region of the gate insulating film to reduce the effect of defects existing in the gate insulating film. This is because the effect of reducing the probability is obtained, which makes it possible to extend the life of the gate insulating film caused by repeating the writing operation and the erasing operation.

FIGS. 3A to 3C are sectional views of a semiconductor chip shown in the order of steps for explaining the manufacturing method according to the second embodiment of the present invention.

First, as shown in FIG. 3A, a first gate insulating film 2, a floating gate electrode 3, and a second gate insulating film are formed on a p-type silicon substrate 1 in the same steps as in the first embodiment. 4,
After providing a multilayer gate electrode structure formed by selectively laminating the control gate electrodes 5 sequentially, the n ⁻ -type diffusion layer 7 formed by oblique ion implantation into the source region side by masking the drain region side and the source region side And ap ⁺ -type diffusion layer 8 formed by oblique ion implantation on the drain region side is provided.

Next, as shown in FIG. 3B, heat treatment is performed in an NH ₃ gas or N ₂ O gas atmosphere to form a nitride film (omitted in the drawing) on the surface of the multilayer gate insulating structure, and at the same time, to form a floating gate. A silicon nitride oxide film 6 is formed on the end faces of the electrode 3 and the control gate electrode 5 and on the interface between the first and second gate insulating films 2 and 4 in a region limited to the vicinity thereof.

Next, as shown in FIG. 3C, as in the first embodiment, a side wall spacer 9 is formed on the side surface of the multilayer gate electrode structure, and arsenic ions are ion-implanted to form an n ⁺ type source. A region 10 and a drain region 11 are formed.

According to the second embodiment, similarly to the first embodiment, in addition to the effect of reducing the influence of defects existing in the gate insulating film, the first and second gate insulating films generated by oblique ion implantation are provided. There is an advantage that deterioration of the film can be recovered.

[0030]

As described above, according to the present invention, the source
A silicon nitride oxide layer is formed at the interface between the floating gate electrode and the control gate electrode on the side facing the drain region and the first and second gate insulating films in regions limited to the vicinity thereof and electrons are generated. By partially increasing the dielectric constant of the flowing region, the electric field in the inactive region of the gate insulating film can be reduced, and the effect of defects existing in the gate insulating film can be reduced with a high probability. In addition, the lifetime up to the destruction of the gate insulating film caused by the repetition of the erasing operation can be extended, and the reliability of the nonvolatile semiconductor memory device can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip shown in the order of steps for describing a manufacturing method according to a first embodiment of the present invention.

FIG. 2 is a graph showing the relationship between the amount of injected charge at which a first gate insulating film of the present invention and a conventional example are destroyed and the cumulative defect rate.

FIG. 3 is a cross-sectional view of a semiconductor chip shown in a process order for describing a manufacturing method according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor chip shown in a process order for describing a method of manufacturing a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 p-type silicon substrate 2 first gate insulating film 3 floating gate electrode 4 second gate insulating film 5 control gate electrode 6 silicon nitride oxide film 7 n ⁻ type diffusion layer 8 p ⁺ type diffusion layer 9 sidewall spacer 10 source region 11 drain Region 12 Interlayer insulating film 13 Electrode 21, 23 Photoresist film 22 Phosphorus ion 24 Boron ion

Claims (3)

(57) [Claims] 1. A multilayer gate electrode formed by sequentially stacking a first gate insulating film made of a silicon oxide film, a floating gate electrode made of a polysilicon film, a second gate insulating film, and a control gate electrode formed on a semiconductor substrate. Structure, and formed on the semiconductor substrate on both sides of the multilayer gate electrode structure
A source / drain region and
Memory erase characteristics formed between the source and drain regions
A first impurity diffusion region controlling the drain region and the drain region
Formed between the source / drain regions adjacent to
In a nonvolatile semiconductor memory device having a second impurity diffusion region for controlling a memory write characteristic, a surface of the interface between the floating gate electrode and the first and second gate insulating films is formed on the source / drain region . Part near the end face
And near an end face of the interface between the control gate electrode and the second gate insulating film facing the source / drain region.
A non-volatile semiconductor memory device comprising a silicon nitride oxide layer at a part of a side thereof. 2. A semiconductor substrate comprising a first gate insulating film made of a silicon oxide film, a floating gate electrode made of a polysilicon film, a second gate insulating film, and a control gate electrode made of a polysilicon film, which are sequentially laminated and patterned. Forming a multi-layer gate electrode structure; and thermally nitriding the surface of the multi-layer gate electrode structure to form an end surface of the floating gate electrode and the control gate electrode on the side facing the diffusion layer formation region and the floating gate electrode in the vicinity thereof. Forming a silicon oxynitride film at each interface between the control gate electrode and the first and second gate insulating films; and ion-implanting impurities from obliquely above the semiconductor substrate to lower the multilayer gate electrode structure. First and second impurities controlling the writing and erasing operations on the region including
Forming an object diffusion layers, of the multilayer gate electrode structure
Forming side wall spacers on side surfaces;
Ion injection using the electrode structure and the sidewall spacers as a mask
Forming a source / drain region by inserting the semiconductor device into a non-volatile semiconductor memory device. 3. The method for manufacturing a nonvolatile semiconductor memory device according to claim ₂ , wherein NH ₃ gas or N ₂ O gas is used for thermal nitridation of the surface of the multilayer gate electrode structure.