JP2658171B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] The present invention relates to a method for manufacturing a Schottky junction gate electrode type field effect transistor (including a heterojunction element), and more particularly to a method for forming elements having different threshold voltages on the same substrate. In order to reduce the number of lithography processes for recess etching, typically, in the formation of an n-channel device, a doping layer or an electron supply layer is composed of two layers having different characteristics to be etched. After previously removing one layer in the region where the element having the threshold value is formed, a resist is applied to open the gate electrode windows of the element having a different threshold value, and the recess is separately formed by an etching method suitable for each layer to be processed. Etching,
The gate electrode is formed by lift-off.

[Industrial applications]

The present invention relates to a method of manufacturing a Schottky junction gate electrode type field effect transistor (FET), and more particularly to a method of forming two types of FETs having different threshold voltages (Vth) on the same substrate.

Direct for digital integrated circuits with unipolar elements
A logic circuit called cuopled FET logic (DCFL) is often used. This DCFL is an enhancement mode FET
(E-FET) and depletion mode FET (D-FET)
Therefore, these two modes of FETs must be formed on the same substrate.

An FET formed on a compound semiconductor, for example, GaAs, operates at a high speed, and a compound semiconductor IC in which the FET is integrated is being developed. Since the gate structure of this type of FET is a Schottky junction type, it is often designed such that Vth is determined by the thickness of a doping layer which is a semiconductor layer below the gate electrode. That is, in a GaAs FET, a normally-on D-FET is formed by forming a thick doping layer.
In general, a normally-off E-FET is realized by forming a thin doping layer.

A structure in which the thickness of the doping layer below the gate electrode is reduced for controlling the operation mode, that is, adjusting Vth, is called a recess structure, and an etching process therefor is called a recess etching. Such adjustment of V th can be achieved by adjusting D at different V th.
An integrated circuit formed by FETs is performed by a similar process.

[Problems to be solved by conventional technology and invention]

In a conventional manufacturing method for realizing the recess structure, the steps shown in FIG. 3 are employed. Hereinafter, the steps of the related art will be described with reference to the drawings.

(A) As shown in the figure, an i-GaAs layer 32 as a buffer layer is epitaxially grown on a GaAs substrate 31 at 4000 .ANG., And an n-GaAs layer 33 as a doping layer is grown on the GaAs substrate 31 at 1000 .ANG. The impurity concentration of n-GaAs is 5 × 10 ¹⁷ cm ⁻³ .

An AuGe / Au electrode 34, which is an S / D electrode of the FET, is selectively formed on the surface, and a photoresist 35 is applied to open a window in a gate electrode formation region of the E-FET. The n-GaAs layer 3 is etched by dry etching or another etching method, and its thickness is assumed to match the E-mode operation of FTE (FIG. 3B).

If Al is deposited on the entire surface and unnecessary Al is lifted off by removing the photoresist, the gate electrode 36 is formed,
E-FET is completed ((c) diagram).

Subsequently, as shown in (d), a D-mode recess etching is performed using the photoresist 35 'as a mask, and as shown in (e), an Al gate electrode 36' of D-FET is provided by lift-off as shown in FIG. It is formed.

In each of the recess etchings, by performing the processing while monitoring the conductance of the transistor, the uncertainty of the thickness in the doping layer deposition step can be compensated, but the photolithography step is performed twice. I c
In order to achieve high density, it is necessary to miniaturize the pattern, and in that case, a large number of lithography becomes a major obstacle.

In order to solve this problem, various processing methods have been conventionally proposed. For example, in the method disclosed in Japanese Patent Application Laid-Open No. 60-41263, etching is performed simultaneously with recess etching of the E-FET so as to leave a part of the channel region of the D-FET.

The prior art will be described with reference to FIG.
An S / D electrode 44 is formed on 43, and an E-FET
A gate electrode 46 is formed by recess etching the channel region 47 on the side, and a part 47 ′ of the channel region is etched simultaneously with the recess etching of the region 47 on the D-FET side, which is the upper half of the figure, and the remaining The gate electrode 46 is formed in the region 47 ″ with the original thickness.

In such a structure, the V-th of the D-FET can be set to a predetermined value by appropriately setting the width of the region 47 ″, so that both E / D mode FETs are formed by one recess etching. Will be.

Further, the technology disclosed in Japanese Patent Application Laid-Open No.
In this embodiment, a heterojunction FET or an FET called an HEMT is formed. However, an adjustment layer of an n-type semiconductor corresponding to the difference in the depth of recess etching of the FET in both the E / D mode is provided. The doping layers having a predetermined thickness are respectively formed by the recess etching.

FIG. 5 is a diagram schematically showing the above technique reconstructed so as to be easily compared with the present invention. After providing the S / D electrode 54, a part of the adjustment layer 59 is removed in advance as shown in FIG.
Reference numeral 58 denotes an electron supply layer of, for example, n-AlGaAs. Next, as shown in FIG. 3B, if an etching process is performed using the photoresist 55 as a mask, a difference occurs in the etching depth of the doping layer in both openings corresponding to the time required for etching the adjustment layer 59. By the recess etching, both E / D mode FETs are formed.

In these prior arts, the characteristics of both E / D mode FETs are determined by values set in advance, such as the pattern size and the thickness of the auxiliary layer, and the throughput can be adjusted according to the actual conditions of the process. Since it is impossible, it is difficult to increase the production yield to a certain degree or more.

An object of the present invention is to eliminate the obstacle of high integration by making the number of times of lithography one, and to perform recess etching for both E / D modes separately to achieve the desired characteristics of each FET. Is to provide a method of manufacturing the same.

[Means for solving the problem]

In order to achieve the above object, according to the method of the present invention, the doping layer or the electron supply layer is formed of two layers having different etching characteristics.
For example, in the case of an n-channel device, for an n-channel device, one layer above the semiconductor layer in the gate electrode formation region of the device having a higher Vth is removed in advance, and a resist is applied to the entire surface to form a gate electrode window The two types of semiconductor layers exposed in the window are separately etched by an etching method suitable for each layer to be processed, and a gate electrode is formed by lift-off.

[Action]

In the recess etching, the two layers constituting the doping layer or the electron supply layer are separately etched by a processing method in which the other layer is not etched, so that even if the two layers are both exposed, the other layer is etched. It is possible to perform a predetermined amount of etching without any need, and it is possible to adjust the thickness of the doping layer according to the characteristics of each transistor.

Since the number of times of lithography is reduced to one, the margin for mask alignment is reduced by that amount, and the density of the IC can be increased. Also, in the actual process, the steps of Al deposition and lift-off are reduced by one time.

〔Example〕

FIG. 1 shows the steps of the first embodiment of the present invention. Less than,
The present invention will be described with reference to the drawings.

(A) As shown in FIG.
00Å, and an n-GaAs layer 3 serving as a first doping layer
Is grown 700 ° epitaxially. The impurity concentration of the layer is 5 × 10 ¹⁷ cm ⁻³ . In the present invention, the n-InGaP layer 3 ', which is the second doping layer, is further epitaxially grown at 700 °. The impurity concentration of this second layer is also 5 × 10 ¹⁷ cm ⁻³ . In addition, these two n-type layers have matching lattice constants.

The n-InGaP layer 3 'in the gate region of the E-FET is
(B) Selectively remove as shown in the figure. Since this positioning does not require accuracy, ordinary photolithography may be used, but the etching method is hydrochloric acid-based wet etching. In the etching process, the InGaP layer is etched, but the GaAs layer is not etched. Therefore, when the InGaP layer is removed, the etching is automatically stopped. The composition of the hydrochloric acid-based etching solution is, for example, HCl: H ₂
O ₂ : H ₂ O = 3: 1: 10.

Next, as shown in FIG. 3C, an AuGe / Au electrode 4 serving as an S / D electrode is selectively formed, and a photoresist 5 is applied to open the gate regions of both types of transistors.

Here, recess etching is performed on the n-GaAs layer 3 using a hydrofluoric acid-based etchant as shown in FIG. The etching amount may be controlled by the processing time, but according to the processing method of monitoring the conductance between the S / D electrodes, the characteristics of the E-FET can be accurately adjusted. During this process n-
The InGaP layer 3 'is also exposed to the etching solution, but the etching hardly proceeds. The composition of the hydrofluoric acid-based etchant is, for example,
HF: H ₂ O ₂ : H ₂ O = 1: 1: 10.

Subsequently, when processing is performed with the hydrochloric acid-based etching solution, recess etching is performed on the n-InGaP layer 3 'as shown in FIG. As described above, since the GaAs layer 3 is not etched by the etching solution, the characteristics of the E-FET are not changed by this processing. Here, too, the conductance can be monitored.

The two recess etchings may be performed in a different order.

After the recess etching, an Al layer is deposited, and an Al gate electrode 6 is formed by lift-off using a photoresist mask (FIG. 7F).

FIG. 2 shows a second embodiment of the present invention. The embodiment is related to the formation of the HEMT. The semiconductor layer is formed on a GaAs substrate 1 by an i-GaAs layer 2 as a channel forming layer and an n-type electron supplying layer. −InGaP layer 23
And an n-GaAs layer 23 '.

In reality, there is an n ⁺ -GaAs layer as a cap layer on the n-GaAs layer 23 ′, but its etching characteristics can be considered to be the same as GaAs. It is omitted in the figure.

As is well known, in the HEMT, two-dimensional electrons supplied from the electron supply layer to the i-GaAs layer serve as a channel and conduct. When the depletion layer spreads to a depth where the channel is formed, the HEMT is pinched off. The selection of the / D mode is performed by setting the thickness of the semiconductor layer from the gate electrode to the channel to a value adapted to each.

First, the n-GaAs layer in the E-FET gate region is selectively removed with the above-mentioned hydrofluoric acid-based etchant, and an S / D electrode is formed in the same manner as in the first embodiment. Further, a photoresist mask is provided, and n-In
If recess etching is performed on the GaP layer 23, the state shown in FIG.

Next, as shown in FIG. 3B, the n-GaAs layer 23 'is etched with the hydrofluoric acid-based etchant to realize a recess structure of the D-FET.

As described in the first embodiment, in the above two types of recess etching, only one layer is etched, so that the thickness of the other layer does not change and each of the two layers is independently formed to a desired thickness. Can be done. As in the first embodiment, the recess etching can be controlled by measuring the conductance of each recess.

Subsequently, when an Al layer is vapor-deposited and lifted off, an Al gate electrode 6 is formed as shown in (c), and HEMTs in both the E mode and the D mode are completed.

〔The invention's effect〕

As described above, according to the method of the present invention, Vth can be controlled to a desired value in both the E / D mode by one lithography. The alignment margin can be reduced, and the DCFL can be integrated at a high density. In addition, since the gate electrodes of the FETs in both the E / D mode are formed at the same time, the gate-to-gate connection wiring required when each is formed separately is unnecessary.

[Brief description of the drawings]

 FIG. 1 is a schematic sectional view showing a process of the first embodiment, FIG. 2 is a schematic sectional view showing a process of the second embodiment, FIG. 3 is a schematic sectional view showing a conventional recess process, FIG. 4 is a schematic diagram showing a first prior art, FIG. 5 is a cross-sectional schematic diagram showing a second prior art, in which 1,31,51 are GaAs substrates, 2,32,52. Is i-GaAs, 3,23 ', 33,43 is n-GaAs, 3', 23 is n-InGaP, 4,34,44,54 are S / D electrodes, 5,35,35 ', 55 are photo 6, 36, 36 'and 46 are gate electrodes, 47, 47' and 47 "are channel regions, 58 is n-AlGaAs, and 59 is an adjustment layer.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication location H01L 29/778 29/812

Claims (1)

(57) [Claims] A step of forming a semiconductor substrate in which a second semiconductor layer is stacked on a first semiconductor layer, and a third semiconductor layer is selectively stacked on the second semiconductor layer; Covering the entire surface of the second and third semiconductor layers except the area where the gate electrode of the field-effect transistor is formed with an etching-resistant film; The exposed surface of the second semiconductor layer is etched by an etching method sufficiently larger than the etching rate for the semiconductor, and the thickness is adjusted to the thickness of the channel region of the field effect transistor having the first threshold voltage. And exposing the third semiconductor layer by an etching method in which an etching rate for the third semiconductor is sufficiently higher than an etching rate for the second semiconductor. A step of reducing the thickness by etching to adjust the thickness of the remaining third semiconductor layer and the second semiconductor layer to the thickness of the channel region of the field effect transistor having the second threshold voltage And a method for manufacturing a field effect transistor.