JP2653442B2 - Progressive scan conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to an improvement of a progressive scanning conversion circuit used in a digital television receiver.

(Prior Art) In recent years, research and development for increasing the image quality of television images of the current system by digital processing have been actively performed, and progressive scanning conversion has been put to practical use as one of the means. This progressive scan conversion is for converting a television signal transmitted by interlace into non-interlace, and is suitable for reproducing an image in which the scanning line structure is difficult to see.

Here, as the above-mentioned progressive scan conversion, a means for converting transmitted horizontal scanning lines into non-interlace by shaking twice and a method for generating scanning lines from upper and lower horizontal scanning and between the original upper and lower horizontal scanning lines are used. There is a means for converting to non-interlace by interpolation.

FIG. 8 shows a conventional progressive scan conversion circuit which performs non-interlace conversion by swaying a transmitted horizontal scan line twice. That is, in the figure, reference numeral 11 denotes an input terminal to which an interlaced television signal is supplied. The television signal supplied to the input terminal 11 is supplied to the selector circuit 12 for one horizontal scanning period (hereinafter, “1”).
(Referred to as lines) alternately to the line memories 13 and 14.

In this case, when the television signal is being guided to the line memory 13, the line memory 13 is in the writing state and the line memory 14 is in the reading state. When a television signal is being guided to the line memory 14, the line memory 14 is in a writing state and the line memory 13 is in a reading state. In either case, reading is performed at twice the speed of writing, and is converted to a so-called double speed.

Here, the television signals read from the line memories 13 and 14 are supplied to the selector circuit 15. The selector circuit 15 selects the line memory 13 or 14 on the side in the readout state, and the double-speed converted non-interlaced television signal is output to the output terminal.
It is taken from 16.

According to such a configuration, the television signal supplied to the input terminal 11 is supplied to the scanning line 17 as shown in FIG.
As shown in FIG. 2B, the television signal taken out from the output terminal 16 is shifted so that the scanning lines 17 to 19 are also moved to the positions of 17a to 19a, respectively. That is, the number of scanning lines is doubled, and can be converted to a non-interlaced signal.

Next, FIG. 10 shows a conventional progressive scan conversion circuit for generating a scan line from upper and lower horizontal scan lines and interpolating between the original upper and lower horizontal scan lines to convert the scan line into non-interlace. That is, in the figure, an input terminal 20 is supplied with an interlaced television signal. This input terminal 20
The television signal supplied to the line is delayed by one line by the line memory 21 and added by the arithmetic circuit 22 and further multiplied by 、 to form two horizontal scanning lines which are continuous vertically. The average is used for calculating the television signal.

Then, the television signal supplied from the input terminal 20 and the television signal output from the arithmetic circuit 22 are:
It is supplied to the double speed conversion circuits 23 and 24, respectively. The double-speed conversion circuits 23 and 24 output the input television signal twice at double speed. The television signals output from the double-speed conversion circuits 23 and 24 are alternately selected by the selector circuit 25. It is taken out from the output terminal 26.

According to such a configuration, the television signal supplied to the input terminal 20 is supplied to the scanning line 27 as shown in FIG.
, The television signal taken out from the output terminal 26 is a signal obtained by averaging the scanning lines 27 and 28 after the scanning line 27 is output, as shown in FIG. 27
The operation of swinging to the position a and then swinging the scanning line 28 is repeated, so that the number of scanning lines is doubled and can be converted to a non-interlaced signal.

Here, FIG. 12 (a) shows a state in which an image in which the oblique line Z is moving upward in the figure is displayed by interlaced scanning. First, the oblique line Z1 is displayed by the scanning lines 32 and. Then, in the next field, the oblique line Z2 is displayed by the scanning lines 31 and 33 of that field. In addition, the diagonal line Z2 rises upward in the figure.
Is represented by scan lines 30, 32 in the next field.
That is, as viewed in the vertical-time plane, as shown in FIG. 12 (b), it rises upward in the figure for each field.

By the way, if the interlaced signal shown in FIG. 12 (a) is converted to non-interlaced by a sequential scan conversion circuit of the type which swings the same scanning line twice as shown in FIG. 8, for example, FIG. 13 (a) It becomes as shown in. First, the scanning lines 32 and 34 displaying the oblique line Z1 are the scanning lines 32 and 34.
Since it is swung to the position of 8, it becomes a line connected in the vertical direction.
Similarly, the scanning lines 31 and 33 displaying the oblique line Z2 are swayed to the positions of the scanning lines 32 and 34, respectively, and thus are lines connected in the vertical direction.

That is, in the vertical-time plane, as shown in FIG. 13 (b), the current field and the past field rise upward in the figure while overlapping, and appear to be connected in the vertical direction. Is degraded.

Also, as shown in FIG. 10, a progressive scan conversion circuit of the type that generates scanning lines from upper and lower horizontal scanning lines and interpolates between the original upper and lower horizontal scanning lines to convert to non-interlaced, Although the connection in the direction is slightly improved as compared with that shown in FIG. 8, it is still noticeable and causes deterioration in image quality.

(Problems to be Solved by the Invention) As described above, in the conventional progressive scan conversion circuit, when an image in which oblique lines move upward in parallel is converted to non-interlace, the oblique lines appear to be connected in the vertical direction. This causes a problem that the image quality is deteriorated.

Therefore, the present invention has been made in consideration of the above circumstances, and can maintain high image quality without deteriorating the image quality even when converting an image with diagonal movement to non-interlace, and in particular, the influence of noise. It is an object of the present invention to provide a very good progressive scan conversion circuit which is less likely to be affected by a simple structure and which can be economically advantageous.

[Structure of the Invention] (Means for Solving the Problems) A progressive scan conversion circuit according to the present invention sequentially delays an interlaced television signal by a predetermined number of pixels a plurality of times within one horizontal scanning period. First multi-stage delay means for causing the television signal output from the first multi-stage delay means to be delayed by one horizontal scanning period together with the total delay amount of the first multi-stage delay means; A second multi-stage delay unit for sequentially delaying the television signal output from the delay unit by a predetermined number of pixels a plurality of times within one horizontal scanning period; and a predetermined number of pixels by the second multi-stage delay unit. A plurality of television signals selected from the television signals sequentially delayed and a television signal selected from the television signals sequentially delayed by a predetermined number of pixels by the first multi-stage delay means. Correlation calculating means for calculating a cross-correlation with a plurality of television signals, respectively, and a scanning line to be interpolated between horizontal scanning lines of the interlaced television signal based on the correlation value calculated by the correlation calculating means. And generating means for performing the processing.

(Operation) According to the above configuration, a plurality of television signals selected from among the television signals sequentially delayed by a predetermined number of pixels by the first multi-stage delay unit, and the second multi-stage delay unit A cross-correlation with a plurality of television signals selected from among the television signals sequentially delayed by a predetermined number of pixels at each is calculated, and based on the correlation value,
Since the scanning lines to be interpolated between the horizontal scanning lines of the interlaced television signal are generated, the sequential scanning conversion can be performed without significantly deteriorating the properties of the image, and the movement of the oblique lines can be performed. Even if an image having a color is converted to non-interlace, high image quality can be maintained without deterioration of image quality.

In particular, since a pattern based on a plurality of television signals selected from the first multi-stage delay unit is compared with a pattern based on a plurality of television signals selected from the second multi-stage delay unit, S / S Even with respect to a television signal having a low N ratio, a scanning line to be interpolated between horizontal scanning lines of an interlaced television signal can be generated correctly, and the system is resistant to noise.

Further, since the television signal output from the first multi-stage delay means is supplied to the delay means, the television signal is used as the delay means together with the total delay amount by the first multi-stage delay means. What is necessary is just to have a function of delaying exactly one horizontal scanning period. For this reason, even when the delay means is configured by, for example, a memory, it is not necessary to use a memory having a capacity sufficient to store all television signals for one horizontal scanning period. Can be reduced, the configuration can be simplified, and it is economically advantageous.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, reference numeral 35 denotes an input terminal to which a television signal to be interlaced is supplied.
The television signal supplied to the input terminal 35 is supplied to a line memory 40 via four delay elements 36 to 39 in series.

Here, each of the delay elements 36 to 39 performs an action of delaying the television signal by one pixel, and the television signal output from the delay element 39 is four pixels apart from the input television signal. Will be delayed. The line memory 40 delays the television signal output from the delay element 44 by one line, but is set to function as a delay circuit that is four pixels less than the number of pixels constituting one line. ing. That is, the delay elements 36 to 39 and the line memory 40 are designed to exactly delay one line.

The television signal output from the line memory 40 is supplied to the first-stage delay element 44 of the four delay elements 41 to 44 connected in series. Each of these delay elements 41-44
Also have the function of delaying the television signal by one pixel.

Here, the television signal supplied to the input terminal 35 and the television signal output from the delay elements 36 and 37 are supplied to one input terminal of a correlation operation circuit 45, respectively. The television signals output from the delay elements 36 to 38 are supplied to one input terminal of a correlation operation circuit 46, respectively. Further, the television signals output from the delay elements 37 to 39 are supplied to one input terminals of a correlation operation circuit 47, respectively.

On the other hand, the television signal output from the line memory 40 and the television signal output from the delay elements 44 and 43 are supplied to the other input terminals of the correlation operation circuit 45, respectively. The television signals output from the delay elements 44 to 42 are supplied to the other input terminals of the correlation operation circuit 46, respectively. Further, the television signals output from the delay elements 43 to 41 are supplied to the other input terminals of the correlation operation circuit 47, respectively.

The television signals output from the delay elements 36 to 38 are supplied to a selector circuit 48. Further, the television signals output from the delay elements 44 to 42 are supplied to a selector circuit 49.

Here, each of the correlation calculation circuits 45 to 47 calculates a cross-correlation between a television signal supplied to one input terminal thereof and a television signal supplied to the other input terminal thereof,
The correlation value is supplied to the maximum value selection circuit 50. The maximum value selection circuit 50 selects the largest one of the correlation values output from the correlation operation circuits 45 to 47,
A control signal is generated in the selector circuits 48 and 49.
Further, the selector circuits 48 and 49 select one of the input television signals based on the control signal output from the maximum value selection circuit 50, and output the selected television signal to the addition circuit 51.

The addition circuit 51 adds the television signals output from the selector circuits 48 and 49 and outputs the result to the double speed conversion circuit 52. The television signal output from the delay element 37 is supplied to a double speed conversion circuit 53. The double-speed conversion circuits 52 and 53 output the input television signal twice at double speed, and each double-speed conversion circuit
The television signals output from 52 and 53 are alternately selected by selector circuit 54 and taken out from output terminal 55.

According to the above configuration, each output signal of the delay elements 39, 38, 37, and 36 and the input signal to the delay element 36 are a-
2, a-1, a0, a1, a2, and the input signal to the delay element 44 and the output signals of the delay elements 44, 43, 42, 41 are b-2, b-1,
Assuming that b0, b1, and b2, each pixel in the continuous horizontal scanning lines A and B has a relationship as shown in FIG.

Here, the correlation operation circuit 47 calculates the cross-correlation of three pixels surrounded by dotted lines A1 and B1 in FIG. Further, the correlation operation circuit 46
Calculates the cross-correlation of three pixels surrounded by dotted lines A2 and B2 in FIG. 2, and the correlation operation circuit 45 calculates the cross-correlation of three pixels surrounded by dotted lines A3 and B3 in FIG. In this case, each correlation operation circuit 4
7, 46, 45, the cross-correlation values of the dotted frame A1 and B1, A2 and B2, A3 and B3 in FIG. 2 are M-1, M0 and M1, respectively. Is performed to calculate the correlation value.

Then, the correlation values output from the correlation operation circuits 47 to 45 are supplied to the maximum value selection circuit 50, and the maximum value is detected. In this case, the maximum value selection circuit 50 is
Depending on which correlation value M-1, M0, M1 output from ~ 45 is the largest, Selector circuit 4 so that
Controls 8,49.

The addition result obtained from the addition circuit 51 in this manner is
FIG. 2 shows the pixel level to be interpolated at the position of Xk between the horizontal scanning lines A and B in FIG. 2, and the above-described operation is performed for one horizontal scanning period. A scanning line X is generated. And the above-mentioned addition circuit
A selector circuit 54 alternately selects a signal obtained by double-converting the output of 51 by the double-speed conversion circuit 52 and a signal obtained by double-converting the output of the delay element 37 by the double-speed conversion circuit 53. It is obtained from the signal.

For this reason, as shown in FIG. 3, when performing non-interlace conversion on an image in which the oblique line Z moves upward in the figure, the pixels 56 to be interpolated are the upper and lower scanning lines 57 and 58.
Are generated from the pixels 59 and 60 displaying the oblique line Z among them, so that the oblique line Z does not appear to be connected in the vertical direction as in the related art, and the image quality can be improved.

In particular, since the correlation between the patterns of three pixels before and after one horizontal scanning period is calculated, S / S
Even with respect to a television signal having a low N ratio, a scanning line to be interpolated between horizontal scanning lines of an interlaced television signal can be generated correctly, and the system is resistant to noise.

Also, the television signal delayed by the delay elements 36 to 39 is supplied to the line memory 40, and is delayed by one horizontal scanning period together with the total delay by the delay elements 36 to 39. As the delay element 36
It is sufficient that the television signal has a function of delaying the television signal by exactly one horizontal scanning period, in addition to the total delay amount of .about.39. That is, as the line memory 40, 1
Since it is not necessary to use a device having a capacity enough to store all the television signals for the horizontal scanning period, the capacity can be reduced, the configuration can be simplified, and it is economically advantageous.

Here, in the above-described embodiment, the delay elements 36 to 39 and 41
Although the description has been made of the case where the delay is delayed by one pixel of the television signal as to 44, a delay element that delays by two pixels may be used. In this case, a continuous horizontal scan line
In A and B, each pixel has a relationship as shown in FIG. 4. Pixels indicated by oblique lines in the figure are not subjected to the correlation calculation, and the correlation calculation is performed every other pixel. Can be performed.

Next, FIG. 5 shows a specific configuration of the correlation operation circuit 47. The other correlation operation circuits 45 and 46 perform the same operation with the same configuration as that of the correlation operation circuit 47, and therefore, the description thereof is omitted.

Television signals a-2, a-1, and ao are supplied to input terminals 61 to 63 on one side of the correlation operation circuit 47, and television signals b2 and b1 are supplied to input terminals 64 to 66 on the other side. , b0 are supplied. The television signal a-2 is multiplied by the television b0 by the multiplication circuit 67, and the television signal a-1 is multiplied by the television signal by the multiplication circuit 68.
b1 and the television signal a0 is multiplied by the television signal b2 by the multiplication circuit 69. Then, the outputs of the multiplication circuits 67 to 69 are added by the addition circuit 70,
The operation of the expression (1) is realized, and the operation result is output to the output terminal 71.
It is taken out from.

The means for calculating the correlation values M-1, M0, M1 can also be calculated by performing the following calculation in addition to the one shown in the above equation (1).

In this case, the correlation operation circuit 47 has a configuration as shown in FIG. That is, the subtraction circuit 72 subtracts the television signals a-2, b0 supplied to the input terminals 61, 66, and the subtraction circuit 73 subtracts the television signals a-1, b1 supplied to the input terminals 62, 65. Then, the subtraction circuit 74 subtracts the television signals a0 and b2 supplied to the input terminals 63 and 64.

Then, the outputs of the respective subtraction circuits 72 to 74 are converted to absolute value circuits 75 to 77.
, The addition is performed by the addition circuit 70, whereby the calculation of the above equation (3) is realized, and the calculation result is taken out from the output terminal 71. However, when a correlation operation circuit as shown in FIG. 6 is used, the maximum value selection circuit
It is necessary to use a minimum value selection circuit instead of 50 and to change the control so that the selector circuit 48, 49 is controlled by detecting the smallest value of the correlation value.

Next, another embodiment of the present invention will be described with reference to FIG. 1 will be described. The outputs of the delay circuits 36 to 38 and the outputs of the delay circuits 43 to 41 are added by addition circuits 78 to 80, respectively, and the coefficient multiplication circuit 81 ~ 83.

On the other hand, the correlation value M output from each of the correlation operation circuits 45 to 47
1, M0, M-1 are supplied to a coefficient generation circuit 84. The coefficient generating circuit 84 outputs three types of coefficients obtained by dividing the inputted correlation values M1, M0, M-1 by their sum (M1 + M0 + M-1) to the coefficient multiplying circuits 81 to 83. is there.

Then, the coefficient multiplying circuits 81 to 83 multiply the output of the adding circuits 78 to 80 by the coefficient output from the coefficient generating circuit 84, that is, perform weighting, and output the result to the adding circuit 85. The addition circuit 85 adds the outputs of the coefficient multiplication circuits 81 to 83 to generate interpolation pixels, and outputs the pixels to the double speed conversion circuit 52.

That is, in the embodiment shown in FIG.
Using the outputs of ~ 47, the interpolation pixel x0 is calculated as x0 = 1 / M {M-1 (a-1 + b1) + M0 (a0 + b0) + M1 (a1 + b-1)} (4) (where M = M-1 + M0 + M1). With this configuration, substantially the same effects as in the above embodiment can be obtained.

It should be noted that the present invention is not limited to the above embodiments, and can be variously modified and implemented without departing from the scope of the invention.

[Effects of the Invention] According to the present invention, even when an image having oblique line motion is converted to non-interlace, high image quality can be maintained without image deterioration, and the image is easily affected by noise. With such a configuration, it is possible to provide an extremely good progressive scan conversion circuit which can be economically advantageous.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a progressive scan conversion circuit according to the present invention, FIGS. 2 and 3 are diagrams for explaining the operation of the embodiment, and FIG. FIG. 5 is a block diagram showing details of the correlation operation circuit of the embodiment, and FIG. 6 is a block diagram showing details of the correlation operation circuit when the delay amount of the delay element is set to 2 pixels. FIG. 7 is a block diagram showing a modification, FIG. 7 is a block diagram showing another embodiment of the present invention, and FIGS. 8 and 9 are block diagrams showing a conventional progressive scan conversion circuit and the operation thereof. FIG. 10 and FIG. 11 are block diagrams showing another conventional progressive scan conversion circuit and diagrams for explaining the operation thereof, and FIG. 12 and FIG. FIG. 11 ... input terminal, 12 ... selector circuit, 13, 14 ... line memory, 15 ... selector circuit, 16 ... output terminal, 17 ~
19 ... scanning line, 20 ... input terminal, 21 ... line memory,
22 arithmetic circuit, 23, 24 double speed conversion circuit, 25 selector circuit, 26 output terminal, 27-34 scanning line, 35
Input terminals, 36 to 39: delay element, 40: line memory,
41 to 44: delay element, 45 to 47: correlation operation circuit, 48, 49
... selector circuit, 50 ... maximum value selection circuit, 51 ... addition circuit, 52, 53 ... double speed conversion circuit, 54 ... selector circuit, 5
5 …… Output terminal, 56 …… Pixel, 57,58 …… Scan line, 59,60
…… Pixel, 61-66 …… Input terminal, 67-69 …… Multiplication circuit,
70 addition circuit, 71 output terminal, 72-74 subtraction circuit, 75-77 absolute value circuit, 78-80 addition circuit, 81-
83 ... coefficient multiplication circuit, 84 ... coefficient generation circuit, 85 ... addition circuit.

Claims (1)

(57) [Claims] 1. A first multi-stage delay means for sequentially delaying an interlaced television signal a plurality of times by a predetermined number of pixels within one horizontal scanning period, and output from the first multi-stage delay means. Delay means for delaying the television signal by one horizontal scanning period together with the total delay amount of the first multi-stage delay means; and a television signal output from the delay means for a predetermined pixel within one horizontal scanning period. A second multi-stage delay means for sequentially delaying a plurality of times, a plurality of television signals selected from the television signals sequentially delayed by a predetermined number of pixels by the second multi-stage delay means; Correlation calculation for calculating a cross-correlation with a plurality of television signals selected from television signals sequentially delayed by a predetermined number of pixels by the first multi-stage delay means, respectively. Means, and generating means for generating a scanning line to be interpolated between horizontal scanning lines of the interlaced television signal based on the correlation value calculated by the correlation calculating means. Scanning conversion circuit.