JP2652221B2 - Ferroelectric liquid crystal display device and display control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric liquid crystal control device that controls display of a ferroelectric liquid crystal (hereinafter, referred to as FLC).

[Prior Art] Conventionally, this type of ferroelectric liquid crystal control device has a plurality of display memories having the same configuration and compares the contents in order to detect that data to be displayed on the FLC display has been rewritten. Or, it was necessary to perform management by software with a drawing device using a CPU or the like.

[Problems to be Solved by the Invention] However, a system having a plurality of display memories requires a relatively large-capacity memory, resulting in an increase in cost, and a system in which software is managed by a CPU or the like has been used up to now. There are drawbacks such as the incompatibility with the software being used.

In view of the above-mentioned problems in the conventional type, the present invention is low-cost without having two large-capacity display memories, and without significantly changing the software used until now. An object of the present invention is to provide a ferroelectric liquid crystal control device capable of detecting partial writing of display data.

[Means and Actions for Solving the Problems] In order to achieve the above object, a ferroelectric liquid crystal control device according to the present invention provides a display device which performs writing to a display memory prior to writing to a display memory. The memory is read, compared with the data to be written, and if they are different, a flag indicating that the data has been rewritten is set.

As a result, rewriting can be detected by adding a much smaller number of flag memories than having another display memory. Also, if the read-modify-write function of the memory is used, reading and writing can be performed almost in parallel, so that an increase in processing time can be suppressed.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a ferroelectric liquid crystal control device and peripheral circuits according to one embodiment of the present invention. In the figure, 1 is a drawing device such as a CPU, 2 is a display memory (VRAM) that the drawing device 1 can freely read and write, and 3 is a VRAM2.
The comparator 4 compares the data to be written to the read data and the flag 4 is set when the drawing device 1 writes to the VRAM 2. This flag 4 is provided by the number corresponding to the display line of the FLC panel.
When a write is performed at an address corresponding to a certain display line, a flag corresponding to the display line is turned on to store that the partial write has been performed. 5 is a sequencer for generating a display address or checking and resetting the flag 3;
Reference numeral 6 denotes an FLC panel for displaying.

When the drawing unit 1 writes data into the VRAM2, first, the VRAM2 is written using the read-modify-write function of the memory.
After reading data from the memory and comparing it with the data to be written, the data is written to the VRAM2. If the contents of the read data and the data to be written do not match, the flag 4 corresponding to the address is set. A normal dynamic RAM can perform reading and writing at exactly the same time in parallel, but a dual-port RAM often used as a display memory requires a little longer processing time. This is shown in the timing chart of FIG.

In the case of the FLC panel, even if one bit in one line is rewritten, it is necessary to send one line of data to the FLC panel. Therefore, the flag 4 only needs to be one bit for the address of one line of the memory.

The sequencer 5 normally performs interlace refresh of display and check of the flag 4, and if all the flags corresponding to each line of the flag 4 are not set, the refresh is repeated. If the flag 4 is set, the address of the VRAM 2 is calculated backward from the number of lines of the set flag, and data for one line is sent to the FLC panel 6 to clear the flag 4.

The partial rewriting method used in the present invention is described in U.S. Pat.
As disclosed in US Pat. No. 4,655,561 and US Pat. No. 4,693,563, a method of applying a scan selection signal to a scan line only in a partial rewrite area can be used. Such a partial rewriting method can be used not only for the character correction display on the display screen but also for the multi-window display, the scroll display in the window, and the moving display of the cursor and the mouse from the pointing device.

FIG. 3 shows an embodiment of a multi-window screen display. The display screen displays different screens in the display area. Window 1 shows a screen in which a certain tabulated result is expressed in a pie chart, window 2 shows a screen in which the tabulated result of window 1 is expressed in a table, and window 3 shows a screen in which the tabulated result of window 1 is expressed in a bar graph. The window 4 performs an operation related to text creation. The background is solid white.

Here, it is assumed that the window 4 is a work screen and the other windows are in a still image state. In other words, the window 4 is in a moving image display state while text is being created. Specific operations in this moving image state include scrolling, insertion / deletion and copying of words / phrases, area movement, and the like. These operations require relatively fast operations. Hereinafter, display operation examples will be described.

First Example—A new character is additionally displayed on an arbitrary line in the window 4. The character font has a 16 x 16 dot configuration. In order to newly display one character, 16 scanning lines are rewritten, and only these 16 scanning lines are driven for scanning.

 Second example-window 4 is in a smooth scroll state.

It is assumed that the number of scanning lines occupied by window 4 is 400. Smooth scroll display is rewriting by scanning only 400 scanning lines.

In the refresh scanning method used in the present invention, a scanning selection signal is periodically applied, but one frame scan (or one field scan) needs to form one screen (in other words, one time). In one scan line scan, pixels on one scan line need to complete selective writing of black display based on the dark state of the FLC and white display based on the bright state).

In particular, as a refresh scanning method used in the present invention, a multi-selection method in which scanning selection signals are selectively applied to scanning lines at intervals of at least two lines, preferably at intervals of at least four lines (every four to twenty lines are suitable). Interlaced scanning is preferred.

FIG. 4A shows a scanning selection signal S _S and a scanning non-selection signal.
S _N, represents the white information signal I _W and a black data signal I _B.
Figure 4 (B), the pixel of the scanning selection signal S _S is the selected pixel (white information signal I _W of the pixels on the scanning selection electrodes applied (intersection of scanning electrodes and information electrodes) is applied At the voltage (I _W
-S _S) is a voltage waveform applied to applied), the voltage (I _B -S _S) is applied by the pixel unselected pixels (black information signal I _B is applied on the same scan selection electrode) And a voltage waveform applied to two types of pixels on the scanning non-selection electrode to which the scanning non-selection signal is applied.

According to FIGS. 4 (A) and (B), the voltage (− (V ₁ + V ₃ )) which is a voltage exceeding one threshold voltage of the FLC is applied to the non-selected pixel on the scanning selection electrode at the phase t _1. Is applied, FLC
A dark state is generated by generating one of the alignment states of
Black writing is performed. The phase t ₁ at this time, to the selected pixel on the scan selection electrode is applied a voltage which is below the threshold voltage of the _{FLC (-V 1 + V 3)} , no change in the alignment state of the FLC. In phase t _2, the selected pixel on the scan selection electrode, the voltage is a voltage exceeding the other threshold voltage of the FLC (V ₂
+ V ₃ ) is applied, causing the FLC to orient to the other orientation state, producing a bright state and written to white. Further, a voltage (V ₂ −V ₃ ) which is a voltage equal to or lower than the FLC threshold is applied to the non-selected pixels on the scan selection electrode at the phase t ₂ ,
It does not change the alignment state at t _1. On the other hand, the phase t ₁ and t ₂ at a voltage ± V ₃ a threshold voltage below the voltage of FLC is applied to the pixels on the scanning non-selection electrodes. Therefore, in this embodiment, white or black writing is performed to the pixels on the scanning electrodes selected in phase T _1, followed by even in a state in which the scanning non-selection signal is applied, the time before writing Is maintained as it is. In the present embodiment, the phase T _2,
Voltages of opposite polarity is applied from the information electrode to the information signal in the writing phase T _1. Therefore, as shown in FIG. 4 (C), an AC voltage is applied to the pixel when scanning is not selected, and FL is applied.
The threshold characteristics of C can be improved.

FIG. 4C shows a timing chart of a voltage waveform for causing a certain display state. In this example,
The scan selection signal is jumped and applied to the scan electrodes every five lines, and the scan selection signal is applied to the non-adjacent scan electrodes in six consecutive fields. Then, every five scanning electrodes are selected, and one frame scan (one screen scan) is performed by six field scans, so that the scan selection period (T ₁ + T ₂ ) is set to be long at a low temperature, and as a result, Even with a low frame frequency scan drive (for example, a frame frequency of 5 to 10 Hz), the occurrence of flicker due to the low frame frequency scan drive can be significantly suppressed. By applying a scan selection signal so as to select a scan electrode that does not match, image deletion can be effectively eliminated.

Further, as the FLC element used in the present invention, U.S. Pat.
No. 367924, US Patent No. 4639089, US Patent No. 4
As disclosed in 655561, U.S. Pat.No.4697887 and U.S. Pat.No.4,712,873, the cell is sufficiently sufficient to suppress the formation of a helical array structure unique to the chiral smect c layer under the bulk state. It is preferable to use a bistable orientation state generated by setting the pressure (substrate interval) to be small.

[Effects of the Invention] As described above, according to the present invention, comparison with read data is performed in parallel at the time of writing to the display memory of the drawing device, so that an increase in processing time can be suppressed. Also, since a flag indicating the result of the comparison may have one bit for one display line, a memory of bits corresponding to the number of display lines may be added as the flag. Therefore, partial writing can be detected by adding a few hundredth of the memory compared to the method of comparing and comparing two display memories, realizing only hardware with a simple circuit with reduced display memory. This has the advantage that vast software can be easily used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a ferroelectric liquid crystal control device and a peripheral circuit according to an embodiment of the present invention. FIG. 2 is a timing chart showing a read-modify-write state of a display memory. FIG. 4 is a display screen diagram showing an example of an image display used in the present invention, and FIGS. 4A to 4C are drive waveform diagrams used in the present invention. 1: Drawing unit, 2: Display memory (VRAM), 3: Comparator, 4: Flag, 5: Sequencer, 6: Display FLC panel.

Claims (11)

(57) [Claims] 1. A ferroelectric liquid crystal display, a display memory for storing display data of each dot at an address corresponding to each dot of the display, a drawing unit for writing display data to the display memory, A sequencer for transferring display data from the display memory to the display device, and a number of flags corresponding to the scan lines of the display device, wherein when the drawing device writes the display data to the display memory,
Reading the display data of the display memory prior to the writing, comparing the read data with the write data,
When different data is written by the comparison, a flag corresponding to a scan line including a dot corresponding to the address where the writing is performed is set, and a scan corresponding to the set flag is referred to by referring to the flag. The display data of all dots on the line is transferred from the display memory to the display and the set flags are reset. If none of the flags is set, the display is interlaced. A ferroelectric liquid crystal display device, wherein display data is transferred from the display memory to the display so as to perform display by scanning. 2. The display memory according to claim 1, wherein the display memory comprises a dual port RAM, wherein the comparison of the display data is performed in synchronism with the writing of the display data to one address of the display memory. 2. The ferroelectric liquid crystal display device according to claim 1, wherein the ferroelectric liquid crystal display device is performed in synchronization with display data transfer to the display device. 3. The ferroelectric liquid crystal display device according to claim 1, wherein one flag is provided for each of the plurality of scanning lines. 4. The ferroelectric liquid crystal display device according to claim 1, wherein one flag is provided for each scanning line. 5. The ferroelectric liquid crystal display device according to claim 1, wherein in the interlaced scanning, a scanning selection signal is supplied to the scanning electrodes of the display while skipping every four or more scanning lines. 6. In the interlaced scanning, two consecutive
6. The ferroelectric liquid crystal display device according to claim 5, wherein the non-adjacent scan line groups are selected in one field scan period to supply the scan selection signal. 7. A display memory for accumulating display data of each dot at an address corresponding to each dot of the display, a drawing unit for writing display data to the display memory, and displaying from the display memory to the display. A sequencer for transferring data, and a number of flags corresponding to the number of scan lines of the display device, wherein when the drawing device writes display data to the display memory,
Reading the display data of the display memory prior to the writing, comparing the read data with the write data,
When different data is written by the comparison, a flag corresponding to a scan line including a dot corresponding to the address where the writing is performed is set, and a scan corresponding to the set flag is referred to by referring to the flag. The display data of all dots on the line is transferred from the display memory to the display and the set flags are reset. If none of the flags is set, the display is interlaced. A display control device for transferring display data from said display memory to said display so as to display by scanning. 8. The display control device according to claim 7, wherein the number of said flags is one for each of said plurality of scanning lines. 9. The display control device according to claim 7, wherein the number of said flags is one per said scanning line. 10. The display control device according to claim 7, wherein in the interlaced scanning, a scanning selection signal is supplied to scanning electrodes of the display while skipping every four or more scanning lines. 11. The display control device according to claim 10, wherein in the interlaced scanning, the scanning selection signal is supplied by selecting a group of scanning lines that are not adjacent to each other in two consecutive field scanning periods.