JP2647984B2 - Disk recording and playback device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disc recording / reproducing apparatus, and more particularly to an ATIP recorded on, for example, a CD-WO (WRITE ONCE) disc.
The present invention relates to a disk recording / reproducing apparatus suitable for compensating for data loss.

[Conventional technology]

For example, spiral-shaped guide grooves (pre-grooves) are formed in advance on a write-once CD-WO disc on which the user can record on the disc only once. This guide groove
ATIP (Absolute Time In) modulated with bi-phase signal
Pregroove) data (absolute time data) is recorded by FM modulation at a carrier frequency of 22.05 kHz.

The format of ATIP data is 4 as shown in FIG.
It has a serial configuration of a bit synchronization signal, 8-bit minute data, 8-bit second data, 8-bit frame data, and 14-bit CRC data.

Of these, minute data, second data,
The frame data are all composed of two-digit BCD data, the minute data takes a value from 00 to 99, the second data takes a value from 00 to 59, and the frame data takes a value from 00 to 74.

The 22.05kHz carrier is used for CLV control of the spindle motor.

The ATIP data is read out by the ATIP data demodulation circuit when user data is recorded, and is used for forming time data in a subcode to be recorded together with the user data.

[Problems to be solved by the invention]

However, in the above-mentioned conventional technology, for example, CD-WO
When the ATIP data output from the ATIP data demodulation circuit is temporarily lost due to a scratch on the disc, etc., it is not possible to form an accurate subcode. For example, when searching for user data, an accurate search cannot be performed. There was a problem.

The present invention has been made in view of the above-described conventional problems, and provides a disk recording / reproducing apparatus that can always obtain accurate ATIP data regardless of a lack of ATIP data output from an ATIP data demodulation circuit. With that purpose.

[Means for solving the problem]

The disk recording / playback apparatus of the present invention has two operation modes, a preset mode and a counter mode, on the output side of an ATIP data demodulation circuit that performs demodulation of ATIP data recorded on a disk, frame synchronization detection, and error checking. A time counter for inputting ATIP data is provided.
The frame synchronization detection signal and error check signal output from the data demodulation circuit are input to the clock terminal and the mode switching signal input terminal of the time counter, and when recording the time code together with the user data on the disk, demodulation while recording It is characterized in that a time code for recording is created using data obtained by correcting the ATIP data obtained by the time counter.

〔Example〕

Next, one embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram showing an ATIP data demodulation system of a CD-WO disk recording / playback apparatus according to the present invention.

An RF amplifier 11 is connected to the output side of the optical pickup 10, and the RF amplifier 11 generates a tracking error signal.

The amplifier 12 is connected to the tracking error signal output terminal of the RF amplifier 11, and the tracking error signal is amplified.

The BPF 14 is connected to the output side of the amplifier 12, and an FM modulated wave component is extracted.

An FM demodulation circuit 16 is connected to the output side of the BPF
An FM demodulation of the modulated wave component is performed to generate a biphase signal.

An ATIP data demodulation circuit 18 is connected to the output side of the FM demodulation circuit 16 to demodulate ATIP data (absolute time data composed of minutes, seconds, and frames).

The ATIP data demodulation circuit 18 also performs a frame synchronization detection and an error check (CRC check), and outputs a frame synchronization detection signal and an error check signal (CRC check signal).

The ATIP data demodulation circuit 18 includes a bi-phase demodulation circuit 20,
Serial-parallel conversion circuits 22-26, latch circuits 28-3
2. Consists of an AND circuit 34.

The bi-phase demodulation circuit 20 is connected to the output side of the FM demodulation circuit 16 and performs demodulation of ATIP serial data from the bi-phase signal, frame synchronization detection, and error check using CRC data.

The biphase demodulation circuit 20 outputs ATIP serial data, a data read clock, a frame synchronization detection signal, and an error check signal.

The error check signal indicates an "H" level indicating an OK state when minute data, second data, and frame data for one frame are all correct, and indicates an error state when any of minute data, second data, or frame data has an error. An "L" level is output.

Here, the relationship between the ATIP serial data, the frame synchronization detection signal, the data read clock, and the error check signal is shown in the time chart of FIG.

The frame synchronization detection signal is output when the last bit of the frame synchronization signal in the ATIP serial data is output.

The data read clock is output during output of minute data, second data, and frame data in ATIP serial data.

The error check signal is the CRC in the ATIP serial data.
It is output as a result of the error check when the output of the last bit of the data ends, and continues until the output of the last bit of the CRC data of the next frame ends.

The output side of the ATIP serial data of the biphase demodulation circuit 20 has an 8-bit serial-parallel converter 22 to 26 each.
Are connected in series, and ATIP serial data is serially input according to a data read clock, and is output in parallel in units of 8 bits.

The latch circuits 28 to 32 are connected to the output sides of the serial-parallel converters 22 to 26, respectively. Then, the frame synchronization detection signal and the error check signal output from the biphase demodulation circuit 20 are input to the AND circuit 34, and the AND circuit 34
The output of 34 is used as a latch strobe signal for each latch circuit 28.
~ 32 have been entered.

When the error check signal is at the “H” level (the last 1
When the frame synchronization detection signal is input in a state where the ATIP data for the frame is correct), a latch strobe signal is output from the AND circuit 34, and the output of the serial-parallel converter 22 to 26 at that time is output to each of the latch circuits 28 to 32. AT latched in
Output as IP data.

The output of the latch circuit 32 is minute data, the output of the latch circuit 30 is second data, and the output of the latch circuit 28 is frame data.

The time counter 36 constituting the ATIP data interpolation circuit is connected to the ATIP data demodulation circuit 18 configured as described above.

This time counter 36 is a 75-base BCD counter 3 in which the output side of the latch circuit 28 is connected to the preset data input terminal.
8, the output side of the latch circuit 30 comprises a 60-base BCD counter 40 connected to the preset data input terminal, and the output side of the latch circuit 32 comprises a 100-base BCD counter 42 connected to the preset data input terminal. The carry signal output terminal is connected to the clock input terminal of the 60-digit BCD counter 40, and the carry signal output terminal of the 60-digit BCD counter 40 is set to 100 decimal.
It is connected to the clock input terminal of the BCD counter 42.

And, as a clock input terminal of the time counter 36,
The frame synchronization detection signal output from the bi-phase demodulation circuit 20 is input to the clock input terminal of the 75-base BCD counter 38, and each of the 75-base BCD counter 38, 60-base BCD counter 40, 100
An error check signal is input to the mode switching signal input terminal of the binary BCD counter 42.

Each 75 base BCD counter 38, 60 base BCD counter 40, 100 base BCD
The counter 42 has two modes, a preset mode and a count mode.
When the "H" level is input to the mode switching signal input terminal, the mode becomes the preset mode, in which the 8-bit data input from each of the latch circuits 28 to 32 is preset and output as it is. .

Conversely, when the "L" level is input to the mode switching signal input terminal, the count is incremented each time a rising edge of the pulse is input to the clock input terminal from the preset value at that time.

100 decimal BCD counter 42, 60 decimal counter 40, 75 decimal counter
The output of 38 is interpolation ATIP data, which is output to a system microcomputer or the like.

The output of the 100 decimal BCD counter 42 is the minute data, the 60 decimal counter
The output of 40 is second data, and the output of 75-base counter 38 is frame data.

Next, the operation of this embodiment will be described with reference to the time charts of FIGS.

First, a case where the CD-WO disc has no flaws and the demodulation of the ATIP data is normally performed will be described (see FIG. 2).

When recording user data, a detection signal of the optical pickup 10 is input to the RF amplifier 11, and a tracking error signal is output. After the tracking error signal is amplified by the amplifier 12, the BPF 14 extracts the FM modulated wave component.

The FM modulated wave component is demodulated by an FM demodulation circuit 16 into a biphase signal.

The biphase signal is input to the ATIP data demodulation circuit 18 where the ATIP data is demodulated.

In the ATIP data demodulation circuit 18, first, a biphase demodulation circuit 20 performs demodulation of ATIP serial data, frame synchronization detection, and error check.

The ATIP serial data is serial-read according to a data read clock output from the biphase demodulation circuit 20.
The data is sequentially transferred to the parallel conversion circuits 22, 24, and 26, and serial-parallel converted in units of 8 bits.

When the bi-phase demodulation circuit 20 finishes outputting the frame data, the minute data from the serial-parallel conversion circuit 26, the second data from the serial-parallel conversion circuit 24, the serial data
Frame data is output from the parallel conversion circuit 22.

The output of each serial-parallel conversion circuit 26, 24, 22 is
The signals are output to the latch circuits 32, 30, and 28, respectively.

Then, when the output of the CRC data from the bi-phase demodulation circuit 20 is completed, the data for one frame this time,
When the second data and the frame data are all correct, an “H” level error check signal indicating the OK state is output from the bi-phase demodulation circuit 20 to the AND circuit.

In this state, when the frame synchronization detection signal for the next frame is output from the bi-phase demodulation circuit 20 to the AND circuit 34, the latch strobe signal is output from the AND circuit 34 to the latch circuits 32, 30, and 28.

At this time, the latch circuits 32, 30, and 28 output minute data, second data, and frame data input from the serial-parallel conversion circuits 26, 24, and 22, respectively.

These ATIP data are correct data, and each 100-digit BCD counter 42 of the time counter 36, the 60-digit counter 40, and the 75-decimal
It is input to the BCD counter 38.

The mode switching signal input terminals of the 100-base BCD counter 42, 60-base counter 40, and 75-base BCD counter 38 of the time counter 36 receive an "H" level error check signal. Latch circuits 32, 30,
The minute data, second data, and frame data input from 28 are output as interpolated ATIP data as they are.

This interpolated ATIP data is correct data and is output to a system microcomputer or the like.

After outputting the frame synchronization detection signal, the biphase demodulation circuit 20 serially outputs minute data, second data, and frame data relating to a new frame. These data are supplied to the serial-parallel conversion circuits 26 and 2 as described above.
The data is transferred to 4, 22 for serial-parallel conversion. When each data is correct, the bi-phase demodulation circuit 20 sets the error check signal to “H” when the CRC data has been output.
Since it is left as it is, when the next frame synchronization detection signal is output, it is latched by the latch circuits 32, 30, and 28, and the output data to the time counter 36 changes.

Since the time counter 36 remains in the preset mode, the changed ATIP data is output as it is as correct interpolation ATIP data.

Hereinafter, similarly, when the CD-WO disc is not damaged and the ATIP data output from the ATIP data demodulation circuit 18 is correct, the time counter 36 is maintained in the preset mode state, and the correct ATIP data is directly used as interpolation ATIP data. Output to a microcomputer or the like.

On the other hand, a case where an error occurs in any of minute data, second data, and frame data when demodulating ATIP data of a certain frame due to a scratch on a CD-WO disc or the like (see FIG. 3) will be described.

At this time, the bi-phase demodulation circuit 20 drops the error check signal from “H” to “L” indicating an error state when the CRC data has been output.

For this reason, even if the frame synchronization detection signal for the next frame is output from the bi-phase demodulation circuit 20, the latch circuits 32, 30, and 28 do not perform the latch operation and output the ATIP data for the immediately preceding frame. to continue.

 Therefore, ATIP data will be lost.

On the other hand, in the time counter 36, when the error check signal input to the mode switching signal input terminal falls from “H” to “L”, the 100-base BCD counter 42, the 60-base BCD counter 40, 75
The hexadecimal BCD counter 38 stores the data corresponding to the data input to the preset data input terminal from the latch circuits 32, 30, and 28 at that time.
The mode is switched to the count mode with the second data and frame data as preset values, and then the clock input terminal of the time counter 36 (clock input terminal of the 75-base BCD counter 38)
When the next frame synchronization detection signal is input
The BCD counter 38 advances by one frame.

At this time, if the preset data of the 75-base BCD counter 38 is 74 in advance, it becomes 00, a carry signal is output to the clock input terminal of the 60-base BCD counter 40, and the second data is advanced by 1 second.

Similarly, at this time, if the preset data of the 60-hexadecimal BCD counter 40 is 59 in advance, it becomes 00, and the carry signal becomes 100.
Is output to the clock input terminal of the binary BCD counter 42, and the minute data is incremented by one minute.

Therefore, even if the ATIP data output from the ATIP data demodulation circuit 20 is not updated due to an error and is lost, the output of the time counter 36 is updated in synchronization with the frame. You can continue to output to.

After outputting the frame synchronization detection signal, the biphase demodulation circuit 20 serially outputs minute data, second data, and frame data relating to a new frame. These data are supplied to the serial-parallel conversion circuits 26 and 2 as described above.
The data is transferred to 4, 22 for serial-parallel conversion. When the error state still continues, the bi-phase demodulation circuit 20
Since the error check signal remains "L" when the CRC data has been output, the latch data of the latch circuits 32, 30 and 28 does not change even when the next frame synchronization detection signal is output.

At this time, since the time counter 36 remains in the count mode, the interpolation ATIP data is advanced by one frame at the point where the next frame synchronization detection signal is input, and interpolation is performed.

Hereinafter, similarly, when the ATIP data output from the ATIP data demodulation circuit 18 is in an error state due to a scratch on the CD-WO disc or the like, the time counter 36 is maintained in the count mode state, and the correct interpolation ATIP data formed by interpolation is obtained. Is output to the system microcomputer.

Thereafter, when the minute data, the second data, and the frame data become normal during the demodulation of the ATIP data of a certain frame, the error check signal changes from "L" to "H" when the CRC data has been output.

At this point, when the frame synchronization detection signal is subsequently output, the correct data output from the serial-parallel conversion circuits 26, 24, and 22 is latched by the latch circuits 32, 30, and 28, and the time counter 36 is used as ATIP data. Output to

The time counter 36 returns to the preset mode when the error check signal becomes “H”, and the latch circuits 32, 30,
The correct ATIP data output from 28 is output as it is to the system microcomputer as interpolation ATIP data.

According to this embodiment, the time counter 36 is provided on the output side of the ATIP data of the ATIP data demodulation circuit 18, and the frame synchronization detection signal and the error check signal output from the ATIP data demodulation circuit 18 are supplied to the clock input terminal of the time counter 36. And the mode switch signal input terminal, and the error check signal is OK.
In this state, the time counter 36 is in the preset mode.
The correct ATIP data output from the ATIP data demodulation circuit 18 is directly output as interpolation ATIP data, and when the error check signal becomes an error state, the time counter 36 sets the ATIP data input at that time as a preset value as a frame synchronization detection signal. The interpolation is performed step by step in accordance with the input of, so that even if an error occurs in the ATIP data output from the ATIP data demodulation circuit 18 due to a scratch on the CD-WO disc and the like and the data is temporarily lost, a continuous correct interpolation ATIP is performed. Data can be output, and a correct subcode can be recorded based on ATIP data when recording user data.

〔The invention's effect〕

According to the disk recording / reproducing apparatus of the present invention, a time counter is provided on the output side of the ATIP data demodulation circuit for the ATIP data, and the frame synchronization detection signal and the error check signal output from the ATIP data demodulation circuit are supplied to the clock terminal of the time counter. Input to the mode switching signal input terminal, and when recording subcode together with user data on the disc, create a time code for recording using data corrected by a time counter on demodulated ATIP data while recording. With this configuration, continuous and accurate interpolated ATIP data can be obtained regardless of temporary loss of ATIP data output from the ATIP data demodulation circuit due to disc scratches, etc., and the correct time code based on ATIP data when recording user data Can be recorded together. Therefore, the search can be correctly performed after the recording of the user data.

[Brief description of the drawings]

FIG. 1 is a block diagram of an ATIP data reproducing system of a CD-WO disk recording / reproducing apparatus according to one embodiment of the present invention, FIGS. 2 and 3 are time charts showing the operation of FIG. 1, and FIG. FIG. 4 is an explanatory diagram showing a format configuration of ATIP data. Explanation of main codes 18: ATIP data demodulation circuit, 36: time counter.

Claims (1)

(57) [Claims] 1. An output side of an ATIP data demodulation circuit for detecting a demodulated frame synchronization of an ATIP data recorded in advance on a recordable / reproducible disc and performing an error check, and has two operation modes, a preset mode and a counter mode. A time counter for inputting ATIP data is provided, and a frame synchronization detection signal and an error check signal output from the ATIP data demodulation circuit are input to a clock terminal and a mode switching signal input terminal of the time counter. A disc recording / reproducing apparatus, wherein when recording a subcode together with data, a time code for recording is created using data obtained by correcting ATIP data demodulated while recording by a time counter.